Re: [PATCH 03/11] PCI: tegra194: Fix Endpoint PERST# IRQ suspend race

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

On 14/10/26 7:44 pm, Manivannan Sadhasivam wrote:
> On 2026-09-23 12:52 +0530, Manikanta Maddireddy wrote:
>> Endpoint mode disables the PERST# IRQ during system suspend when the
>> link is down.  The old code checked ep_state before disabling the IRQ,
>> so the host could deassert PERST# in that window and the IRQ thread
>> could move the endpoint to EP_STATE_ENABLED after the suspend check had
>> already passed.
>>
> 
> What is the issue in this scenario?

Scenario is,
1) Tegra suspend to RAM initiated
2) PCIe suspend is executing
3) EP state is in disabled when "pcie->ep_state == EP_STATE_ENABLED" 
check is done.
4) EP PERST# deassert interrupt is received before pex_rst_irq is disabled.
5) Now suspend and PERST# deassert sequence is racing.>
>> Disable the PERST# IRQ before checking ep_state and re-enable it
>> immediately when suspend is rejected.
> 
> So EP will still miss the PERST# deassertion anyway. Overall, I see this PERST#
> handling logic in suspend as fragile. Since PERST# is asynchronous, it will be
> racy if you try to check the state and make any decision.
> 
> - Mani

Agree, once PCIe suspend is done, Tegra will not receive PERST# 
assert/deassert, this is expected.
I am trying solve SW race where suspend and EP PERST# executes in parallel.

- Manikanta

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