* [PATCH 01/20] dt-bindings: serial: snps-dw-apb-uart: Add Synaptics sl261x uart
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
@ 2026-09-29 6:13 ` Jisheng Zhang
2026-09-29 6:13 ` [PATCH 02/20] dt-bindings: i2c: dw: Add Synaptics sl261x i2c Jisheng Zhang
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:13 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add the compatible for the UARTs of the Synaptics SL261X, which are
compatible with the Synopsys DesignWare APB UART.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../devicetree/bindings/serial/snps-dw-apb-uart.yaml | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 664305de4986..7a80357230eb 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -34,7 +34,16 @@ allOf:
properties:
resets:
minItems: 2
- else:
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jh7110-uart
+ - syna,sl261x-uart
+ then:
properties:
resets:
maxItems: 1
@@ -80,6 +89,7 @@ properties:
- starfive,jh7100-hsuart
- starfive,jh7100-uart
- starfive,jh7110-uart
+ - syna,sl261x-uart
- ultrarisc,dp1000-uart
- const: snps,dw-apb-uart
- const: snps,dw-apb-uart
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 02/20] dt-bindings: i2c: dw: Add Synaptics sl261x i2c
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
2026-09-29 6:13 ` [PATCH 01/20] dt-bindings: serial: snps-dw-apb-uart: Add Synaptics sl261x uart Jisheng Zhang
@ 2026-09-29 6:13 ` Jisheng Zhang
2026-09-29 20:57 ` Andi Shyti
2026-09-29 6:14 ` [PATCH 03/20] spi: dt-bindings: snps,dw-apb-ssi: Add Synaptics sl261x spi Jisheng Zhang
` (18 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:13 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add the compatible for the Synaptics SL261X SoC I2C controllers, which
are compatible with the Synopsys DesignWare I2C.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index 467bdcbb8538..ca2921865b97 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -43,6 +43,7 @@ properties:
- mobileye,eyeq6lplus-i2c
- mscc,ocelot-i2c
- sophgo,sg2044-i2c
+ - syna,sl261x-i2c
- thead,th1520-i2c
- const: snps,designware-i2c
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 02/20] dt-bindings: i2c: dw: Add Synaptics sl261x i2c
2026-09-29 6:13 ` [PATCH 02/20] dt-bindings: i2c: dw: Add Synaptics sl261x i2c Jisheng Zhang
@ 2026-09-29 20:57 ` Andi Shyti
0 siblings, 0 replies; 31+ messages in thread
From: Andi Shyti @ 2026-09-29 20:57 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Alexandre Belloni, Frank Li,
Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
Hi Jisheng,
On Tue, Sep 29, 2026 at 02:13:59PM +0800, Jisheng Zhang wrote:
> Add the compatible for the Synaptics SL261X SoC I2C controllers, which
> are compatible with the Synopsys DesignWare I2C.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Thanks,
Andi
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 03/20] spi: dt-bindings: snps,dw-apb-ssi: Add Synaptics sl261x spi
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
2026-09-29 6:13 ` [PATCH 01/20] dt-bindings: serial: snps-dw-apb-uart: Add Synaptics sl261x uart Jisheng Zhang
2026-09-29 6:13 ` [PATCH 02/20] dt-bindings: i2c: dw: Add Synaptics sl261x i2c Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 04/20] dt-bindings: i3c: dw: support up to two reset lines Jisheng Zhang
` (17 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add the compatible for the Synaptics SL261X SoC SPI controllers, which
are compatible with the Synopsys DesignWare APB SSI.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index 1e70c6804d5d..7090de9fa8d3 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -62,6 +62,7 @@ properties:
- mscc,ocelot-spi
- mscc,jaguar2-spi
- sophgo,sg2042-spi
+ - syna,sl261x-spi
- thead,th1520-spi
- const: snps,dw-apb-ssi
- description: Vendor controllers compatible with v1.01a
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 04/20] dt-bindings: i3c: dw: support up to two reset lines
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (2 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 03/20] spi: dt-bindings: snps,dw-apb-ssi: Add Synaptics sl261x spi Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 19:40 ` Conor Dooley
2026-09-29 6:14 ` [PATCH 05/20] i3c: dw: switch to array-based exclusive reset control Jisheng Zhang
` (16 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
The Synopsys DesignWare I3C master controller can have multiple reset
lines, such as core reset, apb reset, and dma reset.
Update the DT binding documentation to increase maxItems for the resets
property to 2.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
index dc7ee38001d6..dcc21a7ab4c4 100644
--- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
@@ -39,7 +39,7 @@ properties:
maxItems: 1
resets:
- maxItems: 1
+ maxItems: 2
power-domains:
maxItems: 1
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 04/20] dt-bindings: i3c: dw: support up to two reset lines
2026-09-29 6:14 ` [PATCH 04/20] dt-bindings: i3c: dw: support up to two reset lines Jisheng Zhang
@ 2026-09-29 19:40 ` Conor Dooley
0 siblings, 0 replies; 31+ messages in thread
From: Conor Dooley @ 2026-09-29 19:40 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 1144 bytes --]
On Tue, Sep 29, 2026 at 02:14:01PM +0800, Jisheng Zhang wrote:
> The Synopsys DesignWare I3C master controller can have multiple reset
> lines, such as core reset, apb reset, and dma reset.
>
> Update the DT binding documentation to increase maxItems for the resets
> property to 2.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Could you add a conditional section alongside this change to restrict
the altera device to one please?
pw-bot: changes-requested
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> index dc7ee38001d6..dcc21a7ab4c4 100644
> --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
> @@ -39,7 +39,7 @@ properties:
> maxItems: 1
>
> resets:
> - maxItems: 1
> + maxItems: 2
>
> power-domains:
> maxItems: 1
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 05/20] i3c: dw: switch to array-based exclusive reset control
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (3 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 04/20] dt-bindings: i3c: dw: support up to two reset lines Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 15:01 ` Frank Li
2026-09-29 6:14 ` [PATCH 06/20] dt-bindings: i3c: Add Synaptics sl261x i3c Jisheng Zhang
` (15 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
The Synopsys DesignWare I3C master controller can have multiple reset
lines, such as a core reset and APB reset.
Refactor the driver to use devm_reset_control_array_get_exclusive()
instead of a single named reset handle. This automatically manages all
resets allocated to the device node sequentially.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/i3c/master/dw-i3c-master.c | 24 ++++++++++++++++++------
drivers/i3c/master/dw-i3c-master.h | 2 +-
2 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index 4563d8761ba0..1c6c870f5bb3 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -1657,6 +1657,11 @@ static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = {
.set_dat_ibi = dw_i3c_platform_set_dat_ibi_nop,
};
+static void dw_i3c_resets_assert(void *data)
+{
+ reset_control_assert(data);
+}
+
int dw_i3c_common_probe(struct dw_i3c_master *master,
struct platform_device *pdev)
{
@@ -1696,10 +1701,17 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
if (IS_ERR(master->pclk))
return PTR_ERR(master->pclk);
- master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
- NULL);
- if (IS_ERR(master->core_rst))
- return PTR_ERR(master->core_rst);
+ master->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
+ if (IS_ERR(master->resets))
+ return PTR_ERR(master->resets);
+
+ ret = reset_control_deassert(master->resets);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(&pdev->dev, dw_i3c_resets_assert, master->resets);
+ if (ret)
+ return ret;
spin_lock_init(&master->xferqueue.lock);
INIT_LIST_HEAD(&master->xferqueue.list);
@@ -1873,7 +1885,7 @@ static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev)
dw_i3c_master_disable(master);
- reset_control_assert(master->core_rst);
+ reset_control_assert(master->resets);
dw_i3c_master_disable_clks(master);
pinctrl_pm_select_sleep_state(dev);
return 0;
@@ -1885,7 +1897,7 @@ static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev)
pinctrl_pm_select_default_state(dev);
dw_i3c_master_enable_clks(master);
- reset_control_deassert(master->core_rst);
+ reset_control_deassert(master->resets);
dw_i3c_master_set_intr_regs(master);
dw_i3c_master_restore_timing_regs(master);
diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c-master.h
index 17ad817d1f8e..f5b4491b247a 100644
--- a/drivers/i3c/master/dw-i3c-master.h
+++ b/drivers/i3c/master/dw-i3c-master.h
@@ -36,7 +36,7 @@ struct dw_i3c_master {
} xferqueue;
struct dw_i3c_master_caps caps;
void __iomem *regs;
- struct reset_control *core_rst;
+ struct reset_control *resets;
struct clk *core_clk;
struct clk *pclk;
char version[5];
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 05/20] i3c: dw: switch to array-based exclusive reset control
2026-09-29 6:14 ` [PATCH 05/20] i3c: dw: switch to array-based exclusive reset control Jisheng Zhang
@ 2026-09-29 15:01 ` Frank Li
0 siblings, 0 replies; 31+ messages in thread
From: Frank Li @ 2026-09-29 15:01 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
On Tue, Sep 29, 2026 at 02:14:02PM +0800, Jisheng Zhang wrote:
> The Synopsys DesignWare I3C master controller can have multiple reset
> lines, such as a core reset and APB reset.
>
> Refactor the driver to use devm_reset_control_array_get_exclusive()
> instead of a single named reset handle. This automatically manages all
> resets allocated to the device node sequentially.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/i3c/master/dw-i3c-master.c | 24 ++++++++++++++++++------
> drivers/i3c/master/dw-i3c-master.h | 2 +-
> 2 files changed, 19 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 4563d8761ba0..1c6c870f5bb3 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -1657,6 +1657,11 @@ static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = {
> .set_dat_ibi = dw_i3c_platform_set_dat_ibi_nop,
> };
>
> +static void dw_i3c_resets_assert(void *data)
> +{
> + reset_control_assert(data);
> +}
> +
> int dw_i3c_common_probe(struct dw_i3c_master *master,
> struct platform_device *pdev)
> {
> @@ -1696,10 +1701,17 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
> if (IS_ERR(master->pclk))
> return PTR_ERR(master->pclk);
>
> - master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
> - NULL);
> - if (IS_ERR(master->core_rst))
> - return PTR_ERR(master->core_rst);
> + master->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
> + if (IS_ERR(master->resets))
> + return PTR_ERR(master->resets);
> +
> + ret = reset_control_deassert(master->resets);
> + if (ret)
> + return ret;
> +
> + ret = devm_add_action_or_reset(&pdev->dev, dw_i3c_resets_assert, master->resets);
> + if (ret)
> + return ret;
>
> spin_lock_init(&master->xferqueue.lock);
> INIT_LIST_HEAD(&master->xferqueue.list);
> @@ -1873,7 +1885,7 @@ static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev)
>
> dw_i3c_master_disable(master);
>
> - reset_control_assert(master->core_rst);
> + reset_control_assert(master->resets);
> dw_i3c_master_disable_clks(master);
> pinctrl_pm_select_sleep_state(dev);
> return 0;
> @@ -1885,7 +1897,7 @@ static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev)
>
> pinctrl_pm_select_default_state(dev);
> dw_i3c_master_enable_clks(master);
> - reset_control_deassert(master->core_rst);
> + reset_control_deassert(master->resets);
>
> dw_i3c_master_set_intr_regs(master);
> dw_i3c_master_restore_timing_regs(master);
> diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c-master.h
> index 17ad817d1f8e..f5b4491b247a 100644
> --- a/drivers/i3c/master/dw-i3c-master.h
> +++ b/drivers/i3c/master/dw-i3c-master.h
> @@ -36,7 +36,7 @@ struct dw_i3c_master {
> } xferqueue;
> struct dw_i3c_master_caps caps;
> void __iomem *regs;
> - struct reset_control *core_rst;
> + struct reset_control *resets;
> struct clk *core_clk;
> struct clk *pclk;
> char version[5];
> --
> 2.53.0
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 06/20] dt-bindings: i3c: Add Synaptics sl261x i3c
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (4 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 05/20] i3c: dw: switch to array-based exclusive reset control Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 07/20] arm64: kconfig: let ARCH_BERLIN cover Synaptics arm64 SoCs Jisheng Zhang
` (14 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add the compatible for the Synaptics SL261X SoC I3C controller, which
is compatible with the Synopsys DesignWare I3C.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
index dcc21a7ab4c4..bd08d048d44b 100644
--- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
@@ -17,7 +17,9 @@ properties:
oneOf:
- const: snps,dw-i3c-master-1.00a
- items:
- - const: altr,agilex5-dw-i3c-master
+ - enum:
+ - altr,agilex5-dw-i3c-master
+ - syna,sl261x-i3c
- const: snps,dw-i3c-master-1.00a
reg:
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 07/20] arm64: kconfig: let ARCH_BERLIN cover Synaptics arm64 SoCs
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (5 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 06/20] dt-bindings: i3c: Add Synaptics sl261x i3c Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 08/20] dt-bindings: reset: add Synaptics SL261X SoCs Jisheng Zhang
` (13 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Extend ARCH_BERLIN to cover Synaptics arm64 SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/arm64/Kconfig.platforms | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index d2acfac73003..1c0747555a57 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -108,13 +108,13 @@ config ARCH_BRCMSTB
endif
config ARCH_BERLIN
- bool "Marvell Berlin SoC Family"
+ bool "Synaptics/Marvell Berlin SoC Family"
select DW_APB_ICTL
select DW_APB_TIMER_OF
select GPIOLIB
select PINCTRL
help
- This enables support for Marvell Berlin SoC Family
+ This enables support for Synaptics SoCs or Marvell Berlin SoC Family
config ARCH_BITMAIN
bool "Bitmain SoC Platforms"
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 08/20] dt-bindings: reset: add Synaptics SL261X SoCs
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (6 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 07/20] arm64: kconfig: let ARCH_BERLIN cover Synaptics arm64 SoCs Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 19:44 ` Conor Dooley
2026-09-29 6:14 ` [PATCH 09/20] reset: add Synaptics SL261x reset support Jisheng Zhang
` (12 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add device tree bindings for the resets on Synaptics SL261X SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../bindings/reset/syna,sl261x-reset.yaml | 40 ++++++++++
include/dt-bindings/reset/syna,sl261x-reset.h | 80 +++++++++++++++++++
2 files changed, 120 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml
create mode 100644 include/dt-bindings/reset/syna,sl261x-reset.h
diff --git a/Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml b/Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml
new file mode 100644
index 000000000000..8cfec17df800
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2026 Synaptics Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/syna,sl261x-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synaptics SL261X reset controller
+
+maintainers:
+ - Jisheng Zhang <jszhang@kernel.org>
+
+description: The reset controller node must be a sub-node of the chip
+ controller node on SL261X SoCs.
+
+properties:
+ compatible:
+ enum:
+ - syna,sl261x-soc-reset
+ - syna,sl261x-system-reset
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ chip: chip-control@f7e10000 {
+ reg = <0xf7e10000 0x1000>;
+
+ chip_rst: reset {
+ compatible = "syna,sl261x-soc-reset";
+ #reset-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/reset/syna,sl261x-reset.h b/include/dt-bindings/reset/syna,sl261x-reset.h
new file mode 100644
index 000000000000..7034f58aae5b
--- /dev/null
+++ b/include/dt-bindings/reset/syna,sl261x-reset.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2026 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#ifndef _DT_BINDINGS_SL261X_RESET_H
+#define _DT_BINDINGS_SL261X_RESET_H
+
+/* ACPU subsystem */
+#define RST_SOC_SDIO0 0
+#define RST_SOC_USB0 1
+#define RST_SOC_EMMC 2
+#define RST_SOC_GETH0 3
+#define RST_SOC_SDIO1 4
+#define RST_SOC_USB1 5
+#define RST_SOC_GETH1 6
+#define RST_SOC_USB0PHY 7
+#define RST_SOC_USB0CORE 8
+#define RST_SOC_USB0MAHB 9
+#define RST_SOC_USB1PHY 10
+#define RST_SOC_USB1CORE 11
+#define RST_SOC_USB1MAHB 12
+#define RST_SOC_UART0 13
+#define RST_SOC_UART1 14
+#define RST_SOC_UART2 15
+#define RST_SOC_UART3 16
+#define RST_SOC_I2C0 17
+#define RST_SOC_I2C1 18
+#define RST_SOC_SPI0 19
+#define RST_SOC_SPI1 20
+#define RST_SOC_SPI2 21
+#define RST_SOC_SPI3 22
+#define RST_SOC_APBTIMERS 23
+#define RST_SOC_APBSYSCNT 24
+#define RST_SOC_APBWDT 25
+#define RST_SOC_APBGPIO 26
+#define RST_SOC_APBDMA 27
+#define RST_SOC_GPUCORE 28
+#define RST_SOC_NPUCORE 29
+#define RST_SOC_AVIOAIOG 30
+#define RST_SOC_AVIOVPPG 31
+#define RST_SOC_AVIOVIPG 32
+
+/* system subsystem */
+#define RST_SM_ADCCORE 0
+#define RST_SM_ADCPRST 1
+#define RST_SM_CAN0PRST 2
+#define RST_SM_CAN0SRST 3
+#define RST_SM_CAN1PRST 4
+#define RST_SM_CAN1SRST 5
+#define RST_SM_GPIOPRST 6
+#define RST_SM_GPIOSRST 7
+#define RST_SM_I2CM0PRST 8
+#define RST_SM_I2CM0SRST 9
+#define RST_SM_I2CM1PRST 10
+#define RST_SM_I2CM1SRST 11
+#define RST_SM_I3CPRST 12
+#define RST_SM_I3CSRST 13
+#define RST_SM_PDMPRST 14
+#define RST_SM_PDMSRST 15
+#define RST_SM_PVTHSRST 16
+#define RST_SM_PVTPRST 17
+#define RST_SM_PWMPERIRST 18
+#define RST_SM_PWMPRST 19
+#define RST_SM_SPIMPRST 20
+#define RST_SM_SPIMSRST 21
+#define RST_SM_SPISPRST 22
+#define RST_SM_SPISSRST 23
+#define RST_SM_UART0PRST 24
+#define RST_SM_UART0SRST 25
+#define RST_SM_UART1PRST 26
+#define RST_SM_UART1SRST 27
+#define RST_SM_UART2PRST 28
+#define RST_SM_UART2SRST 29
+#define RST_SM_UART3PRST 30
+#define RST_SM_UART3SRST 31
+
+#endif /* _DT_BINDINGS_SL261X_RESET_H */
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 08/20] dt-bindings: reset: add Synaptics SL261X SoCs
2026-09-29 6:14 ` [PATCH 08/20] dt-bindings: reset: add Synaptics SL261X SoCs Jisheng Zhang
@ 2026-09-29 19:44 ` Conor Dooley
0 siblings, 0 replies; 31+ messages in thread
From: Conor Dooley @ 2026-09-29 19:44 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 4729 bytes --]
On Tue, Sep 29, 2026 at 02:14:05PM +0800, Jisheng Zhang wrote:
> Add device tree bindings for the resets on Synaptics SL261X SoCs.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> .../bindings/reset/syna,sl261x-reset.yaml | 40 ++++++++++
> include/dt-bindings/reset/syna,sl261x-reset.h | 80 +++++++++++++++++++
> 2 files changed, 120 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml
> create mode 100644 include/dt-bindings/reset/syna,sl261x-reset.h
>
> diff --git a/Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml b/Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml
> new file mode 100644
> index 000000000000..8cfec17df800
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2026 Synaptics Incorporated
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/syna,sl261x-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synaptics SL261X reset controller
> +
> +maintainers:
> + - Jisheng Zhang <jszhang@kernel.org>
> +
> +description: The reset controller node must be a sub-node of the chip
> + controller node on SL261X SoCs.
> +
> +properties:
> + compatible:
> + enum:
> + - syna,sl261x-soc-reset
> + - syna,sl261x-system-reset
> +
> + "#reset-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + chip: chip-control@f7e10000 {
> + reg = <0xf7e10000 0x1000>;
> +
> + chip_rst: reset {
> + compatible = "syna,sl261x-soc-reset";
> + #reset-cells = <1>;
> + };
Why can't this just be part of the parent node?
From a quick check of the dts, the node with this subnode didn't also
have a system-reset node too, so there's no conflict or anything of that
nature.
> + };
> diff --git a/include/dt-bindings/reset/syna,sl261x-reset.h b/include/dt-bindings/reset/syna,sl261x-reset.h
> new file mode 100644
> index 000000000000..7034f58aae5b
> --- /dev/null
> +++ b/include/dt-bindings/reset/syna,sl261x-reset.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2026 Synaptics Incorporated
> + *
> + * Author: Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +#ifndef _DT_BINDINGS_SL261X_RESET_H
> +#define _DT_BINDINGS_SL261X_RESET_H
> +
> +/* ACPU subsystem */
> +#define RST_SOC_SDIO0 0
> +#define RST_SOC_USB0 1
> +#define RST_SOC_EMMC 2
> +#define RST_SOC_GETH0 3
> +#define RST_SOC_SDIO1 4
> +#define RST_SOC_USB1 5
> +#define RST_SOC_GETH1 6
> +#define RST_SOC_USB0PHY 7
> +#define RST_SOC_USB0CORE 8
> +#define RST_SOC_USB0MAHB 9
> +#define RST_SOC_USB1PHY 10
> +#define RST_SOC_USB1CORE 11
> +#define RST_SOC_USB1MAHB 12
> +#define RST_SOC_UART0 13
> +#define RST_SOC_UART1 14
> +#define RST_SOC_UART2 15
> +#define RST_SOC_UART3 16
> +#define RST_SOC_I2C0 17
> +#define RST_SOC_I2C1 18
> +#define RST_SOC_SPI0 19
> +#define RST_SOC_SPI1 20
> +#define RST_SOC_SPI2 21
> +#define RST_SOC_SPI3 22
> +#define RST_SOC_APBTIMERS 23
> +#define RST_SOC_APBSYSCNT 24
> +#define RST_SOC_APBWDT 25
> +#define RST_SOC_APBGPIO 26
> +#define RST_SOC_APBDMA 27
> +#define RST_SOC_GPUCORE 28
> +#define RST_SOC_NPUCORE 29
> +#define RST_SOC_AVIOAIOG 30
> +#define RST_SOC_AVIOVPPG 31
> +#define RST_SOC_AVIOVIPG 32
> +
> +/* system subsystem */
> +#define RST_SM_ADCCORE 0
> +#define RST_SM_ADCPRST 1
> +#define RST_SM_CAN0PRST 2
> +#define RST_SM_CAN0SRST 3
> +#define RST_SM_CAN1PRST 4
> +#define RST_SM_CAN1SRST 5
> +#define RST_SM_GPIOPRST 6
> +#define RST_SM_GPIOSRST 7
> +#define RST_SM_I2CM0PRST 8
> +#define RST_SM_I2CM0SRST 9
> +#define RST_SM_I2CM1PRST 10
> +#define RST_SM_I2CM1SRST 11
> +#define RST_SM_I3CPRST 12
> +#define RST_SM_I3CSRST 13
> +#define RST_SM_PDMPRST 14
> +#define RST_SM_PDMSRST 15
> +#define RST_SM_PVTHSRST 16
> +#define RST_SM_PVTPRST 17
> +#define RST_SM_PWMPERIRST 18
> +#define RST_SM_PWMPRST 19
> +#define RST_SM_SPIMPRST 20
> +#define RST_SM_SPIMSRST 21
> +#define RST_SM_SPISPRST 22
> +#define RST_SM_SPISSRST 23
> +#define RST_SM_UART0PRST 24
> +#define RST_SM_UART0SRST 25
> +#define RST_SM_UART1PRST 26
> +#define RST_SM_UART1SRST 27
> +#define RST_SM_UART2PRST 28
> +#define RST_SM_UART2SRST 29
> +#define RST_SM_UART3PRST 30
> +#define RST_SM_UART3SRST 31
> +
> +#endif /* _DT_BINDINGS_SL261X_RESET_H */
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 09/20] reset: add Synaptics SL261x reset support
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (7 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 08/20] dt-bindings: reset: add Synaptics SL261X SoCs Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 10/20] pinctrl: berlin: use u16 instead of u8 for the offset Jisheng Zhang
` (11 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add support for reset controller in Synaptics SL261X SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/reset/Kconfig | 6 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-sl261x.c | 224 +++++++++++++++++++++++++++++++++++
3 files changed, 231 insertions(+)
create mode 100644 drivers/reset/reset-sl261x.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 3168ab1eea88..0e8424ede7fa 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -348,6 +348,12 @@ config RESET_SUNXI
help
This enables the reset driver for Allwinner SoCs.
+config RESET_SL261X
+ tristate "Synaptics SL261X Reset Driver"
+ depends on ARCH_BERLIN || COMPILE_TEST
+ help
+ This enables the reset controller driver for Synaptics SL261X SoCs.
+
config RESET_TENSTORRENT_ATLANTIS
tristate "Tenstorrent atlantis reset driver"
depends on ARCH_TENSTORRENT || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 45ad17062462..f3a46f2176db 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_RESET_SKY1_AUDSS) += reset-sky1-audss.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_RESET_SL261X) += reset-sl261x.o
obj-$(CONFIG_RESET_TENSTORRENT_ATLANTIS) += reset-tenstorrent-atlantis.o
obj-$(CONFIG_RESET_TH1520) += reset-th1520.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-sl261x.c b/drivers/reset/reset-sl261x.c
new file mode 100644
index 000000000000..aed22f7d56db
--- /dev/null
+++ b/drivers/reset/reset-sl261x.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Synaptics Incorporated
+ *
+ * Synaptics SL261X reset driver
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/reset/syna,sl261x-reset.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+/* SL261X ACPU subsystem */
+#define SL261X_GBL_PERIFRESET 0x350
+#define SL261X_GBL_PERIFSTICKYRESET 0x360
+#define SL261X_GBL_APBPERIFRESET 0x370
+#define SL261X_GBL_TOPSTICKYRESET 0x378
+#define SL261X_GBL_AVIOSTICKYRESET 0x37c
+
+/* SL261X system subsystem */
+#define SL261X_SMGBL_STICKYRST0 0x400
+
+#define to_sl261x_reset_priv(p) container_of((p), struct sl261x_reset_priv, rcdev)
+
+#define SL261X_RESET(id, reg, bit, sticky)[id] = { reg, BIT(bit), sticky }
+
+struct sl261x_reset_cfg {
+ u32 reg;
+ u32 bit;
+ bool sticky;
+};
+
+struct sl261x_reset_data {
+ const struct sl261x_reset_cfg *cfgs;
+ size_t num;
+};
+
+struct sl261x_reset_priv {
+ struct regmap *regmap;
+ const struct sl261x_reset_cfg *cfgs;
+ struct reset_controller_dev rcdev;
+};
+
+static const struct sl261x_reset_cfg sl261x_reset_cfgs[] = {
+ SL261X_RESET(RST_SOC_SDIO0, SL261X_GBL_PERIFRESET, 2, false),
+ SL261X_RESET(RST_SOC_USB0, SL261X_GBL_PERIFRESET, 4, false),
+ SL261X_RESET(RST_SOC_EMMC, SL261X_GBL_PERIFRESET, 5, false),
+ SL261X_RESET(RST_SOC_GETH0, SL261X_GBL_PERIFRESET, 6, false),
+ SL261X_RESET(RST_SOC_SDIO1, SL261X_GBL_PERIFRESET, 7, false),
+ SL261X_RESET(RST_SOC_USB1, SL261X_GBL_PERIFRESET, 8, false),
+ SL261X_RESET(RST_SOC_GETH1, SL261X_GBL_PERIFRESET, 9, false),
+ SL261X_RESET(RST_SOC_USB0PHY, SL261X_GBL_PERIFSTICKYRESET, 0, true),
+ SL261X_RESET(RST_SOC_USB0CORE, SL261X_GBL_PERIFSTICKYRESET, 1, true),
+ SL261X_RESET(RST_SOC_USB0MAHB, SL261X_GBL_PERIFSTICKYRESET, 2, true),
+ SL261X_RESET(RST_SOC_USB1PHY, SL261X_GBL_PERIFSTICKYRESET, 3, true),
+ SL261X_RESET(RST_SOC_USB1CORE, SL261X_GBL_PERIFSTICKYRESET, 4, true),
+ SL261X_RESET(RST_SOC_USB1MAHB, SL261X_GBL_PERIFSTICKYRESET, 5, true),
+ SL261X_RESET(RST_SOC_UART0, SL261X_GBL_APBPERIFRESET, 0, false),
+ SL261X_RESET(RST_SOC_UART1, SL261X_GBL_APBPERIFRESET, 1, false),
+ SL261X_RESET(RST_SOC_UART2, SL261X_GBL_APBPERIFRESET, 2, false),
+ SL261X_RESET(RST_SOC_UART3, SL261X_GBL_APBPERIFRESET, 3, false),
+ SL261X_RESET(RST_SOC_I2C0, SL261X_GBL_APBPERIFRESET, 4, false),
+ SL261X_RESET(RST_SOC_I2C1, SL261X_GBL_APBPERIFRESET, 5, false),
+ SL261X_RESET(RST_SOC_SPI0, SL261X_GBL_APBPERIFRESET, 6, false),
+ SL261X_RESET(RST_SOC_SPI1, SL261X_GBL_APBPERIFRESET, 7, false),
+ SL261X_RESET(RST_SOC_SPI2, SL261X_GBL_APBPERIFRESET, 8, false),
+ SL261X_RESET(RST_SOC_SPI3, SL261X_GBL_APBPERIFRESET, 9, false),
+ SL261X_RESET(RST_SOC_APBTIMERS, SL261X_GBL_APBPERIFRESET, 10, false),
+ SL261X_RESET(RST_SOC_APBSYSCNT, SL261X_GBL_APBPERIFRESET, 11, false),
+ SL261X_RESET(RST_SOC_APBWDT, SL261X_GBL_APBPERIFRESET, 12, false),
+ SL261X_RESET(RST_SOC_APBGPIO, SL261X_GBL_APBPERIFRESET, 13, false),
+ SL261X_RESET(RST_SOC_APBDMA, SL261X_GBL_APBPERIFRESET, 14, false),
+ SL261X_RESET(RST_SOC_GPUCORE, SL261X_GBL_TOPSTICKYRESET, 0, true),
+ SL261X_RESET(RST_SOC_NPUCORE, SL261X_GBL_TOPSTICKYRESET, 1, true),
+ SL261X_RESET(RST_SOC_AVIOAIOG, SL261X_GBL_AVIOSTICKYRESET, 0, true),
+ SL261X_RESET(RST_SOC_AVIOVPPG, SL261X_GBL_AVIOSTICKYRESET, 1, true),
+ SL261X_RESET(RST_SOC_AVIOVIPG, SL261X_GBL_AVIOSTICKYRESET, 2, true),
+};
+
+static const struct sl261x_reset_cfg sl261x_system_reset_cfgs[] = {
+ SL261X_RESET(RST_SM_ADCCORE, SL261X_SMGBL_STICKYRST0, 0, true),
+ SL261X_RESET(RST_SM_ADCPRST, SL261X_SMGBL_STICKYRST0, 1, true),
+ SL261X_RESET(RST_SM_CAN0PRST, SL261X_SMGBL_STICKYRST0, 2, true),
+ SL261X_RESET(RST_SM_CAN0SRST, SL261X_SMGBL_STICKYRST0, 3, true),
+ SL261X_RESET(RST_SM_CAN1PRST, SL261X_SMGBL_STICKYRST0, 4, true),
+ SL261X_RESET(RST_SM_CAN1SRST, SL261X_SMGBL_STICKYRST0, 5, true),
+ SL261X_RESET(RST_SM_GPIOPRST, SL261X_SMGBL_STICKYRST0, 6, true),
+ SL261X_RESET(RST_SM_GPIOSRST, SL261X_SMGBL_STICKYRST0, 7, true),
+ SL261X_RESET(RST_SM_I2CM0PRST, SL261X_SMGBL_STICKYRST0, 8, true),
+ SL261X_RESET(RST_SM_I2CM0SRST, SL261X_SMGBL_STICKYRST0, 9, true),
+ SL261X_RESET(RST_SM_I2CM1PRST, SL261X_SMGBL_STICKYRST0, 10, true),
+ SL261X_RESET(RST_SM_I2CM1SRST, SL261X_SMGBL_STICKYRST0, 11, true),
+ SL261X_RESET(RST_SM_I3CPRST, SL261X_SMGBL_STICKYRST0, 12, true),
+ SL261X_RESET(RST_SM_I3CSRST, SL261X_SMGBL_STICKYRST0, 13, true),
+ SL261X_RESET(RST_SM_PDMPRST, SL261X_SMGBL_STICKYRST0, 14, true),
+ SL261X_RESET(RST_SM_PDMSRST, SL261X_SMGBL_STICKYRST0, 15, true),
+ SL261X_RESET(RST_SM_PVTHSRST, SL261X_SMGBL_STICKYRST0, 16, true),
+ SL261X_RESET(RST_SM_PVTPRST, SL261X_SMGBL_STICKYRST0, 17, true),
+ SL261X_RESET(RST_SM_PWMPERIRST, SL261X_SMGBL_STICKYRST0, 18, true),
+ SL261X_RESET(RST_SM_PWMPRST, SL261X_SMGBL_STICKYRST0, 19, true),
+ SL261X_RESET(RST_SM_SPIMPRST, SL261X_SMGBL_STICKYRST0, 20, true),
+ SL261X_RESET(RST_SM_SPIMSRST, SL261X_SMGBL_STICKYRST0, 21, true),
+ SL261X_RESET(RST_SM_SPISPRST, SL261X_SMGBL_STICKYRST0, 22, true),
+ SL261X_RESET(RST_SM_SPISSRST, SL261X_SMGBL_STICKYRST0, 23, true),
+ SL261X_RESET(RST_SM_UART0PRST, SL261X_SMGBL_STICKYRST0, 24, true),
+ SL261X_RESET(RST_SM_UART0SRST, SL261X_SMGBL_STICKYRST0, 25, true),
+ SL261X_RESET(RST_SM_UART1PRST, SL261X_SMGBL_STICKYRST0, 26, true),
+ SL261X_RESET(RST_SM_UART1SRST, SL261X_SMGBL_STICKYRST0, 27, true),
+ SL261X_RESET(RST_SM_UART2PRST, SL261X_SMGBL_STICKYRST0, 28, true),
+ SL261X_RESET(RST_SM_UART2SRST, SL261X_SMGBL_STICKYRST0, 29, true),
+ SL261X_RESET(RST_SM_UART3PRST, SL261X_SMGBL_STICKYRST0, 30, true),
+ SL261X_RESET(RST_SM_UART3SRST, SL261X_SMGBL_STICKYRST0, 31, true),
+};
+
+static const struct sl261x_reset_data sl261x_reset_data = {
+ .cfgs = sl261x_reset_cfgs,
+ .num = ARRAY_SIZE(sl261x_reset_cfgs),
+};
+
+static const struct sl261x_reset_data sl261x_system_reset_data = {
+ .cfgs = sl261x_system_reset_cfgs,
+ .num = ARRAY_SIZE(sl261x_system_reset_cfgs),
+};
+
+static int sl261x_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct sl261x_reset_priv *priv = to_sl261x_reset_priv(rcdev);
+ const struct sl261x_reset_cfg *cfg = &priv->cfgs[id];
+
+ if (!cfg->sticky)
+ return -EINVAL;
+
+ return regmap_clear_bits(priv->regmap, cfg->reg, cfg->bit);
+}
+
+static int sl261x_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct sl261x_reset_priv *priv = to_sl261x_reset_priv(rcdev);
+ const struct sl261x_reset_cfg *cfg = &priv->cfgs[id];
+
+ if (!cfg->sticky)
+ return -EINVAL;
+
+ return regmap_set_bits(priv->regmap, cfg->reg, cfg->bit);
+}
+
+static int sl261x_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct sl261x_reset_priv *priv = to_sl261x_reset_priv(rcdev);
+ const struct sl261x_reset_cfg *cfg = &priv->cfgs[id];
+
+ if (cfg->sticky) {
+ regmap_clear_bits(priv->regmap, cfg->reg, cfg->bit);
+ usleep_range(10, 15);
+ return regmap_set_bits(priv->regmap, cfg->reg, cfg->bit);
+ }
+
+ return regmap_set_bits(priv->regmap, cfg->reg, cfg->bit);
+}
+
+static const struct reset_control_ops sl261x_reset_ops = {
+ .reset = sl261x_reset_reset,
+ .assert = sl261x_reset_assert,
+ .deassert = sl261x_reset_deassert,
+};
+
+static int sl261x2_reset_probe(struct platform_device *pdev)
+{
+ struct device_node *parent_np;
+ struct sl261x_reset_priv *priv;
+ const struct sl261x_reset_data *data = device_get_match_data(&pdev->dev);
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ parent_np = of_get_parent(pdev->dev.of_node);
+ priv->regmap = syscon_node_to_regmap(parent_np);
+ of_node_put(parent_np);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->rcdev.owner = THIS_MODULE;
+ priv->rcdev.ops = &sl261x_reset_ops;
+ priv->rcdev.of_node = pdev->dev.of_node;
+ priv->rcdev.of_reset_n_cells = 1;
+ priv->rcdev.nr_resets = data->num;
+ priv->cfgs = data->cfgs;
+
+ return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
+}
+
+static const struct of_device_id sl261x_reset_dt_match[] = {
+ { .compatible = "syna,sl261x-reset", .data = &sl261x_reset_data },
+ { .compatible = "syna,sl261x-system-reset", .data = &sl261x_system_reset_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, sl261x_reset_dt_match);
+
+static struct platform_driver sl261x_reset_driver = {
+ .probe = sl261x2_reset_probe,
+ .driver = {
+ .name = "sl261x2-reset",
+ .of_match_table = sl261x_reset_dt_match,
+ },
+};
+module_platform_driver(sl261x_reset_driver);
+
+MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
+MODULE_DESCRIPTION("Synaptics SL261X reset controller");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 10/20] pinctrl: berlin: use u16 instead of u8 for the offset
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (8 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 09/20] reset: add Synaptics SL261x reset support Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 11/20] pinctrl: berlin: enable module build support Jisheng Zhang
` (10 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
The u8 may not be enough for newer Synaptics SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/pinctrl/berlin/berlin.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h
index 231aab61d415..7e7096842eda 100644
--- a/drivers/pinctrl/berlin/berlin.h
+++ b/drivers/pinctrl/berlin/berlin.h
@@ -17,7 +17,7 @@ struct berlin_desc_function {
struct berlin_desc_group {
const char *name;
- u8 offset;
+ u16 offset;
u8 bit_width;
u8 lsb;
struct berlin_desc_function *functions;
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 11/20] pinctrl: berlin: enable module build support
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (9 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 10/20] pinctrl: berlin: use u16 instead of u8 for the offset Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 12/20] pinctrl: berlin: add optional pinconf support Jisheng Zhang
` (9 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
For Android GKI + vendor_dlkm deployments, where vendor-specific
drivers must be kept separate from the GKI vmlinux and loaded as
modules from the vendor partition, we need to enable module build
support for berlin pinctrl drivers.
To acchive this goal:
1.Use devm_* APIs to alloc memory, so that we don't need to care free when
unloading.
2.Export two symbols which will be used by SoC pinctrl drivers.
3.Add MODULE_LICENSE and MODULE_DESCRIPTION
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/pinctrl/berlin/berlin.c | 27 ++++++++++++++-------------
drivers/pinctrl/berlin/berlin.h | 15 +++++++++++++++
2 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
index 7971339e269f..0c2179b98629 100644
--- a/drivers/pinctrl/berlin/berlin.c
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -215,7 +215,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
}
/* we will reallocate later */
- pctrl->functions = kzalloc_objs(*pctrl->functions, max_functions);
+ pctrl->functions = devm_kcalloc(&pdev->dev, max_functions,
+ sizeof(*pctrl->functions), GFP_KERNEL);
if (!pctrl->functions)
return -ENOMEM;
@@ -230,13 +231,11 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
}
}
- new_functions = krealloc(pctrl->functions,
- pctrl->nfunctions * sizeof(*pctrl->functions),
- GFP_KERNEL);
- if (!new_functions) {
- kfree(pctrl->functions);
+ new_functions = devm_krealloc(&pdev->dev, pctrl->functions,
+ pctrl->nfunctions * sizeof(*pctrl->functions),
+ GFP_KERNEL);
+ if (!new_functions)
return -ENOMEM;
- }
pctrl->functions = new_functions;
/* map functions to theirs groups */
@@ -257,10 +256,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
function++;
}
- if (!found) {
- kfree(pctrl->functions);
+ if (!found)
return -EINVAL;
- }
if (!function->groups) {
function->groups =
@@ -268,10 +265,9 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
function->ngroups,
sizeof(*function->groups),
GFP_KERNEL);
- if (!function->groups) {
- kfree(pctrl->functions);
+
+ if (!function->groups)
return -ENOMEM;
- }
}
groups = (const char **)function->groups;
@@ -327,6 +323,7 @@ int berlin_pinctrl_probe_regmap(struct platform_device *pdev,
return 0;
}
+EXPORT_SYMBOL_GPL(berlin_pinctrl_probe_regmap);
int berlin_pinctrl_probe(struct platform_device *pdev,
const struct berlin_pinctrl_desc *desc)
@@ -341,3 +338,7 @@ int berlin_pinctrl_probe(struct platform_device *pdev,
return berlin_pinctrl_probe_regmap(pdev, desc, regmap);
}
+EXPORT_SYMBOL_GPL(berlin_pinctrl_probe);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("pinctrl library for Synaptics SoCs");
diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h
index 7e7096842eda..8ff70d682593 100644
--- a/drivers/pinctrl/berlin/berlin.h
+++ b/drivers/pinctrl/berlin/berlin.h
@@ -20,6 +20,8 @@ struct berlin_desc_group {
u16 offset;
u8 bit_width;
u8 lsb;
+ u16 conf_offset;
+ u8 conf_bits;
struct berlin_desc_function *functions;
};
@@ -28,6 +30,19 @@ struct berlin_pinctrl_desc {
unsigned ngroups;
};
+#define BERLIN_PINCTRLCONF_GROUP(_name, _offset, _width, _lsb, \
+ _conf_offset, _conf_bits, ...) \
+ { \
+ .name = _name, \
+ .offset = _offset, \
+ .bit_width = _width, \
+ .lsb = _lsb, \
+ .conf_offset = _conf_offset, \
+ .conf_bits = _conf_bits, \
+ .functions = (struct berlin_desc_function[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
#define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \
{ \
.name = _name, \
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 12/20] pinctrl: berlin: add optional pinconf support
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (10 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 11/20] pinctrl: berlin: enable module build support Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 13/20] dt-bindings: pinctrl: berlin: Support Synaptics SL261X SoCs Jisheng Zhang
` (8 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add pinconf support for newer Synaptics SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/pinctrl/berlin/berlin.c | 232 +++++++++++++++++++++++++++++++-
1 file changed, 228 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
index 0c2179b98629..06c67f00c527 100644
--- a/drivers/pinctrl/berlin/berlin.c
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -13,6 +13,8 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
@@ -20,9 +22,24 @@
#include <linux/slab.h>
#include "../core.h"
+#include "../pinconf.h"
#include "../pinctrl-utils.h"
#include "berlin.h"
+#define PINCFG_DS_10BIT GENMASK(3, 0)
+#define PINCFG_IE_10BIT BIT(4)
+#define PINCFG_PE_10BIT BIT(5)
+#define PINCFG_PS_10BIT BIT(6)
+#define PINCFG_SL_10BIT BIT(7)
+#define PINCFG_SPU_10BIT BIT(8)
+#define PINCFG_ST_10BIT BIT(9)
+#define PINCFG_DS_8BIT GENMASK(2, 0)
+#define PINCFG_IE_8BIT BIT(3)
+#define PINCFG_PD_8BIT BIT(4)
+#define PINCFG_PU_8BIT BIT(5)
+#define PINCFG_SL_8BIT BIT(6)
+#define PINCFG_ST_8BIT BIT(7)
+
struct berlin_pinctrl {
struct regmap *regmap;
struct device *dev;
@@ -56,6 +73,8 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
struct property *prop;
const char *function_name, *group_name;
unsigned reserved_maps = 0;
+ unsigned long *configs = NULL;
+ unsigned int num_configs = 0;
int ret, ngroups;
*map = NULL;
@@ -75,11 +94,19 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
return -EINVAL;
}
+ ret = pinconf_generic_parse_dt_config(node, pctrl_dev, &configs,
+ &num_configs);
+ if (ret < 0) {
+ dev_err(pctrl->dev, "%s: could not parse node property\n",
+ node->name);
+ return ret;
+ }
+
ret = pinctrl_utils_reserve_map(pctrl_dev, map, &reserved_maps,
- num_maps, ngroups);
+ num_maps, ngroups * (num_configs + 1));
if (ret) {
dev_err(pctrl->dev, "can't reserve map: %d\n", ret);
- return ret;
+ goto exit;
}
of_property_for_each_string(node, "groups", prop, group_name) {
@@ -88,11 +115,22 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
function_name);
if (ret) {
dev_err(pctrl->dev, "can't add map: %d\n", ret);
- return ret;
+ goto exit;
+ }
+
+ if (num_configs) {
+ ret = pinctrl_utils_add_map_configs(pctrl_dev, map,
+ &reserved_maps, num_maps, group_name,
+ configs, num_configs,
+ PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (ret < 0)
+ goto exit;
}
}
- return 0;
+exit:
+ kfree(configs);
+ return ret;
}
static const struct pinctrl_ops berlin_pinctrl_ops = {
@@ -177,6 +215,191 @@ static const struct pinmux_ops berlin_pinmux_ops = {
.set_mux = &berlin_pinmux_set,
};
+static int berlin_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
+ unsigned int group, unsigned long *configs)
+{
+ enum pin_config_param param = pinconf_to_config_param(*configs);
+ struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
+ bool enabled;
+ u32 val;
+ int ret;
+ u8 conf_bits = group_desc->conf_bits;
+
+ if (!conf_bits)
+ return -EOPNOTSUPP;
+
+ ret = regmap_read(pctrl->regmap, group_desc->conf_offset, &val);
+ if (ret)
+ return ret;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (conf_bits == 10)
+ enabled = !(val & PINCFG_PE_10BIT);
+ else
+ enabled = !(val & (PINCFG_PD_8BIT | PINCFG_PU_8BIT));
+ val = 0;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (conf_bits == 10)
+ enabled = (val & (PINCFG_PE_10BIT | PINCFG_PS_10BIT)) == PINCFG_PE_10BIT;
+ else
+ enabled = val & PINCFG_PD_8BIT;
+ val = enabled ? 1 : 0;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (conf_bits == 10) {
+ if ((val & (PINCFG_PE_10BIT | PINCFG_PS_10BIT)) == (PINCFG_PE_10BIT | PINCFG_PS_10BIT)) {
+ enabled = true;
+ if (val & PINCFG_SPU_10BIT)
+ val = 2;
+ else
+ val = 1;
+ } else {
+ enabled = false;
+ val = 0;
+ }
+ } else {
+ enabled = val & PINCFG_PU_8BIT;
+ val = enabled ? 1 : 0;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ enabled = true;
+ if (conf_bits == 10)
+ val = FIELD_GET(PINCFG_DS_10BIT, val);
+ else
+ val = FIELD_GET(PINCFG_DS_8BIT, val);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ if (conf_bits == 10)
+ enabled = val & PINCFG_IE_10BIT;
+ else
+ enabled = val & PINCFG_IE_8BIT;
+ val = enabled ? 1 : 0;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (conf_bits == 10)
+ enabled = val & PINCFG_ST_10BIT;
+ else
+ enabled = val & PINCFG_ST_8BIT;
+ val = enabled ? 1 : 0;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (conf_bits == 10)
+ enabled = val & PINCFG_SL_10BIT;
+ else
+ enabled = val & PINCFG_SL_8BIT;
+ val = enabled ? 1 : 0;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ *configs = pinconf_to_config_packed(param, val);
+ return enabled ? 0 : -EINVAL;
+}
+
+static int berlin_pinconf_group_set(struct pinctrl_dev *pctrl_dev,
+ unsigned int group, unsigned long *configs,
+ unsigned int nconfigs)
+{
+ struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
+ u8 conf_bits = group_desc->conf_bits;
+ u32 mask = 0, val = 0;
+ int i;
+
+ if (!conf_bits)
+ return -EOPNOTSUPP;
+
+ for (i = 0; i < nconfigs; i++) {
+ enum pin_config_param param =
+ pinconf_to_config_param(configs[i]);
+ u32 arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (conf_bits == 10)
+ mask |= (PINCFG_PE_10BIT | PINCFG_PS_10BIT | PINCFG_SPU_10BIT);
+ else
+ mask |= (PINCFG_PU_8BIT | PINCFG_PD_8BIT);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (conf_bits == 10) {
+ mask |= (PINCFG_PE_10BIT | PINCFG_PS_10BIT | PINCFG_SPU_10BIT);
+ val |= PINCFG_PE_10BIT;
+ } else {
+ mask |= (PINCFG_PU_8BIT | PINCFG_PD_8BIT);
+ val |= PINCFG_PD_8BIT;
+ }
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (conf_bits == 10) {
+ mask |= (PINCFG_PE_10BIT | PINCFG_PS_10BIT | PINCFG_SPU_10BIT);
+ val |= (PINCFG_PE_10BIT | PINCFG_PS_10BIT);
+ if (arg == 2)
+ val |= PINCFG_SPU_10BIT;
+ } else {
+ mask |= (PINCFG_PU_8BIT | PINCFG_PD_8BIT);
+ val |= PINCFG_PU_8BIT;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ if (conf_bits == 10)
+ mask |= PINCFG_DS_10BIT;
+ else
+ mask |= PINCFG_DS_8BIT;
+ val |= arg;
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ if (conf_bits == 10) {
+ mask |= PINCFG_IE_10BIT;
+ if (arg)
+ val |= PINCFG_IE_10BIT;
+ } else {
+ mask |= PINCFG_IE_8BIT;
+ if (arg)
+ val |= PINCFG_IE_8BIT;
+ }
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (conf_bits == 10) {
+ mask |= PINCFG_ST_10BIT;
+ if (arg)
+ val |= PINCFG_ST_10BIT;
+ } else {
+ mask |= PINCFG_ST_8BIT;
+ if (arg)
+ val |= PINCFG_ST_8BIT;
+ }
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (conf_bits == 10) {
+ mask |= PINCFG_SL_10BIT;
+ if (arg)
+ val |= PINCFG_SL_10BIT;
+ } else {
+ mask |= PINCFG_SL_8BIT;
+ if (arg)
+ val |= PINCFG_SL_8BIT;
+ }
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+ }
+
+ return regmap_update_bits(pctrl->regmap, group_desc->conf_offset, mask, val);
+}
+
+static const struct pinconf_ops berlin_confops = {
+ .is_generic = true,
+ .pin_config_group_get = berlin_pinconf_group_get,
+ .pin_config_group_set = berlin_pinconf_group_set,
+};
+
static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
const char *name)
{
@@ -287,6 +510,7 @@ static const struct pinctrl_desc berlin_pctrl_desc = {
.name = "berlin-pinctrl",
.pctlops = &berlin_pinctrl_ops,
.pmxops = &berlin_pinmux_ops,
+ .confops = &berlin_confops,
.owner = THIS_MODULE,
};
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 13/20] dt-bindings: pinctrl: berlin: Support Synaptics SL261X SoCs
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (11 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 12/20] pinctrl: berlin: add optional pinconf support Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 14/20] pinctrl: berlin: support " Jisheng Zhang
` (7 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Document the dt-bindings for pinctrl in Synaptics SL261X SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml
index 6ace3bf5433b..fb60a310a24e 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml
@@ -37,6 +37,8 @@ properties:
- marvell,berlin4ct-soc-pinctrl
- marvell,berlin4ct-system-pinctrl
- syna,as370-soc-pinctrl
+ - syna,sl261x-soc-pinctrl
+ - syna,sl261x-system-pinctrl
reg:
maxItems: 1
@@ -44,8 +46,10 @@ properties:
additionalProperties:
description: Pin group configuration subnodes.
type: object
- $ref: /schemas/pinctrl/pinmux-node.yaml#
- additionalProperties: false
+
+ allOf:
+ - $ref: /schemas/pinctrl/pinmux-node.yaml#
+ - $ref: /schemas/pinctrl/pincfg-node.yaml#
properties:
groups:
@@ -60,6 +64,8 @@ additionalProperties:
- groups
- function
+ unevaluatedProperties: false
+
allOf:
- if:
properties:
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 14/20] pinctrl: berlin: support Synaptics SL261X SoCs
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (12 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 13/20] dt-bindings: pinctrl: berlin: Support Synaptics SL261X SoCs Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 15:34 ` Uwe Kleine-König
2026-09-29 6:14 ` [PATCH 15/20] dt-bindings: clock: add Synaptics SL261X clock Jisheng Zhang
` (6 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add driver for the pinctrl in Synaptics SL261X SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/pinctrl/berlin/Kconfig | 7 +
drivers/pinctrl/berlin/Makefile | 1 +
drivers/pinctrl/berlin/pinctrl-sl261x.c | 745 ++++++++++++++++++++++++
3 files changed, 753 insertions(+)
create mode 100644 drivers/pinctrl/berlin/pinctrl-sl261x.c
diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig
index 9b1644d1d4ea..40e4b6546d0c 100644
--- a/drivers/pinctrl/berlin/Kconfig
+++ b/drivers/pinctrl/berlin/Kconfig
@@ -31,4 +31,11 @@ config PINCTRL_BERLIN_BG4CT
depends on OF
select PINCTRL_BERLIN
+config PINCTRL_SL261X
+ tristate "Synaptics SL261X pin controller driver"
+ depends on OF
+ select GENERIC_PINCONF
+ select PINCONF
+ select PINCTRL_BERLIN
+
endif
diff --git a/drivers/pinctrl/berlin/Makefile b/drivers/pinctrl/berlin/Makefile
index 7b4aa5444a4a..21031f0297af 100644
--- a/drivers/pinctrl/berlin/Makefile
+++ b/drivers/pinctrl/berlin/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o
obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o
obj-$(CONFIG_PINCTRL_BERLIN_BG4CT) += berlin-bg4ct.o
obj-$(CONFIG_PINCTRL_AS370) += pinctrl-as370.o
+obj-$(CONFIG_PINCTRL_SL261X) += pinctrl-sl261x.o
diff --git a/drivers/pinctrl/berlin/pinctrl-sl261x.c b/drivers/pinctrl/berlin/pinctrl-sl261x.c
new file mode 100644
index 000000000000..8296ab1836a7
--- /dev/null
+++ b/drivers/pinctrl/berlin/pinctrl-sl261x.c
@@ -0,0 +1,745 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Synaptics SL261X pinctrl driver
+ *
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <linux/init.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+#include "berlin.h"
+
+static const struct berlin_desc_group sl261x_soc_pinctrl_groups[] = {
+ BERLIN_PINCTRLCONF_GROUP("GPIO23", 0x8000, 0x3, 0x00,
+ 0x8800, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO23 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "tw2"), /* SCL */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), /* MDC */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row0"),
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi3"), /* SS2n */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col3"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* OUT4 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO24", 0x8000, 0x3, 0x03,
+ 0x8804, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO24 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "tw2"), /* SDA */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), /* MDIO */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row1"),
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi3"), /* SS3n */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col2"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* OUT5 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO25", 0x8000, 0x3, 0x06,
+ 0x8808, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO25 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "uart5"), /* RXD */
+ BERLIN_PINCTRL_FUNCTION(0x2, "gpio_trig1"),
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row2"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "sm_uart1"), /* RXD */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col1"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* OUT6 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO26", 0x8000, 0x3, 0x09,
+ 0x880c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO26 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "uart5"), /* TXD */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), /* PTP_PPS_O */
+ BERLIN_PINCTRL_FUNCTION(0x4, "sm_uart1"), /* TXD */
+ BERLIN_PINCTRL_FUNCTION(0x5, "usb2"), /* VBUS */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* OUT7 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO27", 0x8000, 0x3, 0x0c,
+ 0x8810, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO27 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "tw3"), /* SCL */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart4"), /* TXD */
+ BERLIN_PINCTRL_FUNCTION(0x4, "sm_uart1")), /* RTSn */
+ BERLIN_PINCTRLCONF_GROUP("GPIO28", 0x8000, 0x3, 0x0f,
+ 0x8814, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO28 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "tw3"), /* SDA */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart4"), /* RXD */
+ BERLIN_PINCTRL_FUNCTION(0x4, "sm_uart1")), /* CTSn */
+ BERLIN_PINCTRLCONF_GROUP("GPIO29", 0x8000, 0x3, 0x12,
+ 0x8818, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO29 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart4"), /* DE */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row4"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "sm_uart1"), /* RXD */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col4"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SDI */
+ BERLIN_PINCTRLCONF_GROUP("GPIO30", 0x8000, 0x3, 0x15,
+ 0x881c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO30 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart4"), /* REn */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row5"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "sm_uart1"), /* TXD */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col5"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SCLK */
+ BERLIN_PINCTRLCONF_GROUP("GPIO31", 0x8000, 0x3, 0x18,
+ 0x8820, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO31 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), /* MDC */
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi5"), /* SS3n */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi3"), /* SS2n */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SS2n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO32", 0x8000, 0x3, 0x1b,
+ 0x8824, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO32 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"), /* MDIO */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi3"), /* SS3n */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SS3n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO33", 0x8004, 0x3, 0x00,
+ 0x8828, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO33 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* TD0 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii1"), /* TXD0 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "can0"), /* TX */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi3"), /* SS1n */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SS1n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO34", 0x8004, 0x3, 0x03,
+ 0x882c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO34 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* TD1 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii1"), /* TXD1 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "can0")), /* RX */
+ BERLIN_PINCTRLCONF_GROUP("GPIO35", 0x8004, 0x3, 0x06,
+ 0x8830, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO35 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* TD2 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii2"), /* TXD0 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col7"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart5"), /* RXD */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SS0n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO36", 0x8004, 0x3, 0x09,
+ 0x8834, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO36 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* TD3 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii2"), /* TXD1 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart5"), /* TXD */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SDO */
+ BERLIN_PINCTRLCONF_GROUP("GPIO37", 0x8004, 0x3, 0x0c,
+ 0x8838, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO37 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* RD0 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii1"), /* RXD0 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "can1"), /* TX */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi5")), /* SDI */
+ BERLIN_PINCTRLCONF_GROUP("GPIO38", 0x8004, 0x3, 0x0f,
+ 0x883c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO38 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* RD1 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii1"), /* RXD1 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "can1"), /* RX */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi5")), /* SDO */
+ BERLIN_PINCTRLCONF_GROUP("GPIO39", 0x8004, 0x3, 0x12,
+ 0x8840, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO39 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* RD2 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii2"), /* RXD0 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row6"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart6"), /* RXD */
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi5"), /* SS1n*/
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4")), /* SS3n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO40", 0x8004, 0x3, 0x15,
+ 0x8844, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO40 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* RD3 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii2"), /* RXD1 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row7"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart6"), /* TXD */
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi5"), /* SS2n */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4")), /* SS2n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO41", 0x8004, 0x3, 0x18,
+ 0x8848, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO41 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* RXC */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii1"), /* CRSDV */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi5")), /* SCLK */
+ BERLIN_PINCTRLCONF_GROUP("GPIO42", 0x8004, 0x3, 0x1b,
+ 0x884c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO42 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* TXC */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii2"), /* CRSDV */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row8"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart7"), /* RXD */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4")), /* SCLK */
+ BERLIN_PINCTRLCONF_GROUP("GPIO43", 0x8008, 0x3, 0x00,
+ 0x8850, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO43 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* TXCTL */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii1"), /* TXEN */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4")), /* SS0n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO44", 0x8008, 0x3, 0x03,
+ 0x8854, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO44 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* RXCTL */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii2"), /* TXEN */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row9"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart7"), /* TXD */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4")), /* SDI */
+ BERLIN_PINCTRLCONF_GROUP("GPIO45", 0x8008, 0x3, 0x06,
+ 0x8858, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO45 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii1"), /* CLKOUT */
+ BERLIN_PINCTRL_FUNCTION(0x2, "rmii1")), /* REFCLK */
+ BERLIN_PINCTRLCONF_GROUP("GPIO46", 0x8008, 0x3, 0x09,
+ 0x885c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO46 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "sdio1"), /* CDn */
+ BERLIN_PINCTRL_FUNCTION(0x2, "sdio2"), /* CDn */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col0"),
+ BERLIN_PINCTRL_FUNCTION(0x5, "sm_uart1"), /* RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_row9"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "dsi")), /* TE */
+ BERLIN_PINCTRLCONF_GROUP("GPIO47", 0x8008, 0x3, 0x0c,
+ 0x8860, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO47 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "sdio1"), /* WP */
+ BERLIN_PINCTRL_FUNCTION(0x2, "sdio2"), /* WP */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col1"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "rmii2"), /* REFCLK */
+ BERLIN_PINCTRL_FUNCTION(0x5, "sm_uart1"), /* CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_row8")),
+ BERLIN_PINCTRLCONF_GROUP("GPIO48", 0x8008, 0x3, 0x0f,
+ 0x8864, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO48 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* TD0 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi5"), /* SS0n */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4"), /* SS2n */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SS3n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO49", 0x8008, 0x3, 0x12,
+ 0x8868, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO49 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* TD1 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi5"), /* SDO */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4"), /* SS3n */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SS2n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO50", 0x8008, 0x3, 0x15,
+ 0x886c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO50 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* TD2 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi5"), /* SCLK */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SS1n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO51", 0x8008, 0x3, 0x18,
+ 0x8870, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO51 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* TD3 */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SS0n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO52", 0x8008, 0x3, 0x1b,
+ 0x8874, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO52 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* RD0 */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4"), /* SS2n */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SDO */
+ BERLIN_PINCTRLCONF_GROUP("GPIO53", 0x800c, 0x3, 0x00,
+ 0x8878, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO53 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* RD1 */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spi4"), /* SS3n */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SCLK */
+ BERLIN_PINCTRLCONF_GROUP("GPIO54", 0x800c, 0x3, 0x03,
+ 0x87c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO54 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* RD2 */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SDI */
+ BERLIN_PINCTRLCONF_GROUP("GPIO55", 0x800c, 0x3, 0x06,
+ 0x8880, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO55 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* RD3 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "spi5"), /* SDI */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SS1n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO56", 0x800c, 0x3, 0x09,
+ 0x8884, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO56 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* RXC */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SS0n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO57", 0x800c, 0x3, 0x0c,
+ 0x8888, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO57 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* TXC */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SDO */
+ BERLIN_PINCTRLCONF_GROUP("GPIO58", 0x800c, 0x3, 0x0f,
+ 0x888c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO58 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* TXCTL */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SCLK */
+ BERLIN_PINCTRLCONF_GROUP("GPIO59", 0x800c, 0x3, 0x12,
+ 0x8890, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO59 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "rgmii2"), /* RXCTL */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi4")), /* SDI */
+ BERLIN_PINCTRLCONF_GROUP("GPIO0", 0x800c, 0x3, 0x15,
+ 0x8894, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO0 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCK */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SS0n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO1", 0x800c, 0x3, 0x18,
+ 0x8898, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO1 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLK */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SCLK */
+ BERLIN_PINCTRLCONF_GROUP("GPIO2", 0x800c, 0x3, 0x1b,
+ 0x889c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO2*/
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO */
+ BERLIN_PINCTRL_FUNCTION(0x4, "spdif"), /* O */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SDO */
+ BERLIN_PINCTRLCONF_GROUP("GPIO3", 0x8010, 0x3, 0x00,
+ 0x88a0, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO3 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* MCLK */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SS1n */
+ BERLIN_PINCTRLCONF_GROUP("GPIO4", 0x8010, 0x3, 0x03,
+ 0x88a4, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO4 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DI */
+ BERLIN_PINCTRL_FUNCTION(0x4, "spdif"), /* I */
+ BERLIN_PINCTRL_FUNCTION(0x7, "spi3")), /* SDI */
+ BERLIN_PINCTRLCONF_GROUP("GPIO5", 0x8010, 0x3, 0x06,
+ 0x88a8, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO5 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* LRCK */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* PIXCLK */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row0"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "spdif"), /* I */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col7")),
+ BERLIN_PINCTRLCONF_GROUP("GPIO6", 0x8010, 0x3, 0x09,
+ 0x88ac, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO6 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* BCLK */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* HSYNC */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row1"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "spdif"), /* O */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col6")),
+ BERLIN_PINCTRLCONF_GROUP("GPIO7", 0x8010, 0x3, 0x0c,
+ 0x88b0, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO7 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DO */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row2"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "spdif"), /* O */
+ BERLIN_PINCTRL_FUNCTION(0x5, "sm_pdm"), /* CLKIO */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col5")),
+ BERLIN_PINCTRLCONF_GROUP("GPIO8", 0x8010, 0x3, 0x0f,
+ 0x88b4, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO8 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* VSYNC */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row3"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "spdif"), /* I */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_col4")),
+ BERLIN_PINCTRLCONF_GROUP("GPIO9", 0x8010, 0x3, 0x12,
+ 0x88b8, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO9 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* DATA0 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "pdm")), /* DI1 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO10", 0x8010, 0x3, 0x15,
+ 0x88bc, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO10 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* DATA1 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "pdm"), /* DI2 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "dsi")), /* TE */
+ BERLIN_PINCTRLCONF_GROUP("GPIO11", 0x8010, 0x3, 0x18,
+ 0x88c0, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO11 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* MCLK */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* DATA2 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "sm_pdm"), /* CLKIO */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* CLK */
+ BERLIN_PINCTRLCONF_GROUP("GPIO12", 0x8010, 0x3, 0x1b,
+ 0x88c4, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO12 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* LRCK */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* DATA3 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sdio2"), /* WP */
+ BERLIN_PINCTRL_FUNCTION(0x4, "sdio1"), /* WP */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* OUT0 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO13", 0x8014, 0x3, 0x00,
+ 0x88c8, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO13 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* BCLK */
+ BERLIN_PINCTRL_FUNCTION(0x2, "pdm"), /* DI1 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "rgmii"), /* PTP_PPS_O */
+ BERLIN_PINCTRL_FUNCTION(0x4, "usb2"), /* VBUS */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* OUT1 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO14", 0x8014, 0x3, 0x03,
+ 0x88cc, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO14 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* DO */
+ BERLIN_PINCTRL_FUNCTION(0x4, "pdm"), /* DI3 */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spdif"), /* O */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* OUT2 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO15", 0x8014, 0x3, 0x06,
+ 0x88d0, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO15 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* DI */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* DATA4 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "sm_pdm"), /* DI0 */
+ BERLIN_PINCTRL_FUNCTION(0x6, "spdif"), /* I */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* OUT3 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO16", 0x8014, 0x3, 0x09,
+ 0x88d4, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO16 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS0n */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sdio2")), /* DAT3 */
+ BERLIN_PINCTRLCONF_GROUP("GPIO17", 0x8014, 0x3, 0x0c,
+ 0x88d8, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO17 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS1n */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* DATA5 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sdio2"), /* DAT2 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "dsi")), /* TE */
+ BERLIN_PINCTRLCONF_GROUP("GPIO18", 0x8014, 0x3, 0x0f,
+ 0x88dc, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO18 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS2n */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* DATA6 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sdio2"), /* DAT1 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "pdm"), /* DI2 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "can1")), /* RX */
+ BERLIN_PINCTRLCONF_GROUP("GPIO19", 0x8014, 0x3, 0x12,
+ 0x88e0, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO19 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS3n */
+ BERLIN_PINCTRL_FUNCTION(0x2, "cam"), /* DATA7 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sdio2"), /* DAT0 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "pdm"), /* DI3 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "can1")), /* TX */
+ BERLIN_PINCTRLCONF_GROUP("GPIO20", 0x8014, 0x3, 0x15,
+ 0x88e4, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO20 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SDO */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sdio2")), /* CMD */
+ BERLIN_PINCTRLCONF_GROUP("GPIO21", 0x8014, 0x3, 0x18,
+ 0x88e8, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO21 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SCLK */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sdio2"), /* CLK */
+ BERLIN_PINCTRL_FUNCTION(0x5, "clkout")),
+ BERLIN_PINCTRLCONF_GROUP("GPIO22", 0x8014, 0x3, 0x1b,
+ 0x88ec, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO22 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SDI */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sdio2"), /* CDn */
+ BERLIN_PINCTRL_FUNCTION(0x4, "sdio1")), /* CDn */
+};
+
+static const struct berlin_desc_group sl261x_sysmgr_pinctrl_groups[] = {
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO31", 0xb00, 0x3, 0x00,
+ 0xc00, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO31*/
+ BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* SM PWM0*/
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* SM UART1 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row7"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "pdm"), /* SM PDM DI0 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "uart0"), /* SM UART0 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x6, "can1")), /* SM CAN1 RX */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO32", 0xb00, 0x3, 0x03,
+ 0xc04, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO32 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* SM PWM1 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* SM UART1 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col0"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "pdm"), /* SM PDM CLKIO */
+ BERLIN_PINCTRL_FUNCTION(0x5, "uart0"), /* SM UART0 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x6, "can1")), /* SM CAN1 TX */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO33", 0xb00, 0x3, 0x06,
+ 0xc08, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO33 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* SM PWM2 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "uart2"), /* SM UART2 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart3"), /* SM UART3 RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x5, "key_row5"),
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart3_de")), /* SM UART3 DE */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO34", 0xb00, 0x3, 0x09,
+ 0xc0c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO34 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* SM PWM3 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "uart2"), /* SM UART2 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart3"), /* SM UART3 CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x5, "key_row4"),
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart3_ren")), /* SM UART3 REn */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO35", 0xb00, 0x3, 0x0c,
+ 0xc10, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO35 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* SM PWM4 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* SM UART1 RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x3, "uart3"), /* SM UART3 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart2"), /* SM UART2 RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x5, "key_row3"),
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart0")), /* SM UART0 RTSn */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO36", 0xb00, 0x3, 0x0f,
+ 0xc14, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO36 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* SM PWM5 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* SM UART1 CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x3, "uart3"), /* SM UART3 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart2"), /* SM UART2 CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x5, "key_row2"),
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart0")), /* SM UART0 CTSn */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO37", 0xb00, 0x3, 0x12,
+ 0xc18, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO37 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* SM PWM6 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "tw0"), /* SM TW0 SCL */
+ BERLIN_PINCTRL_FUNCTION(0x4, "key_row6"),
+ BERLIN_PINCTRL_FUNCTION(0x5, "pdm")), /* SM PDM CLKIO */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO38", 0xb00, 0x3, 0x15,
+ 0xc1c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO38 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* SM PWM7 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "tw0"), /* SM TW0 SDA */
+ BERLIN_PINCTRL_FUNCTION(0x5, "pdm")), /* SM PDM DI0 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO3", 0xb00, 0x3, 0x18,
+ 0xc20, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO3 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SM SPI1 SS0n */
+ BERLIN_PINCTRL_FUNCTION(0x2, "tw1"), /* SM TW1 SCL */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm"), /* SM PWM8 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "i3c")), /* SM I3C MS SCL */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO4", 0xb00, 0x3, 0x1b,
+ 0xc24, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO4 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SM SPI1 SS1n */
+ BERLIN_PINCTRL_FUNCTION(0x2, "tw1"), /* SM TW1 SDA */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm"), /* SM PWM0 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "i3c")), /* SM I3C MS SDA */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO5", 0xb04, 0x3, 0x00,
+ 0xc28, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO5 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SM SPI1 SS2n */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* SM PWM1 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO6", 0xb04, 0x3, 0x03,
+ 0xc2c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO6 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SM SPI1 SS3n */
+ BERLIN_PINCTRL_FUNCTION(0x2, "spi1s"), /* SM SPI1S SSn */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* SM PWM2 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO9", 0xb04, 0x3, 0x06,
+ 0xc30, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO9 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SM SPI1 SDO */
+ BERLIN_PINCTRL_FUNCTION(0x2, "spi1s"), /* SM SPI1S SDO */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* SM PWM3 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO10", 0xb04, 0x3, 0x09,
+ 0xc34, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO10 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SM SPI1 SCLK */
+ BERLIN_PINCTRL_FUNCTION(0x2, "spi1s"), /* SM SPI1S SCLK */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* SM PWM4 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO11", 0xb04, 0x3, 0x0c,
+ 0xc38, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO11 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SM SPI1 SDI */
+ BERLIN_PINCTRL_FUNCTION(0x2, "spi1s"), /* SM SPI1S SDI */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* SM PWM5 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO30", 0xb04, 0x3, 0x0f,
+ 0xc44, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO30 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi"), /* SM XSPI DATA7 */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col6"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "sm_clkout")),
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO29", 0xb04, 0x3, 0x12,
+ 0xc48, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO29 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi"), /* SM XSPI DATA6 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart3"), /* SM UART3 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col5"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart2"), /* SM UART2 CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x5, "uart0"), /* SM UART0 CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_row2"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "uart1")), /* SM UART1 CTSn */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO28", 0xb04, 0x3, 0x15,
+ 0xc4c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO28 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi"), /* SM XSPI DATA5 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart3"), /* SM UART3 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col4"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart2"), /* SM UART2 RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x5, "uart0"), /* SM UART0 RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_row3"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "uart1")), /* SM UART1 RTSn */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO27", 0xb04, 0x3, 0x18,
+ 0xc50, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO27 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi"), /* SM XSPI DATA4 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart2"), /* SM UART2 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col3"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart3"), /* SM UART3 CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x5, "uart3_ren"), /* SM UART3 REn */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_row4")),
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO26", 0xb04, 0x3, 0x1b,
+ 0xc54, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO26 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi"), /* SM XSPI CS1n */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart2"), /* SM UART2 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col2"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "uart3"), /* SM UART3 RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x5, "uart3_de"), /* SM UART3 DE */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_row5"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "sm_clkout")),
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO25", 0xb08, 0x3, 0x00,
+ 0xc58, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO25 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi"), /* SM XSPI DQS */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_row6")),
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO24", 0xb08, 0x3, 0x03,
+ 0xc5c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO24 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi")), /* SM XSPI CLKn */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO23", 0xb08, 0x3, 0x06,
+ 0xc60, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO23 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi")), /* SM XSPI CLK */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO22", 0xb08, 0x3, 0x09,
+ 0xc64, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO22 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi")), /* SM XSPI DATA3 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO21", 0xb08, 0x3, 0x0c,
+ 0xc68, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO21 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi")), /* SM XSPI DATA2 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO20", 0x8, 0x3, 0x0f,
+ 0xc6c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO20 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi")), /* SM XSPI DATA1 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO19", 0xb08, 0x3, 0x12,
+ 0xc70, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO19 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi")), /* SM XSPI DATA0 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO18", 0xb08, 0x3, 0x15,
+ 0xc74, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO18 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "xspi")), /* SM XSPI CS0n*/
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO17", 0xb08, 0x3, 0x18,
+ 0xc78, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO17 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* SM UART1 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x2, "can0"), /* SM CAN0 TX */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm"), /* SM PWM8 */
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart0")), /* SM UART0 TXD */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO15", 0xb08, 0x3, 0x1b,
+ 0xc7c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO15 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "tw1"), /* SM TW1 SDA */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart0"), /* SM UART0 RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm"), /* SM PWM11 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "can0"), /* SM CAN0 TX */
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart1"), /* SM UART1 RTSn */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* DBG OUT */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO14", 0xb0c, 0x3, 0x00,
+ 0xc80, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO14 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "tw1"), /* SM TW1 SCL */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart0"), /* SM UART0 CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm"), /* SM PWM10 */
+ BERLIN_PINCTRL_FUNCTION(0x4, "can0"), /* SM CAN0 RX */
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart1"), /* SM UART1 CTSn */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* DBG OUT */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO16", 0xb0c, 0x3, 0x03,
+ 0xc84, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO16 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* SM UART1 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x2, "can0"), /* SM CAN0 RX */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* SM PWM7 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO13", 0xb0c, 0x3, 0x06,
+ 0xc88, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO13 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "tw0"), /* SM TW0 SDA */
+ BERLIN_PINCTRL_FUNCTION(0x2, "i3c"), /* SM I3C MS SDA */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sm_clkout"),
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* DBG out */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO12", 0xb0c, 0x3, 0x09,
+ 0xc8c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO12 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "tw0"), /* SM TW0 SCL */
+ BERLIN_PINCTRL_FUNCTION(0x2, "i3c"), /* SM I3C MS SCL */
+ BERLIN_PINCTRL_FUNCTION(0x3, "pwm"), /* SM PWM6 */
+ BERLIN_PINCTRL_FUNCTION(0x7, "dbg")), /* DBG CLK */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO8", 0xb0c, 0x3, 0x0c,
+ 0xc90, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO8 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* SM UART0 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x2, "can0"), /* SM CAN0 TX */
+ BERLIN_PINCTRL_FUNCTION(0x3, "sm_clkout"),
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart1")), /* SM UART0 TXD */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO7", 0xb0c, 0x3, 0x0f,
+ 0xc94, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO7 */
+ BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* SM UART0 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x2, "can0"), /* SM CAN0 RX */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_row6"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "gpio_trig"), /* TRIG2 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "pwm"), /* SM PWM9 */
+ BERLIN_PINCTRL_FUNCTION(0x6, "uart1")), /* SM UART0 RXD */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO2", 0xb0c, 0x3, 0x12,
+ 0xc98, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDO */
+ BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO2 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "pdm"), /* SM PDM CLKIO */
+ BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"), /* MCLK */
+ BERLIN_PINCTRL_FUNCTION(0x6, "pwm")), /* SM PWM11 */
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO1", 0xb0c, 0x3, 0x15,
+ 0xc9c, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDI */
+ BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO1 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart0"), /* SM UART0 RXD */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col1"),
+ BERLIN_PINCTRL_FUNCTION(0x4, "gpio_trig"), /* TRIG0 */
+ BERLIN_PINCTRL_FUNCTION(0x5, "pwm"), /* SM PWM9 */
+ BERLIN_PINCTRL_FUNCTION(0x6, "key_row7")),
+ BERLIN_PINCTRLCONF_GROUP("SM_GPIO0", 0xb0c, 0x3, 0x18,
+ 0xca0, 10,
+ BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TMS */
+ BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO0 */
+ BERLIN_PINCTRL_FUNCTION(0x2, "uart0"), /* SM UART0 TXD */
+ BERLIN_PINCTRL_FUNCTION(0x3, "key_col0"),
+ BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* SM PDM DI0 */
+ BERLIN_PINCTRL_FUNCTION(0x6, "pwm")), /* SM PWM10 */
+};
+
+static const struct berlin_pinctrl_desc sl261x_soc_pinctrl_data = {
+ .groups = sl261x_soc_pinctrl_groups,
+ .ngroups = ARRAY_SIZE(sl261x_soc_pinctrl_groups),
+};
+
+static const struct berlin_pinctrl_desc sl261x_sysmgr_pinctrl_data = {
+ .groups = sl261x_sysmgr_pinctrl_groups,
+ .ngroups = ARRAY_SIZE(sl261x_sysmgr_pinctrl_groups),
+};
+
+static const struct of_device_id sl261x_pinctrl_match[] = {
+ {
+ .compatible = "syna,sl261x-soc-pinctrl",
+ .data = &sl261x_soc_pinctrl_data,
+ },
+ {
+ .compatible = "syna,sl261x-system-pinctrl",
+ .data = &sl261x_sysmgr_pinctrl_data,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sl261x_pinctrl_match);
+
+static int sl261x_pinctrl_probe(struct platform_device *pdev)
+{
+ return berlin_pinctrl_probe(pdev, device_get_match_data(&pdev->dev));
+}
+
+static struct platform_driver sl261x_pinctrl_driver = {
+ .probe = sl261x_pinctrl_probe,
+ .driver = {
+ .name = "sl261x-pinctrl",
+ .of_match_table = sl261x_pinctrl_match,
+ },
+};
+module_platform_driver(sl261x_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
+MODULE_DESCRIPTION("pinctrl driver for Synaptics SL261X SoC");
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 14/20] pinctrl: berlin: support Synaptics SL261X SoCs
2026-09-29 6:14 ` [PATCH 14/20] pinctrl: berlin: support " Jisheng Zhang
@ 2026-09-29 15:34 ` Uwe Kleine-König
0 siblings, 0 replies; 31+ messages in thread
From: Uwe Kleine-König @ 2026-09-29 15:34 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 1409 bytes --]
Hello,
On Tue, Sep 29, 2026 at 02:14:11PM +0800, Jisheng Zhang wrote:
> +#include <linux/mod_devicetable.h>
Please rely on <linux/platform_device.h> to pull in the definition of
of_device_id and drop the inclusion of <linux/mod_devicetable.h>.
Including <linux/mod_devicetable.h> creates a bunch of unneeded
dependencies on subsystems you will never need in this driver.
> [...]
> +static const struct of_device_id sl261x_pinctrl_match[] = {
> + {
> + .compatible = "syna,sl261x-soc-pinctrl",
> + .data = &sl261x_soc_pinctrl_data,
> + },
> + {
> + .compatible = "syna,sl261x-system-pinctrl",
> + .data = &sl261x_sysmgr_pinctrl_data,
> + },
> + {}
Please use { } (with a space) to match the most common style for these
arrays.
> +};
> +MODULE_DEVICE_TABLE(of, sl261x_pinctrl_match);
> +
> +static int sl261x_pinctrl_probe(struct platform_device *pdev)
> +{
> + return berlin_pinctrl_probe(pdev, device_get_match_data(&pdev->dev));
> +}
> +
> +static struct platform_driver sl261x_pinctrl_driver = {
> + .probe = sl261x_pinctrl_probe,
Not a fan on aligning the =, still more if it's done inconsistently in a
single struct. If you ask me, just use a single space before the =.
> + .driver = {
> + .name = "sl261x-pinctrl",
> + .of_match_table = sl261x_pinctrl_match,
> + },
> +};
> +module_platform_driver(sl261x_pinctrl_driver);
Best regards
Uwe
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 15/20] dt-bindings: clock: add Synaptics SL261X clock
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (13 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 14/20] pinctrl: berlin: support " Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 19:46 ` Conor Dooley
2026-09-29 20:49 ` Rob Herring (Arm)
2026-09-29 6:14 ` [PATCH 16/20] clk: berlin: add Synaptics SL261X SoC clocks and plls Jisheng Zhang
` (5 subsequent siblings)
20 siblings, 2 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add support for clocks, plls in Synaptics SL261X SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../bindings/clock/syna,sl261x-clk.yaml | 92 ++++++++++++
include/dt-bindings/clock/syna,sl261x.h | 131 ++++++++++++++++++
2 files changed, 223 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml
create mode 100644 include/dt-bindings/clock/syna,sl261x.h
diff --git a/Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml b/Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml
new file mode 100755
index 000000000000..3fd380c1dd39
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/syna,sl261x-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synaptics SL261x clock controllers
+
+maintainers:
+ - Jisheng Zhang <jszhang@kernel.org>
+
+description: |
+ The SL261x clock hardware is divided into SoC, CPU, AIO, and system
+ manager register blocks. Each clock controller is a child of the node
+ containing its register range. The CPU clock node has a phandle to the
+ global chip control syscon.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - syna,sl261x-soc-clk
+ - syna,sl261x-cpu-clk
+ - syna,sl261x-aio-clk
+ - syna,sl261x-system-clk
+ - items:
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ syna,gbl-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the SL261x global chip control syscon.
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ maxItems: 1
+ description: Reference clock used as the input to the PLLs.
+
+required:
+ - compatible
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: syna,sl261x-cpu-clk
+ then:
+ required:
+ - syna,gbl-syscon
+ else:
+ properties:
+ syna,gbl-syscon: false
+
+additionalProperties: false
+
+examples:
+ - |
+ osc: clock-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ chip: syscon@f7e10000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0xf7e10000 0x10000>;
+
+ clk: clock {
+ compatible = "syna,sl261x-soc-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+ };
+
+ cpu_wrap: cpu-wrap@f7e30000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0xf7e30000 0x4000>;
+
+ cpuclk: clock {
+ compatible = "syna,sl261x-cpu-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ syna,gbl-syscon = <&chip>;
+ };
+ };
+...
diff --git a/include/dt-bindings/clock/syna,sl261x.h b/include/dt-bindings/clock/syna,sl261x.h
new file mode 100644
index 000000000000..4649b233f08a
--- /dev/null
+++ b/include/dt-bindings/clock/syna,sl261x.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Synaptics SL261X clock tree IDs
+ *
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/* SoC domain */
+
+/* GBL common clks */
+#define CLK_CPUFASTREF 0
+#define CLK_MEMFASTREF 1
+#define CLK_CFG 2
+#define CLK_SYS 3
+#define CLK_PERIFSYS 4
+#define CLK_APBCORE 5
+#define CLK_APBSER 6
+#define CLK_ATB 7
+#define CLK_HPC 8
+#define CLK_EMMC 9
+#define CLK_SD0 10
+#define CLK_SD1 11
+#define CLK_GETHRGMII 12
+#define CLK_GETHRGMII1 13
+#define CLK_GE0_PTP_REF 14
+#define CLK_GE1_PTP_REF 15
+#define CLK_USB2TEST 16
+#define CLK_USB2TEST480MG0 17
+#define CLK_USB2TEST480MG1 18
+#define CLK_USB2TEST480MG2 19
+#define CLK_USB2TEST100MG0 20
+#define CLK_USB2TEST100MG1 21
+#define CLK_USB2TEST100MG2 22
+#define CLK_USB2TEST100MG3 23
+#define CLK_PERIFTEST125MG0 24
+#define CLK_PERIFTEST200MG0 25
+#define CLK_PERIFTEST200MG1 26
+#define CLK_GPU 27
+#define CLK_NPU 28
+#define CLK_AVIOSYS 29
+#define CLK_AIOSYS 30
+#define CLK_AVIO_LCDC2SCAN 31
+#define CLK_AVIO_IPI 32
+#define CLK_AVIO_P 33
+#define CLK_AVIO_DPHYRXTXESC 34
+#define CLK_AVIOFPLL 35
+#define CLK_AVIO_RX_SCANBYTE 36
+#define CLK_AVIO_RX_SCANTEST 37
+
+/* GBL gate clks */
+#define CLK_USB0CORE 38
+#define CLK_SDIOSYS 39
+#define CLK_EMMCSYS 40
+#define CLK_GPUAXI 41
+#define CLK_GETHRGMIISYS 42
+#define CLK_SDIO1SYS 43
+#define CLK_USB1CORE 44
+#define CLK_GETHRGMII1SYS 45
+#define CLK_USB0PHYREF 46
+#define CLK_USB1PHYREF 47
+#define CLK_APBUART0 48
+#define CLK_APBUART1 49
+#define CLK_APBUART2 50
+#define CLK_APBUART3 51
+#define CLK_APBI2C0 52
+#define CLK_APBI2C1 53
+#define CLK_APBSPI0 54
+#define CLK_APBSPI1 55
+#define CLK_APBSPI2 56
+#define CLK_APBSPI3 57
+#define CLK_APBGPIO 58
+#define CLK_APBTIMERS 59
+#define CLK_APBSYSCNT 60
+#define CLK_APBWDT 61
+#define CLK_APBDMA 62
+#define SL261X_CLK_MAX 63
+
+/* cpuss */
+#define CLK_CPU0 0
+#define CLK_CPU1 1
+#define CLK_DSU 2
+#define SL261X_CPU_CLK_MAX 3
+
+
+/* sysmgr domain */
+
+#define CLK_CFG_UART0 0
+#define CLK_SER_UART0 1
+#define CLK_CFG_UART1 2
+#define CLK_CFG_UART2 3
+#define CLK_CFG_UART3 4
+#define CLK_CFG_GPIO 5
+#define CLK_CFG_I2CM0 6
+#define CLK_CFG_I2CM1 7
+#define CLK_CFG_SPIM 8
+#define CLK_CFG_SPIS 9
+#define CLK_CFG_I3C 10
+#define CLK_CFG_XSPI 11
+#define CLK_AXI_XSPI 12
+#define CLK_CFG_PVT 13
+#define CLK_CFG_ADC 14
+#define CLK_CFG_PWM 15
+#define CLK_BUS_CAN0 16
+#define CLK_BUS_CAN1 17
+#define CLK_CFG_PDM 18
+
+#define CLK_SER_UART1 19
+#define CLK_SER_UART2 20
+#define CLK_SER_UART3 21
+#define CLK_DEB_GPIO 22
+#define CLK_SER_I2CM0 23
+#define CLK_SER_I2CM1 24
+#define CLK_SER_SPIM 25
+#define CLK_SER_SPIS 26
+#define CLK_SER_I3C 27
+#define CLK_SER_XSPI 28
+#define CLK_HS_PVT 29
+#define CLK_CORE_ADC 30
+#define CLK_SER_PWM 31
+#define CLK_SER_CAN0 32
+#define CLK_SER_CAN1 33
+#define CLK_SER_PDM 34
+#define CLK_REF_CALIB 35
+
+#define CLK_MCU_REF 36
+#define CLK_MCU_PLL 37
+#define CLK_MCU_IO_PLL 38
+#define CLK_MCU_APB 39
+#define CLK_MCU_AXI 40
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 15/20] dt-bindings: clock: add Synaptics SL261X clock
2026-09-29 6:14 ` [PATCH 15/20] dt-bindings: clock: add Synaptics SL261X clock Jisheng Zhang
@ 2026-09-29 19:46 ` Conor Dooley
2026-09-29 20:49 ` Rob Herring (Arm)
1 sibling, 0 replies; 31+ messages in thread
From: Conor Dooley @ 2026-09-29 19:46 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 7359 bytes --]
On Tue, Sep 29, 2026 at 02:14:12PM +0800, Jisheng Zhang wrote:
> Add support for clocks, plls in Synaptics SL261X SoCs.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> .../bindings/clock/syna,sl261x-clk.yaml | 92 ++++++++++++
> include/dt-bindings/clock/syna,sl261x.h | 131 ++++++++++++++++++
> 2 files changed, 223 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml
> create mode 100644 include/dt-bindings/clock/syna,sl261x.h
>
> diff --git a/Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml b/Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml
> new file mode 100755
> index 000000000000..3fd380c1dd39
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/syna,sl261x-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synaptics SL261x clock controllers
> +
> +maintainers:
> + - Jisheng Zhang <jszhang@kernel.org>
> +
> +description: |
> + The SL261x clock hardware is divided into SoC, CPU, AIO, and system
> + manager register blocks. Each clock controller is a child of the node
> + containing its register range. The CPU clock node has a phandle to the
> + global chip control syscon.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - syna,sl261x-soc-clk
> + - syna,sl261x-cpu-clk
> + - syna,sl261x-aio-clk
> + - syna,sl261x-system-clk
> + - items:
> + - const: simple-mfd
> + - const: syscon
What's going on here? You're entirely missing specific compatibles for
your syscon nodes (which aren't clock controllers and shouldn't be
defined here.
Similarly to the reset stuff, why can't these just be parts of their
parent nodes?
Thanks,
Conor.
> +
> + reg:
> + maxItems: 1
> +
> + syna,gbl-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Phandle to the SL261x global chip control syscon.
> +
> + '#clock-cells':
> + const: 1
> +
> + clocks:
> + maxItems: 1
> + description: Reference clock used as the input to the PLLs.
> +
> +required:
> + - compatible
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: syna,sl261x-cpu-clk
> + then:
> + required:
> + - syna,gbl-syscon
> + else:
> + properties:
> + syna,gbl-syscon: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + osc: clock-osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + chip: syscon@f7e10000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0xf7e10000 0x10000>;
> +
> + clk: clock {
> + compatible = "syna,sl261x-soc-clk";
> + #clock-cells = <1>;
> + clocks = <&osc>;
> + };
> + };
> +
> + cpu_wrap: cpu-wrap@f7e30000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0xf7e30000 0x4000>;
> +
> + cpuclk: clock {
> + compatible = "syna,sl261x-cpu-clk";
> + #clock-cells = <1>;
> + clocks = <&osc>;
> + syna,gbl-syscon = <&chip>;
> + };
> + };
> +...
> diff --git a/include/dt-bindings/clock/syna,sl261x.h b/include/dt-bindings/clock/syna,sl261x.h
> new file mode 100644
> index 000000000000..4649b233f08a
> --- /dev/null
> +++ b/include/dt-bindings/clock/syna,sl261x.h
> @@ -0,0 +1,131 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Synaptics SL261X clock tree IDs
> + *
> + * Copyright (C) 2025 Synaptics Incorporated
> + *
> + * Author: Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +/* SoC domain */
> +
> +/* GBL common clks */
> +#define CLK_CPUFASTREF 0
> +#define CLK_MEMFASTREF 1
> +#define CLK_CFG 2
> +#define CLK_SYS 3
> +#define CLK_PERIFSYS 4
> +#define CLK_APBCORE 5
> +#define CLK_APBSER 6
> +#define CLK_ATB 7
> +#define CLK_HPC 8
> +#define CLK_EMMC 9
> +#define CLK_SD0 10
> +#define CLK_SD1 11
> +#define CLK_GETHRGMII 12
> +#define CLK_GETHRGMII1 13
> +#define CLK_GE0_PTP_REF 14
> +#define CLK_GE1_PTP_REF 15
> +#define CLK_USB2TEST 16
> +#define CLK_USB2TEST480MG0 17
> +#define CLK_USB2TEST480MG1 18
> +#define CLK_USB2TEST480MG2 19
> +#define CLK_USB2TEST100MG0 20
> +#define CLK_USB2TEST100MG1 21
> +#define CLK_USB2TEST100MG2 22
> +#define CLK_USB2TEST100MG3 23
> +#define CLK_PERIFTEST125MG0 24
> +#define CLK_PERIFTEST200MG0 25
> +#define CLK_PERIFTEST200MG1 26
> +#define CLK_GPU 27
> +#define CLK_NPU 28
> +#define CLK_AVIOSYS 29
> +#define CLK_AIOSYS 30
> +#define CLK_AVIO_LCDC2SCAN 31
> +#define CLK_AVIO_IPI 32
> +#define CLK_AVIO_P 33
> +#define CLK_AVIO_DPHYRXTXESC 34
> +#define CLK_AVIOFPLL 35
> +#define CLK_AVIO_RX_SCANBYTE 36
> +#define CLK_AVIO_RX_SCANTEST 37
> +
> +/* GBL gate clks */
> +#define CLK_USB0CORE 38
> +#define CLK_SDIOSYS 39
> +#define CLK_EMMCSYS 40
> +#define CLK_GPUAXI 41
> +#define CLK_GETHRGMIISYS 42
> +#define CLK_SDIO1SYS 43
> +#define CLK_USB1CORE 44
> +#define CLK_GETHRGMII1SYS 45
> +#define CLK_USB0PHYREF 46
> +#define CLK_USB1PHYREF 47
> +#define CLK_APBUART0 48
> +#define CLK_APBUART1 49
> +#define CLK_APBUART2 50
> +#define CLK_APBUART3 51
> +#define CLK_APBI2C0 52
> +#define CLK_APBI2C1 53
> +#define CLK_APBSPI0 54
> +#define CLK_APBSPI1 55
> +#define CLK_APBSPI2 56
> +#define CLK_APBSPI3 57
> +#define CLK_APBGPIO 58
> +#define CLK_APBTIMERS 59
> +#define CLK_APBSYSCNT 60
> +#define CLK_APBWDT 61
> +#define CLK_APBDMA 62
> +#define SL261X_CLK_MAX 63
> +
> +/* cpuss */
> +#define CLK_CPU0 0
> +#define CLK_CPU1 1
> +#define CLK_DSU 2
> +#define SL261X_CPU_CLK_MAX 3
> +
> +
> +/* sysmgr domain */
> +
> +#define CLK_CFG_UART0 0
> +#define CLK_SER_UART0 1
> +#define CLK_CFG_UART1 2
> +#define CLK_CFG_UART2 3
> +#define CLK_CFG_UART3 4
> +#define CLK_CFG_GPIO 5
> +#define CLK_CFG_I2CM0 6
> +#define CLK_CFG_I2CM1 7
> +#define CLK_CFG_SPIM 8
> +#define CLK_CFG_SPIS 9
> +#define CLK_CFG_I3C 10
> +#define CLK_CFG_XSPI 11
> +#define CLK_AXI_XSPI 12
> +#define CLK_CFG_PVT 13
> +#define CLK_CFG_ADC 14
> +#define CLK_CFG_PWM 15
> +#define CLK_BUS_CAN0 16
> +#define CLK_BUS_CAN1 17
> +#define CLK_CFG_PDM 18
> +
> +#define CLK_SER_UART1 19
> +#define CLK_SER_UART2 20
> +#define CLK_SER_UART3 21
> +#define CLK_DEB_GPIO 22
> +#define CLK_SER_I2CM0 23
> +#define CLK_SER_I2CM1 24
> +#define CLK_SER_SPIM 25
> +#define CLK_SER_SPIS 26
> +#define CLK_SER_I3C 27
> +#define CLK_SER_XSPI 28
> +#define CLK_HS_PVT 29
> +#define CLK_CORE_ADC 30
> +#define CLK_SER_PWM 31
> +#define CLK_SER_CAN0 32
> +#define CLK_SER_CAN1 33
> +#define CLK_SER_PDM 34
> +#define CLK_REF_CALIB 35
> +
> +#define CLK_MCU_REF 36
> +#define CLK_MCU_PLL 37
> +#define CLK_MCU_IO_PLL 38
> +#define CLK_MCU_APB 39
> +#define CLK_MCU_AXI 40
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 15/20] dt-bindings: clock: add Synaptics SL261X clock
2026-09-29 6:14 ` [PATCH 15/20] dt-bindings: clock: add Synaptics SL261X clock Jisheng Zhang
2026-09-29 19:46 ` Conor Dooley
@ 2026-09-29 20:49 ` Rob Herring (Arm)
1 sibling, 0 replies; 31+ messages in thread
From: Rob Herring (Arm) @ 2026-09-29 20:49 UTC (permalink / raw)
To: Jisheng Zhang
Cc: linux-clk, Mark Brown, linux-gpio, Frank Li,
Sebastian Hesselbarth, Alexandre Belloni, Greg Kroah-Hartman,
Andi Shyti, Philipp Zabel, Lee Jones, Brian Masney, devicetree,
mfd, Jerome Brunet, linux-spi, Conor Dooley, Krzysztof Kozlowski,
linux-arm-kernel, linux-kernel, linux-serial, Linus Walleij,
Liam Girdwood, Jiri Slaby, Stephen Boyd, linux-i3c, linux-i2c
On Tue, 29 Sep 2026 14:14:12 +0800, Jisheng Zhang wrote:
> Add support for clocks, plls in Synaptics SL261X SoCs.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> .../bindings/clock/syna,sl261x-clk.yaml | 92 ++++++++++++
> include/dt-bindings/clock/syna,sl261x.h | 131 ++++++++++++++++++
> 2 files changed, 223 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml
> create mode 100644 include/dt-bindings/clock/syna,sl261x.h
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/clock/syna,sl261x-clk.example.dtb: syscon@f7e10000 (syscon): compatible: ['syscon', 'simple-mfd'] is too short
from schema $id: http://devicetree.org/schemas/mfd/syscon-common.yaml
Documentation/devicetree/bindings/clock/syna,sl261x-clk.example.dtb: cpu-wrap@f7e30000 (syscon): compatible: ['syscon', 'simple-mfd'] is too short
from schema $id: http://devicetree.org/schemas/mfd/syscon-common.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260929061417.20733-16-jszhang@kernel.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 16/20] clk: berlin: add Synaptics SL261X SoC clocks and plls
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (14 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 15/20] dt-bindings: clock: add Synaptics SL261X clock Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 17/20] dt-bindings: mfd: Add Synaptics SL261x global block binding Jisheng Zhang
` (4 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add support for clocks, plls in Synaptics SL261X SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/clk/Kconfig | 1 +
drivers/clk/berlin/Kconfig | 25 ++
drivers/clk/berlin/Makefile | 4 +
drivers/clk/berlin/sl-clk.c | 279 +++++++++++++++++++++
drivers/clk/berlin/sl-clk.h | 31 +++
drivers/clk/berlin/sl-sysmgr-clk.c | 250 +++++++++++++++++++
drivers/clk/berlin/sl-sysmgr-clk.h | 44 ++++
drivers/clk/berlin/sl261x-clks.c | 385 +++++++++++++++++++++++++++++
drivers/clk/berlin/sl261x-pll.c | 145 +++++++++++
drivers/clk/berlin/sl261x-pll.h | 14 ++
10 files changed, 1178 insertions(+)
create mode 100644 drivers/clk/berlin/Kconfig
create mode 100644 drivers/clk/berlin/sl-clk.c
create mode 100644 drivers/clk/berlin/sl-clk.h
create mode 100644 drivers/clk/berlin/sl-sysmgr-clk.c
create mode 100644 drivers/clk/berlin/sl-sysmgr-clk.h
create mode 100644 drivers/clk/berlin/sl261x-clks.c
create mode 100644 drivers/clk/berlin/sl261x-pll.c
create mode 100644 drivers/clk/berlin/sl261x-pll.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index f9592fd9ec2b..8052db52e28f 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -509,6 +509,7 @@ source "drivers/clk/actions/Kconfig"
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/aspeed/Kconfig"
source "drivers/clk/bcm/Kconfig"
+source "drivers/clk/berlin/Kconfig"
source "drivers/clk/cix/Kconfig"
source "drivers/clk/eswin/Kconfig"
source "drivers/clk/hisilicon/Kconfig"
diff --git a/drivers/clk/berlin/Kconfig b/drivers/clk/berlin/Kconfig
new file mode 100644
index 000000000000..2d5694cd29b7
--- /dev/null
+++ b/drivers/clk/berlin/Kconfig
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config SL_COMMON_CLK
+ bool
+
+config SL_SYSMGR_CLK
+ bool
+
+config SL261X_PLL
+ tristate "Synaptics SL261X PLL Driver"
+ depends on ARCH_BERLIN || COMPILE_TEST
+ default n
+ help
+ This driver provides support for PLLs on Synaptics SL261X SoC.
+
+config SL261X_CLK
+ tristate "Synaptics SL261X Clock Driver"
+ depends on ARCH_BERLIN || COMPILE_TEST
+ select SL_COMMON_CLK
+ select SL_SYSMGR_CLK
+ default n
+ help
+ This driver provides support for clock controller on Synaptics SL261X
+ SoC. The clock controller generates and supplies clocks to various
+ peripherals within the SoC.
diff --git a/drivers/clk/berlin/Makefile b/drivers/clk/berlin/Makefile
index 3733733a4806..2a664782d8a2 100644
--- a/drivers/clk/berlin/Makefile
+++ b/drivers/clk/berlin/Makefile
@@ -3,3 +3,7 @@ obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
obj-$(CONFIG_MACH_BERLIN_BG2) += bg2.o
obj-$(CONFIG_MACH_BERLIN_BG2CD) += bg2.o
obj-$(CONFIG_MACH_BERLIN_BG2Q) += bg2q.o
+obj-$(CONFIG_SL_COMMON_CLK) += sl-clk.o
+obj-$(CONFIG_SL_SYSMGR_CLK) += sl-sysmgr-clk.o
+obj-$(CONFIG_SL261X_PLL) += sl261x-pll.o
+obj-$(CONFIG_SL261X_CLK) += sl261x-clks.o
diff --git a/drivers/clk/berlin/sl-clk.c b/drivers/clk/berlin/sl-clk.c
new file mode 100644
index 000000000000..e212320a0637
--- /dev/null
+++ b/drivers/clk/berlin/sl-clk.c
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Synaptics Incorporated
+ * Copyright (c) 2015 Marvell Technology Group Ltd.
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "sl-clk.h"
+
+#define SL_CLK_EN BIT(0)
+#define SL_CLK_PLL_SEL GENMASK(3, 1)
+#define SL_CLK_PLL_SWITCH BIT(4)
+#define SL_CLK_DIV_SWITCH BIT(5)
+#define SL_CLK_DIV3_SWITCH BIT(6)
+#define SL_CLK_DIV_SEL GENMASK(9, 7)
+#define SL_MAX_PARENTS 6
+
+struct sl_clk {
+ struct clk_hw hw;
+ void __iomem *reg;
+ spinlock_t *lock;
+ struct device *dev;
+};
+
+#define to_sl_clk(_hw) container_of(_hw, struct sl_clk, hw)
+
+static const unsigned int sl_clk_values[] = { 1, 2, 3, 4, 6, 8, 12 };
+
+static unsigned int sl_clk_value(u32 val)
+{
+ static const u8 div_table[] = { 0, 2, 4, 6, 8, 12, 0, 0 };
+
+ if (val & SL_CLK_DIV3_SWITCH)
+ return 3;
+ if (!(val & SL_CLK_DIV_SWITCH))
+ return 1;
+
+ return div_table[FIELD_GET(SL_CLK_DIV_SEL, val)];
+}
+
+static unsigned long sl_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sl_clk *clk = to_sl_clk(hw);
+ unsigned int divisor = sl_clk_value(readl_relaxed(clk->reg));
+
+ if (WARN_ON_ONCE(!divisor))
+ return 0;
+
+ return parent_rate / divisor;
+}
+
+static unsigned int sl_clk_best(unsigned long parent_rate,
+ unsigned long rate)
+{
+ unsigned long best_diff = ULONG_MAX;
+ unsigned int best = 1, i;
+
+ for (i = 0; i < ARRAY_SIZE(sl_clk_values); i++) {
+ unsigned long candidate = parent_rate / sl_clk_values[i];
+ unsigned long diff = candidate > rate ? candidate - rate :
+ rate - candidate;
+
+ if (diff < best_diff) {
+ best_diff = diff;
+ best = sl_clk_values[i];
+ }
+ }
+
+ return best;
+}
+
+static int sl_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+
+ if (!parent)
+ return -EINVAL;
+
+ req->best_parent_hw = parent;
+ req->best_parent_rate = clk_hw_get_rate(parent);
+ req->rate = req->best_parent_rate /
+ sl_clk_best(req->best_parent_rate, req->rate);
+
+ return 0;
+}
+
+static int sl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sl_clk *clk = to_sl_clk(hw);
+ unsigned int divisor, select;
+ unsigned long flags;
+ u32 val;
+
+ divisor = sl_clk_best(parent_rate, rate);
+ if (parent_rate / divisor != rate)
+ return -EINVAL;
+
+ spin_lock_irqsave(clk->lock, flags);
+ val = readl_relaxed(clk->reg);
+ val &= ~(SL_CLK_DIV3_SWITCH | SL_CLK_DIV_SWITCH |
+ SL_CLK_DIV_SEL);
+ if (divisor == 3) {
+ val |= SL_CLK_DIV3_SWITCH;
+ } else if (divisor != 1) {
+ switch (divisor) {
+ case 2:
+ select = 1;
+ break;
+ case 4:
+ select = 2;
+ break;
+ case 6:
+ select = 3;
+ break;
+ case 8:
+ select = 4;
+ break;
+ case 12:
+ select = 5;
+ break;
+ default:
+ spin_unlock_irqrestore(clk->lock, flags);
+ return -EINVAL;
+ }
+ val |= SL_CLK_DIV_SWITCH |
+ FIELD_PREP(SL_CLK_DIV_SEL, select);
+ }
+ writel_relaxed(val, clk->reg);
+ spin_unlock_irqrestore(clk->lock, flags);
+
+ return 0;
+}
+
+static u8 sl_clk_get_parent(struct clk_hw *hw)
+{
+ struct sl_clk *clk = to_sl_clk(hw);
+ u32 val = readl_relaxed(clk->reg);
+ u8 selector;
+ unsigned int index;
+
+ if (!(val & SL_CLK_PLL_SWITCH))
+ return 0;
+
+ selector = FIELD_GET(SL_CLK_PLL_SEL, val);
+ index = selector + 1;
+ if (index < clk_hw_get_num_parents(hw))
+ return index;
+
+ dev_warn(clk->dev, "%s: unsupported parent selector %u\n",
+ clk_hw_get_name(hw), selector);
+ return 0;
+}
+
+static int sl_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct sl_clk *clk = to_sl_clk(hw);
+ unsigned long flags;
+ u32 val;
+
+ if (index >= clk_hw_get_num_parents(hw) || index >= SL_MAX_PARENTS)
+ return -EINVAL;
+
+ spin_lock_irqsave(clk->lock, flags);
+ val = readl_relaxed(clk->reg);
+ if (!index) {
+ val &= ~SL_CLK_PLL_SWITCH;
+ } else {
+ val &= ~SL_CLK_PLL_SEL;
+ val |= SL_CLK_PLL_SWITCH |
+ FIELD_PREP(SL_CLK_PLL_SEL, index - 1);
+ }
+ writel_relaxed(val, clk->reg);
+ spin_unlock_irqrestore(clk->lock, flags);
+
+ return 0;
+}
+
+static int sl_clk_enable(struct clk_hw *hw)
+{
+ struct sl_clk *clk = to_sl_clk(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(clk->lock, flags);
+ val = readl_relaxed(clk->reg);
+ writel_relaxed(val | SL_CLK_EN, clk->reg);
+ spin_unlock_irqrestore(clk->lock, flags);
+
+ return 0;
+}
+
+static void sl_clk_disable(struct clk_hw *hw)
+{
+ struct sl_clk *clk = to_sl_clk(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(clk->lock, flags);
+ val = readl_relaxed(clk->reg);
+ writel_relaxed(val & ~SL_CLK_EN, clk->reg);
+ spin_unlock_irqrestore(clk->lock, flags);
+}
+
+static int sl_clk_is_enabled(struct clk_hw *hw)
+{
+ struct sl_clk *clk = to_sl_clk(hw);
+
+ return !!(readl_relaxed(clk->reg) & SL_CLK_EN);
+}
+
+static const struct clk_ops sl_clk_ops = {
+ .get_parent = sl_clk_get_parent,
+ .set_parent = sl_clk_set_parent,
+ .recalc_rate = sl_clk_recalc_rate,
+ .determine_rate = sl_clk_determine_rate,
+ .set_rate = sl_clk_set_rate,
+ .enable = sl_clk_enable,
+ .disable = sl_clk_disable,
+ .is_enabled = sl_clk_is_enabled,
+};
+
+struct clk_hw *sl_clk_register(struct device *dev, void __iomem *reg,
+ const char *name, const char * const *parent_names,
+ unsigned int num_parents, unsigned long flags,
+ spinlock_t *lock)
+{
+ struct clk_init_data init = {};
+ struct sl_clk *clk;
+ unsigned int i;
+ int ret;
+
+ if (!dev || !reg || !name || !parent_names || !num_parents ||
+ num_parents > SL_MAX_PARENTS || !lock)
+ return ERR_PTR(-EINVAL);
+
+ for (i = 0; i < num_parents; i++)
+ if (!parent_names[i])
+ return ERR_PTR(-EINVAL);
+
+ clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return ERR_PTR(-ENOMEM);
+
+ clk->dev = dev;
+ clk->reg = reg;
+ clk->lock = lock;
+
+ init.name = name;
+ init.ops = &sl_clk_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = flags;
+ clk->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &clk->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &clk->hw;
+}
+EXPORT_SYMBOL_GPL(sl_clk_register);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Synaptics SL261x clock divider support");
diff --git a/drivers/clk/berlin/sl-clk.h b/drivers/clk/berlin/sl-clk.h
new file mode 100644
index 000000000000..7489b26a5e8d
--- /dev/null
+++ b/drivers/clk/berlin/sl-clk.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SL_CLK_H
+#define __SL_CLK_H
+
+#include <linux/compiler_types.h>
+#include <linux/spinlock_types.h>
+
+struct clk_hw;
+struct device;
+
+struct sl_clk_desc {
+ const char *name;
+ u32 id;
+ u32 offset;
+ unsigned long flags;
+};
+
+struct sl_gateclk_desc {
+ const char *name;
+ const char *parent_name;
+ u32 id;
+ u8 bit_idx;
+ unsigned long flags;
+};
+
+struct clk_hw *sl_clk_register(struct device *dev, void __iomem *reg,
+ const char *name, const char * const *parent_names,
+ unsigned int num_parents, unsigned long flags,
+ spinlock_t *lock);
+
+#endif /* __SL_CLK_H */
diff --git a/drivers/clk/berlin/sl-sysmgr-clk.c b/drivers/clk/berlin/sl-sysmgr-clk.c
new file mode 100644
index 000000000000..fba8c22ca830
--- /dev/null
+++ b/drivers/clk/berlin/sl-sysmgr-clk.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+
+#include "sl-sysmgr-clk.h"
+
+#define CLK_EN BIT(0)
+#define DIV_CHNG_EN BIT(1)
+
+struct sl_sysmgr_gateclk {
+ struct clk_hw hw;
+ void __iomem *base;
+ u8 bit_idx;
+};
+
+struct sl_sysmgr_clk {
+ struct clk_hw hw;
+ void __iomem *base;
+ u8 div_bits;
+};
+
+struct sl_sysmgr_clk_priv {
+ struct sl_sysmgr_gateclk *gclks;
+ struct sl_sysmgr_clk *clks;
+};
+
+static DEFINE_SPINLOCK(sl_sysmgr_gateclk_lock);
+
+#define to_sl_sysmgr_gateclk(hw) container_of(hw, struct sl_sysmgr_gateclk, hw)
+#define to_sl_sysmgr_clk(hw) container_of(hw, struct sl_sysmgr_clk, hw)
+
+static int sl_sysmgr_gateclk_enable(struct clk_hw *hw)
+{
+ u32 val;
+ struct sl_sysmgr_gateclk *clk = to_sl_sysmgr_gateclk(hw);
+
+ guard(spinlock)(&sl_sysmgr_gateclk_lock);
+
+ val = readl_relaxed(clk->base);
+ if (!(val & BIT(clk->bit_idx))) {
+ val |= BIT(clk->bit_idx);
+ writel_relaxed(val, clk->base);
+ }
+
+ return 0;
+}
+
+static int sl_sysmgr_gateclk_is_enabled(struct clk_hw *hw)
+{
+ u32 val;
+ struct sl_sysmgr_gateclk *clk = to_sl_sysmgr_gateclk(hw);
+
+ guard(spinlock)(&sl_sysmgr_gateclk_lock);
+
+ val = readl_relaxed(clk->base);
+ val &= BIT(clk->bit_idx);
+
+ return val ? 1 : 0;
+}
+
+static const struct clk_ops sl_sysmgr_gateclk_ops = {
+ .enable = sl_sysmgr_gateclk_enable,
+ .is_enabled = sl_sysmgr_gateclk_is_enabled,
+};
+
+static int
+sl_sysmgr_gateclk_register(struct device *dev, struct sl_sysmgr_gateclk *gclk,
+ const char *name, const char *parent_names,
+ u8 bit_idx, void __iomem *base)
+{
+ struct clk_init_data init;
+
+ init.name = name;
+ init.ops = &sl_sysmgr_gateclk_ops;
+ init.parent_names = &parent_names;
+ init.num_parents = 1;
+ init.flags = 0;
+
+ gclk->bit_idx = bit_idx;
+ gclk->base = base;
+ gclk->hw.init = &init;
+
+ return devm_clk_hw_register(dev, &gclk->hw);
+}
+
+static unsigned long
+sl_sysmgr_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ u32 val, div;
+ struct sl_sysmgr_clk *clk = to_sl_sysmgr_clk(hw);
+
+ val = readl_relaxed(clk->base);
+ div = (val >> 2) & ((1 << clk->div_bits) - 1);
+ ++div;
+
+ return parent_rate / div;
+}
+
+static int sl_sysmgr_clk_enable(struct clk_hw *hw)
+{
+ u32 val;
+ struct sl_sysmgr_clk *clk = to_sl_sysmgr_clk(hw);
+
+ val = readl_relaxed(clk->base);
+ if (!(val & CLK_EN)) {
+ val |= CLK_EN;
+ writel_relaxed(val, clk->base);
+ }
+
+ return 0;
+}
+
+static int sl_sysmgr_clk_is_enabled(struct clk_hw *hw)
+{
+ u32 val;
+ struct sl_sysmgr_clk *clk = to_sl_sysmgr_clk(hw);
+
+ val = readl_relaxed(clk->base);
+ val &= CLK_EN;
+
+ return val ? 1 : 0;
+}
+
+static const struct clk_ops sl_sysmgr_clk_ops = {
+ .recalc_rate = sl_sysmgr_clk_recalc_rate,
+ .enable = sl_sysmgr_clk_enable,
+ .is_enabled = sl_sysmgr_clk_is_enabled,
+};
+
+static int
+sl_sysmgr_clk_register(struct device *dev, struct sl_sysmgr_clk *sclk,
+ const char *name, const char *parent_names,
+ u8 div_bits, void __iomem *base)
+{
+ struct clk_init_data init;
+
+ init.name = name;
+ init.ops = &sl_sysmgr_clk_ops;
+ init.parent_names = &parent_names;
+ init.num_parents = 1;
+ init.flags = 0;
+
+ sclk->div_bits = div_bits;
+ sclk->base = base;
+ sclk->hw.init = &init;
+
+ return devm_clk_hw_register(dev, &sclk->hw);
+}
+
+static void sl_sysmgr_clk_put_node(void *data)
+{
+ of_node_put(data);
+}
+
+int sl_sysmgr_clk_setup(struct platform_device *pdev,
+ const struct sl_sysmgr_fixedclk_desc *fdescs,
+ int fclk_n,
+ const struct sl_sysmgr_gateclk_desc *gdescs,
+ int gclk_n,
+ u32 gclk_offset,
+ const struct sl_sysmgr_clk_desc *descs,
+ int clk_n)
+{
+ struct device_node *parent_np = of_get_parent(pdev->dev.of_node);
+ int i, ret, num = fclk_n + gclk_n + clk_n;
+ struct clk_hw_onecell_data *clk_data;
+ struct sl_sysmgr_clk_priv *priv;
+ struct clk_hw *clk_hw;
+ void __iomem *base;
+ u32 id;
+
+ ret = devm_add_action_or_reset(&pdev->dev, sl_sysmgr_clk_put_node, parent_np);
+ if (ret)
+ return ret;
+
+ clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, num), GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+ clk_data->num = num;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->gclks = devm_kcalloc(&pdev->dev, gclk_n, sizeof(*priv->gclks), GFP_KERNEL);
+ if (!priv->gclks)
+ return -ENOMEM;
+
+ priv->clks = devm_kcalloc(&pdev->dev, clk_n, sizeof(*priv->clks), GFP_KERNEL);
+ if (!priv->clks)
+ return -ENOMEM;
+
+ base = devm_of_iomap(&pdev->dev, parent_np, 0, NULL);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ for (i = 0; i < fclk_n; i++) {
+ clk_hw = devm_clk_hw_register_fixed_rate(&pdev->dev, fdescs[i].name,
+ NULL, 0,
+ fdescs[i].rate);
+ if (IS_ERR(clk_hw))
+ return PTR_ERR(clk_hw);
+
+ id = fdescs[i].id;
+ clk_data->hws[id] = clk_hw;
+ }
+
+ for (i = 0; i < gclk_n; i++) {
+ ret = sl_sysmgr_gateclk_register(&pdev->dev, &priv->gclks[i],
+ gdescs[i].name, gdescs[i].parent_name,
+ gdescs[i].bit_idx, base + gclk_offset);
+ if (ret)
+ return ret;
+
+ id = gdescs[i].id;
+ clk_data->hws[id] = &priv->gclks[i].hw;
+ }
+
+ for (i = 0; i < clk_n; i++) {
+ ret = sl_sysmgr_clk_register(&pdev->dev, &priv->clks[i],
+ descs[i].name, descs[i].parent_name,
+ descs[i].div_bits, base + descs[i].offset);
+ if (ret)
+ return ret;
+
+ id = descs[i].id;
+ clk_data->hws[id] = &priv->clks[i].hw;
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, clk_data);
+}
+EXPORT_SYMBOL_GPL(sl_sysmgr_clk_setup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
+MODULE_DESCRIPTION("SysMgr domain clk driver for Synaptics SL SoCs");
diff --git a/drivers/clk/berlin/sl-sysmgr-clk.h b/drivers/clk/berlin/sl-sysmgr-clk.h
new file mode 100644
index 000000000000..5ccf388bcccb
--- /dev/null
+++ b/drivers/clk/berlin/sl-sysmgr-clk.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2026 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ *
+ */
+
+#ifndef __SL_SYSMGR_CLK_H
+#define __SL_SYSMGR_CLK_H
+
+struct sl_sysmgr_clk_desc {
+ const char *name;
+ const char *parent_name;
+ u32 id;
+ u32 offset;
+ u8 div_bits;
+ unsigned long flags;
+};
+
+struct sl_sysmgr_gateclk_desc {
+ const char *name;
+ const char *parent_name;
+ u32 id;
+ u8 bit_idx;
+ unsigned long flags;
+};
+
+struct sl_sysmgr_fixedclk_desc {
+ const char *name;
+ u32 id;
+ unsigned long rate;
+};
+
+int sl_sysmgr_clk_setup(struct platform_device *pdev,
+ const struct sl_sysmgr_fixedclk_desc *fdescs,
+ int fclk_n,
+ const struct sl_sysmgr_gateclk_desc *gdescs,
+ int gclk_n,
+ u32 gclk_offset,
+ const struct sl_sysmgr_clk_desc *descs,
+ int clk_n);
+
+#endif
diff --git a/drivers/clk/berlin/sl261x-clks.c b/drivers/clk/berlin/sl261x-clks.c
new file mode 100644
index 000000000000..d4e9cee7b685
--- /dev/null
+++ b/drivers/clk/berlin/sl261x-clks.c
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+
+#include <dt-bindings/clock/syna,sl261x.h>
+
+#include "sl261x-pll.h"
+#include "sl-clk.h"
+#include "sl-sysmgr-clk.h"
+
+#define REG_CLKENABLE 0x0420
+
+#define CLK_GATE_CTRL0 0x0600
+
+#define SYSPLL0_OFFSET 0x0200
+#define SYSPLL1_OFFSET 0x0220
+#define CPUPLL_OFFSET 0x2000
+#define APLL0_OFFSET 0x0008
+#define APLL1_OFFSET 0x0030
+
+static DEFINE_SPINLOCK(gate_lock);
+static DEFINE_SPINLOCK(lock);
+
+enum {
+ SYSPLL0_OUT, SYSPLL0_OUTF,
+ SYSPLL1_OUT, SYSPLL1_OUTF,
+ CPUPLL_OUT, CPUPLL_OUTF,
+ APLL0_OUT, APLL0_OUTF,
+ APLL1_OUT, APLL1_OUTF,
+};
+
+static const char *clk_names[] = {
+ [SYSPLL0_OUT] = "syspll0_out",
+ [SYSPLL0_OUTF] = "syspll0_outf",
+ [SYSPLL1_OUT] = "syspll1_out",
+ [SYSPLL1_OUTF] = "syspll1_outf",
+ [CPUPLL_OUT] = "cpupll_out",
+ [CPUPLL_OUTF] = "cpupll_outf",
+ [APLL0_OUT] = "apll0_out",
+ [APLL0_OUTF] = "apll0_outf",
+ [APLL1_OUT] = "apll1_out",
+ [APLL1_OUTF] = "apll1_outf",
+};
+
+static const struct sl_gateclk_desc sl261x_gates[] = {
+ { "usb0coreclk", "perifsysclk", CLK_USB0CORE, 0 },
+ { "sdiosysclk", "perifsysclk", CLK_SDIOSYS, 1 },
+ { "emmcsysclk", "perifsysclk", CLK_EMMCSYS, 2 },
+ { "gpuaxiclk", "hpcclk", CLK_GPUAXI, 3 },
+ { "gethrgmiisysclk", "perifsysclk", CLK_GETHRGMIISYS, 4 },
+ { "sdio1sysclk", "perifsysclk", CLK_SDIO1SYS, 5 },
+ { "usb1coreclk", "perifsysclk", CLK_USB1CORE, 6 },
+ { "gethrgmii1sysclk", "perifsysclk", CLK_GETHRGMII1SYS, 7 },
+ { "usb0phyrefclk", "perifsysclk", CLK_USB0PHYREF, 8 },
+ { "usb1phyrefclk", "perifsysclk", CLK_USB1PHYREF, 9 },
+ { "apbuart0clk", "apbcoreclk", CLK_APBUART0, 10 },
+ { "apbuart1clk", "apbcoreclk", CLK_APBUART1, 11 },
+ { "apbuart2clk", "apbcoreclk", CLK_APBUART2, 12 },
+ { "apbuart3lck", "apbcoreclk", CLK_APBUART3, 13 },
+ { "apbi2c0clk", "apbcoreclk", CLK_APBI2C0, 14 },
+ { "apbi2c1lck", "apbcoreclk", CLK_APBI2C1, 15 },
+ { "apbspi0clk", "apbcoreclk", CLK_APBSPI0, 16 },
+ { "apbspi1clk", "apbcoreclk", CLK_APBSPI1, 17 },
+ { "apbspi2clk", "apbcoreclk", CLK_APBSPI2, 18 },
+ { "apbspi3clk", "apbcoreclk", CLK_APBSPI3, 19 },
+ { "apbgpioclk", "apbcoreclk", CLK_APBGPIO, 20 },
+ { "apbtimersclk", "apbcoreclk", CLK_APBTIMERS, 21 },
+ { "apbsyscntclk", "apbcoreclk", CLK_APBSYSCNT, 22 },
+ { "apbwdtclk", "apbcoreclk", CLK_APBWDT, 23 },
+ { "apbdmaclk", "apbcoreclk", CLK_APBDMA, 24 },
+};
+
+static const struct sl_clk_desc sl261x_descs[] = {
+ { "cpufastrefclk", CLK_CPUFASTREF, 0x440, CLK_IS_CRITICAL },
+ { "memfastrefclk", CLK_MEMFASTREF, 0x444, CLK_IS_CRITICAL },
+ { "cfgclk", CLK_CFG, 0x448, CLK_IS_CRITICAL },
+ { "sysclk", CLK_SYS, 0x44c, CLK_IS_CRITICAL },
+ { "perifsysclk", CLK_PERIFSYS, 0x450, CLK_IS_CRITICAL },
+ { "apbcoreclk", CLK_APBCORE, 0x454, CLK_IS_CRITICAL },
+ { "apbserclk", CLK_APBSER, 0x458, CLK_IS_CRITICAL },
+ { "atbclk", CLK_ATB, 0x45c },
+ { "hpcclk", CLK_HPC, 0x460, CLK_IS_CRITICAL },
+ { "emmcclk", CLK_EMMC, 0x464 },
+ { "sd0clk", CLK_SD0, 0x468 },
+ { "sd1clk", CLK_SD1, 0x46c },
+ { "gethrgmiiclk", CLK_GETHRGMII, 0x470 },
+ { "gethrgmii1clk", CLK_GETHRGMII1, 0x474 },
+ { "ge0_ptp_refclk", CLK_GE0_PTP_REF, 0x478 },
+ { "ge1_ptp_refclk", CLK_GE1_PTP_REF, 0x47c },
+ { "usb2testclk", CLK_USB2TEST, 0x480 },
+ { "usb2test480mg0clk", CLK_USB2TEST480MG0, 0x484 },
+ { "usb2test480mg1clk", CLK_USB2TEST480MG1, 0x488 },
+ { "usb2test480mg2clk", CLK_USB2TEST480MG2, 0x48c },
+ { "usb2test100mg0clk", CLK_USB2TEST100MG0, 0x490 },
+ { "usb2test100mg1clk", CLK_USB2TEST100MG1, 0x494 },
+ { "usb2test100mg2clk", CLK_USB2TEST100MG2, 0x498 },
+ { "usb2test100mg3clk", CLK_USB2TEST100MG3, 0x49c },
+ { "periftest125mg0clk", CLK_PERIFTEST125MG0, 0x4a0 },
+ { "periftest200mg0clk", CLK_PERIFTEST200MG0, 0x4a4 },
+ { "periftest200mg1clk", CLK_PERIFTEST200MG1, 0x4a8 },
+ { "gpuclk", CLK_GPU, 0x4ac },
+ { "npuclk", CLK_NPU, 0x4b0 },
+ { "aviosysclk", CLK_AVIOSYS, 0x4b4, CLK_IS_CRITICAL },
+ { "aiosysclk", CLK_AIOSYS, 0x4b8, CLK_IS_CRITICAL },
+ { "avio_lcdc2scanclk", CLK_AVIO_LCDC2SCAN, 0x4bc },
+ { "avio_ipiclk", CLK_AVIO_IPI, 0x4c0 },
+ { "avio_pclk", CLK_AVIO_P, 0x4c4 },
+ { "avio_dphyrxtxescclk", CLK_AVIO_DPHYRXTXESC, 0x4c8 },
+ { "aviofpllclk", CLK_AVIOFPLL, 0x4cc },
+ { "avio_rx_scanbyteclk", CLK_AVIO_RX_SCANBYTE, 0x4d0 },
+ { "avio_rx_scantestclk", CLK_AVIO_RX_SCANTEST, 0x4d4 },
+};
+
+static const char *default_parent_names[] = {
+ "syspll0_out",
+ "apll0_out",
+ "syspll0_outf",
+ "apll0_outf",
+ "syspll1_out",
+ "syspll1_outf",
+};
+
+static const char *ge_ptp_refclk_parent_names[] = {
+ "osc",
+ "apll0_outf",
+ "syspll1_out",
+ "syspll0_out",
+ "clk_mcu_axi",
+};
+
+static int sl261x_soc_clk_setup(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *parent_np = of_get_parent(np);
+ struct clk_hw_onecell_data *clk_data;
+ const char **parent_names;
+ int num_parents;
+ void __iomem *base;
+ struct clk_hw **hws;
+ int n, ret;
+ u32 id;
+
+ base = devm_of_iomap(dev, parent_np, 0, NULL);
+ of_node_put(parent_np);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, SL261X_CLK_MAX), GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+ clk_data->num = SL261X_CLK_MAX;
+ hws = clk_data->hws;
+
+ /* sysplls */
+ ret = sl261x_pll_register(dev, base + SYSPLL0_OFFSET,
+ clk_names[SYSPLL0_OUT], clk_names[SYSPLL0_OUTF]);
+ if (ret)
+ return ret;
+ ret = sl261x_pll_register(dev, base + SYSPLL1_OFFSET,
+ clk_names[SYSPLL1_OUT], clk_names[SYSPLL1_OUTF]);
+ if (ret)
+ return ret;
+
+ /* normal clocks */
+ for (n = 0; n < ARRAY_SIZE(sl261x_descs); n++) {
+ const struct sl_clk_desc *cd = &sl261x_descs[n];
+
+ id = cd->id;
+ if (id == CLK_GE0_PTP_REF || id == CLK_GE1_PTP_REF) {
+ parent_names = ge_ptp_refclk_parent_names;
+ num_parents = ARRAY_SIZE(ge_ptp_refclk_parent_names);
+ } else {
+ parent_names = default_parent_names;
+ num_parents = ARRAY_SIZE(default_parent_names);
+ }
+ hws[id] = sl_clk_register(dev, base + cd->offset, cd->name,
+ parent_names, num_parents, cd->flags, &lock);
+ if (IS_ERR(hws[id]))
+ return PTR_ERR(hws[id]);
+ }
+
+ /* gate clocks */
+ for (n = 0; n < ARRAY_SIZE(sl261x_gates); n++) {
+ const struct sl_gateclk_desc *gd = &sl261x_gates[n];
+
+ id = gd->id;
+ hws[id] = devm_clk_hw_register_gate(dev, gd->name, gd->parent_name,
+ gd->flags, base + REG_CLKENABLE,
+ gd->bit_idx, 0, &gate_lock);
+ if (IS_ERR(hws[id]))
+ return PTR_ERR(hws[id]);
+ }
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
+}
+
+static int sl261x_cpu_clk_setup(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *parent_np = of_get_parent(np);
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **hws;
+ void __iomem *base;
+ int ret;
+
+ base = devm_of_iomap(dev, parent_np, 0, NULL);
+ of_node_put(parent_np);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, SL261X_CPU_CLK_MAX), GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+ clk_data->num = SL261X_CPU_CLK_MAX;
+ hws = clk_data->hws;
+
+ /* cpupll */
+ ret = sl261x_pll_register(dev, base + CPUPLL_OFFSET,
+ clk_names[CPUPLL_OUT], clk_names[CPUPLL_OUTF]);
+ if (ret)
+ return ret;
+
+ /* TODO: support cpupll bypass */
+ hws[CLK_CPU0] =
+ devm_clk_hw_register_fixed_factor(dev, "cpu0", clk_names[CPUPLL_OUTF], 0, 1, 1);
+ if (IS_ERR(hws[CLK_CPU0]))
+ return PTR_ERR(hws[CLK_CPU0]);
+ hws[CLK_CPU1] =
+ devm_clk_hw_register_fixed_factor(dev, "cpu1", clk_names[CPUPLL_OUTF], 0, 1, 1);
+ if (IS_ERR(hws[CLK_CPU1]))
+ return PTR_ERR(hws[CLK_CPU1]);
+ hws[CLK_DSU] =
+ devm_clk_hw_register_fixed_factor(dev, "dsu", clk_names[CPUPLL_OUT], 0, 1, 1);
+ if (IS_ERR(hws[CLK_DSU]))
+ return PTR_ERR(hws[CLK_DSU]);
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
+}
+
+static int sl261x_aio_clk_setup(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *parent_np = of_get_parent(np);
+ void __iomem *base;
+ int ret;
+
+ base = devm_of_iomap(dev, parent_np, 0, NULL);
+ of_node_put(parent_np);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ /* aplls */
+ ret = sl261x_pll_register(dev, base + APLL0_OFFSET,
+ clk_names[APLL0_OUT], clk_names[APLL0_OUTF]);
+ if (ret)
+ return ret;
+ ret = sl261x_pll_register(dev, base + APLL1_OFFSET,
+ clk_names[APLL1_OUT], clk_names[APLL1_OUTF]);
+ if (ret)
+ return ret;
+
+ /* TODO aio clks */
+
+ return 0;
+}
+
+static const struct sl_sysmgr_fixedclk_desc sl261x_sysmgr_fixeds[] = {
+ { "clk_mcu_ref", CLK_MCU_REF, 25000000 },
+ { "clk_mcu_pll", CLK_MCU_PLL, 400000000 },
+ { "clk_mcu_io_pll", CLK_MCU_IO_PLL, 300000000 },
+ { "clk_mcu_apb", CLK_MCU_APB, 100000000 },
+ { "clk_mcu_axi", CLK_MCU_AXI, 200000000 },
+};
+
+static const struct sl_sysmgr_gateclk_desc sl261x_sysmgr_gates[] = {
+ { "clk_cfg_uart0", "clk_mcu_apb", CLK_CFG_UART0, 0 },
+ { "clk_ser_uart0", "clk_mcu_ref", CLK_SER_UART0, 1 },
+ { "clk_cfg_uart1", "clk_mcu_apb", CLK_CFG_UART1, 2 },
+ { "clk_cfg_uart2", "clk_mcu_apb", CLK_CFG_UART2, 3 },
+ { "clk_cfg_uart3", "clk_mcu_apb", CLK_CFG_UART3, 4 },
+ { "clk_cfg_gpio", "clk_mcu_apb", CLK_CFG_GPIO, 5 },
+ { "clk_cfg_i2cm0", "clk_mcu_apb", CLK_CFG_I2CM0, 6 },
+ { "clk_cfg_i2cm1", "clk_mcu_apb", CLK_CFG_I2CM1, 7 },
+ { "clk_cfg_spim", "clk_mcu_apb", CLK_CFG_SPIM, 8 },
+ { "clk_cfg_spis", "clk_mcu_apb", CLK_CFG_SPIS, 9 },
+ { "clk_cfg_i3c", "clk_mcu_apb", CLK_CFG_I3C, 10 },
+ { "clk_cfg_xspi", "clk_mcu_apb", CLK_CFG_XSPI, 11 },
+ { "clk_axi_xspi", "clk_mcu_axi", CLK_AXI_XSPI, 12 },
+ { "clk_cfg_pvt", "clk_mcu_apb", CLK_CFG_PVT, 13 },
+ { "clk_cfg_adc", "clk_mcu_apb", CLK_CFG_ADC, 14 },
+ { "clk_cfg_pwm", "clk_mcu_apb", CLK_CFG_PWM, 15 },
+ { "clk_bus_can0", "clk_mcu_axi", CLK_BUS_CAN0, 16 },
+ { "clk_bus_can1", "clk_mcu_axi", CLK_BUS_CAN1, 17 },
+ { "clk_cfg_pdm", "clk_mcu_apb", CLK_CFG_PDM, 18 },
+};
+
+static const struct sl_sysmgr_clk_desc sl261x_sysmgr_clks[] = {
+ { "clk_ser_uart1", "clk_mcu_pll", CLK_SER_UART1, 0x604, 4 },
+ { "clk_ser_uart2", "clk_mcu_pll", CLK_SER_UART2, 0x608, 4 },
+ { "clk_ser_uart3", "clk_mcu_pll", CLK_SER_UART3, 0x60c, 4 },
+ { "clk_deb_gpio", "clk_mcu_pll", CLK_DEB_GPIO, 0x610, 4 },
+ { "clk_ser_i2cm0", "clk_mcu_pll", CLK_SER_I2CM0, 0x614, 4 },
+ { "clk_ser_i2cm1", "clk_mcu_pll", CLK_SER_I2CM1, 0x618, 4 },
+ { "clk_ser_spim", "clk_mcu_pll", CLK_SER_SPIM, 0x61c, 4 },
+ { "clk_ser_spis", "clk_mcu_pll", CLK_SER_SPIS, 0x620, 4 },
+ { "clk_ser_i3c", "clk_mcu_pll", CLK_SER_I3C, 0x624, 4 },
+ { "clk_ser_xspi", "clk_mcu_io_pll", CLK_SER_XSPI, 0x628, 4 },
+ { "clk_hs_pvt", "clk_mcu_pll", CLK_HS_PVT, 0x62c, 4 },
+ { "clk_core_adc", "clk_mcu_pll", CLK_CORE_ADC, 0x630, 8 },
+ { "clk_ser_pwm", "clk_mcu_pll", CLK_SER_PWM, 0x634, 4 },
+ { "clk_ser_can0", "clk_mcu_pll", CLK_SER_CAN0, 0x638, 4 },
+ { "clk_ser_can1", "clk_mcu_pll", CLK_SER_CAN1, 0x63c, 4 },
+ { "clk_ser_pdm", "clk_mcu_pll", CLK_SER_PDM, 0x640, 8 },
+ { "clk_ref_calib", "clk_mcu_pll", CLK_REF_CALIB, 0x644, 8 },
+};
+
+static int sl261x_sysmgr_clk_setup(struct platform_device *pdev)
+{
+ return sl_sysmgr_clk_setup(pdev, sl261x_sysmgr_fixeds, ARRAY_SIZE(sl261x_sysmgr_fixeds),
+ sl261x_sysmgr_gates, ARRAY_SIZE(sl261x_sysmgr_gates),
+ CLK_GATE_CTRL0,
+ sl261x_sysmgr_clks, ARRAY_SIZE(sl261x_sysmgr_clks));
+}
+
+static const struct of_device_id sl261x_clks_match_table[] = {
+ {
+ .compatible = "syna,sl261x-soc-clk",
+ .data = sl261x_soc_clk_setup,
+ },
+ {
+ .compatible = "syna,sl261x-cpu-clk",
+ .data = sl261x_cpu_clk_setup,
+ },
+ {
+ .compatible = "syna,sl261x-aio-clk",
+ .data = sl261x_aio_clk_setup,
+ },
+ {
+ .compatible = "syna,sl261x-system-clk",
+ .data = sl261x_sysmgr_clk_setup,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sl261x_clks_match_table);
+
+static int sl261x_clks_probe(struct platform_device *pdev)
+{
+ int (*clk_setup)(struct platform_device *pdev);
+ int ret;
+
+ clk_setup = of_device_get_match_data(&pdev->dev);
+ if (!clk_setup)
+ return -ENODEV;
+
+ ret = clk_setup(pdev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct platform_driver sl261x_clks_driver = {
+ .probe = sl261x_clks_probe,
+ .driver = {
+ .name = "syna-sl261x-clks",
+ .of_match_table = sl261x_clks_match_table,
+ },
+};
+module_platform_driver(sl261x_clks_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
+MODULE_DESCRIPTION("Synaptics sl261x clks Driver");
diff --git a/drivers/clk/berlin/sl261x-pll.c b/drivers/clk/berlin/sl261x-pll.c
new file mode 100644
index 000000000000..ce19a6043da1
--- /dev/null
+++ b/drivers/clk/berlin/sl261x-pll.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2021 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/container_of.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_clk.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "sl261x-pll.h"
+
+#define FRAC_BITS 24
+
+#define CTRLC 0x08
+#define DIVR_MASK GENMASK(8, 0)
+#define CTRLD 0x0c
+#define DIVF_MASK GENMASK(8, 0)
+#define CTRLE 0x10
+#define DIVFF_MASK GENMASK(23, 0)
+#define CTRLF 0x14
+#define DIVQ_MASK GENMASK(4, 0)
+#define CTRLG 0x18
+#define DIVQF_MASK GENMASK(2, 0)
+
+#define SL261X_APLL
+struct sl261x_pll {
+ void __iomem *ctrl;
+ struct clk_hw pllout;
+ struct clk_hw plloutf;
+};
+
+#define to_pllout(_hw) container_of(_hw, struct sl261x_pll, pllout)
+#define to_plloutf(_hw) container_of(_hw, struct sl261x_pll, plloutf)
+
+static unsigned long sl261x_pll_recalc_rate(struct sl261x_pll *pll,
+ unsigned long parent_rate, bool fractional_output)
+{
+ u32 dm, dn, frac, dp;
+ u64 rate;
+
+ dm = (readl_relaxed(pll->ctrl + CTRLC) & DIVR_MASK) + 1;
+ dn = (readl_relaxed(pll->ctrl + CTRLD) & DIVF_MASK) + 1;
+ frac = readl_relaxed(pll->ctrl + CTRLE) & DIVFF_MASK;
+
+ if (fractional_output)
+ dp = (readl_relaxed(pll->ctrl + CTRLG) & DIVQF_MASK) + 1;
+ else
+ dp = ((readl_relaxed(pll->ctrl + CTRLF) & DIVQ_MASK) + 1) * 2;
+
+ rate = (u64)parent_rate * dn;
+ rate += ((u64)parent_rate * frac + BIT_ULL(FRAC_BITS - 1)) >> FRAC_BITS;
+ rate = DIV_ROUND_CLOSEST_ULL(rate * 4, dm * dp);
+
+ return rate;
+}
+
+static unsigned long sl261x_pllout_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return sl261x_pll_recalc_rate(to_pllout(hw), parent_rate, false);
+}
+
+static unsigned long sl261x_plloutf_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return sl261x_pll_recalc_rate(to_plloutf(hw), parent_rate, true);
+}
+
+static const struct clk_ops sl261x_pllout_ops = {
+ .recalc_rate = sl261x_pllout_recalc_rate,
+};
+
+static const struct clk_ops sl261x_plloutf_ops = {
+ .recalc_rate = sl261x_plloutf_recalc_rate,
+};
+
+static void sl261x_pll_put_clk(void *data)
+{
+ clk_put(data);
+}
+
+int sl261x_pll_register(struct device *dev, void __iomem *ctrl,
+ const char *out, const char *outf)
+{
+ struct device_node *np = dev->of_node;
+ struct clk_parent_data parent = {};
+ struct clk_init_data init = {};
+ struct sl261x_pll *pll;
+ struct clk *input;
+ int ret;
+
+ if (!dev || !ctrl || !out || !outf)
+ return -EINVAL;
+
+ input = of_clk_get(np, 0);
+ if (IS_ERR(input))
+ return dev_err_probe(dev, PTR_ERR(input),
+ "failed to get PLL reference clock\n");
+ parent.hw = __clk_get_hw(input);
+ ret = devm_add_action_or_reset(dev, sl261x_pll_put_clk, input);
+ if (ret)
+ return ret;
+
+ pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return -ENOMEM;
+ pll->ctrl = ctrl;
+
+ init.name = out;
+ init.ops = &sl261x_pllout_ops;
+ init.parent_data = &parent;
+ init.num_parents = 1;
+ init.flags = CLK_GET_RATE_NOCACHE;
+ pll->pllout.init = &init;
+
+ ret = devm_clk_hw_register(dev, &pll->pllout);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register pllout\n");
+
+ init.name = outf;
+ init.ops = &sl261x_plloutf_ops;
+ pll->plloutf.init = &init;
+
+ ret = devm_clk_hw_register(dev, &pll->plloutf);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register plloutf\n");
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(sl261x_pll_register);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Synaptics SL261x PLL clock driver");
diff --git a/drivers/clk/berlin/sl261x-pll.h b/drivers/clk/berlin/sl261x-pll.h
new file mode 100644
index 000000000000..70788661ff60
--- /dev/null
+++ b/drivers/clk/berlin/sl261x-pll.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SL261X_PLL_H
+#define __SL261X_PLL_H
+
+#include <linux/io.h>
+
+struct clk_hw_onecell_data;
+struct device;
+struct device_node;
+
+int sl261x_pll_register(struct device *dev, void __iomem *ctrl,
+ const char *out, const char *outf);
+
+#endif /* __SL261X_PLL_H */
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 17/20] dt-bindings: mfd: Add Synaptics SL261x global block binding
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (15 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 16/20] clk: berlin: add Synaptics SL261X SoC clocks and plls Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 19:55 ` Conor Dooley
2026-09-29 6:14 ` [PATCH 18/20] regulator: dt-bindings: sy8827n: support standard properties Jisheng Zhang
` (3 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Document the AVIO global, CPU wrapper, chip control, and MCU global
register blocks on SL261x SoCs. Each block exposes its clock and, where
applicable, pinctrl and reset functions through child nodes.
Document the chip control syscon phandle used by the CPU clock
controller.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../bindings/mfd/syna,sl261x-gbl.yaml | 208 ++++++++++++++++++
1 file changed, 208 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml
diff --git a/Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml b/Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml
new file mode 100644
index 000000000000..3e5842169c4a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/syna,sl261x-gbl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synaptics SL261x global and control register blocks
+
+maintainers:
+ - Jisheng Zhang <jszhang@kernel.org>
+
+description: |
+ The SL261x global and control register blocks contain clock, reset, and
+ pin control registers. Each functional child uses its parent's register
+ range. The CPU clock controller also refers to the chip control syscon.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: syna,sl261x-avio-gbl
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: syna,sl261x-cpu-wrp
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: syna,sl261x-chip-control
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: syna,sl261x-mcu-gbl
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ clock:
+ type: object
+ additionalProperties: true
+
+ pin-controller:
+ type: object
+ additionalProperties: true
+
+ reset:
+ type: object
+ additionalProperties: true
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: syna,sl261x-avio-gbl
+ then:
+ required:
+ - clock
+ properties:
+ clock:
+ properties:
+ compatible:
+ const: syna,sl261x-aio-clk
+ pin-controller: false
+ reset: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: syna,sl261x-cpu-wrp
+ then:
+ required:
+ - clock
+ properties:
+ clock:
+ properties:
+ compatible:
+ const: syna,sl261x-cpu-clk
+ pin-controller: false
+ reset: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: syna,sl261x-chip-control
+ then:
+ required:
+ - clock
+ - pin-controller
+ - reset
+ properties:
+ clock:
+ properties:
+ compatible:
+ const: syna,sl261x-soc-clk
+ pin-controller:
+ properties:
+ compatible:
+ const: syna,sl261x-soc-pinctrl
+ reset:
+ properties:
+ compatible:
+ const: syna,sl261x-soc-reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: syna,sl261x-mcu-gbl
+ then:
+ required:
+ - clock
+ - pin-controller
+ - reset
+ properties:
+ clock:
+ properties:
+ compatible:
+ const: syna,sl261x-system-clk
+ pin-controller:
+ properties:
+ compatible:
+ const: syna,sl261x-system-pinctrl
+ reset:
+ properties:
+ compatible:
+ const: syna,sl261x-system-reset
+
+additionalProperties: false
+
+examples:
+ - |
+ osc: clock-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ avio_gbl: avio-gbl@f7490000 {
+ compatible = "syna,sl261x-avio-gbl", "syscon", "simple-mfd";
+ reg = <0xf7490000 0x4000>;
+
+ aioclk: clock {
+ compatible = "syna,sl261x-aio-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+ };
+
+ chip: chip-control@f7e10000 {
+ compatible = "syna,sl261x-chip-control", "syscon", "simple-mfd";
+ reg = <0xf7e10000 0x10000>;
+
+ clk: clock {
+ compatible = "syna,sl261x-soc-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+
+ pinctrl: pin-controller {
+ compatible = "syna,sl261x-soc-pinctrl";
+ };
+
+ rst: reset {
+ compatible = "syna,sl261x-soc-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ cpu_wrp: cpu-wrp@f7e30000 {
+ compatible = "syna,sl261x-cpu-wrp", "syscon", "simple-mfd";
+ reg = <0xf7e30000 0x4000>;
+
+ cpuclk: clock {
+ compatible = "syna,sl261x-cpu-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ syna,gbl-syscon = <&chip>;
+ };
+ };
+
+ mcu_gbl: mcu-gbl@e5025000 {
+ compatible = "syna,sl261x-mcu-gbl", "syscon", "simple-mfd";
+ reg = <0xe5025000 0x1000>;
+
+ sm_clk: clock {
+ compatible = "syna,sl261x-system-clk";
+ #clock-cells = <1>;
+ };
+
+ sm_pinctrl: pin-controller {
+ compatible = "syna,sl261x-system-pinctrl";
+ };
+
+ sm_rst: reset {
+ compatible = "syna,sl261x-system-reset";
+ #reset-cells = <1>;
+ };
+ };
+...
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 17/20] dt-bindings: mfd: Add Synaptics SL261x global block binding
2026-09-29 6:14 ` [PATCH 17/20] dt-bindings: mfd: Add Synaptics SL261x global block binding Jisheng Zhang
@ 2026-09-29 19:55 ` Conor Dooley
0 siblings, 0 replies; 31+ messages in thread
From: Conor Dooley @ 2026-09-29 19:55 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 7181 bytes --]
On Tue, Sep 29, 2026 at 02:14:14PM +0800, Jisheng Zhang wrote:
> Document the AVIO global, CPU wrapper, chip control, and MCU global
> register blocks on SL261x SoCs. Each block exposes its clock and, where
> applicable, pinctrl and reset functions through child nodes.
>
> Document the chip control syscon phandle used by the CPU clock
> controller.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> .../bindings/mfd/syna,sl261x-gbl.yaml | 208 ++++++++++++++++++
> 1 file changed, 208 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml b/Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml
Filename should match a compatible.
> new file mode 100644
> index 000000000000..3e5842169c4a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml
> @@ -0,0 +1,208 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/syna,sl261x-gbl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synaptics SL261x global and control register blocks
> +
> +maintainers:
> + - Jisheng Zhang <jszhang@kernel.org>
> +
> +description: |
> + The SL261x global and control register blocks contain clock, reset, and
> + pin control registers. Each functional child uses its parent's register
> + range. The CPU clock controller also refers to the chip control syscon.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: syna,sl261x-avio-gbl
> + - const: syscon
> + - const: simple-mfd
> + - items:
> + - const: syna,sl261x-cpu-wrp
> + - const: syscon
> + - const: simple-mfd
> + - items:
> + - const: syna,sl261x-chip-control
> + - const: syscon
> + - const: simple-mfd
> + - items:
> + - const: syna,sl261x-mcu-gbl
> + - const: syscon
> + - const: simple-mfd
This can be simplified significantly by using an enum for the variable
part.
> +
> + reg:
> + maxItems: 1
> +
> + clock:
> + type: object
> + additionalProperties: true
> +
> + pin-controller:
> + type: object
> + additionalProperties: true
> +
> + reset:
> + type: object
> + additionalProperties: true
> +
> +required:
> + - compatible
> + - reg
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: syna,sl261x-avio-gbl
> + then:
> + required:
> + - clock
> + properties:
> + clock:
> + properties:
> + compatible:
> + const: syna,sl261x-aio-clk
> + pin-controller: false
> + reset: false
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: syna,sl261x-cpu-wrp
> + then:
> + required:
> + - clock
> + properties:
> + clock:
> + properties:
> + compatible:
> + const: syna,sl261x-cpu-clk
> + pin-controller: false
> + reset: false
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: syna,sl261x-chip-control
> + then:
> + required:
> + - clock
> + - pin-controller
> + - reset
> + properties:
> + clock:
> + properties:
> + compatible:
> + const: syna,sl261x-soc-clk
> + pin-controller:
> + properties:
> + compatible:
> + const: syna,sl261x-soc-pinctrl
> + reset:
> + properties:
> + compatible:
> + const: syna,sl261x-soc-reset
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: syna,sl261x-mcu-gbl
> + then:
> + required:
> + - clock
> + - pin-controller
> + - reset
> + properties:
> + clock:
> + properties:
> + compatible:
> + const: syna,sl261x-system-clk
> + pin-controller:
> + properties:
> + compatible:
> + const: syna,sl261x-system-pinctrl
> + reset:
> + properties:
> + compatible:
> + const: syna,sl261x-system-reset
Most of this can just disappear because most of these subnodes don't need to
exist. In fact, maybe all of them can be removed, leaving you just with
the syscon nodes themselves containing the relevant properties for
resets/clocks/pinctrl.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + osc: clock-osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
Nodes like this will get simulated by the tooling, they're not needed
here.
> +
> + avio_gbl: avio-gbl@f7490000 {
> + compatible = "syna,sl261x-avio-gbl", "syscon", "simple-mfd";
> + reg = <0xf7490000 0x4000>;
> +
> + aioclk: clock {
> + compatible = "syna,sl261x-aio-clk";
> + #clock-cells = <1>;
> + clocks = <&osc>;
> + };
> + };
> +
> + chip: chip-control@f7e10000 {
> + compatible = "syna,sl261x-chip-control", "syscon", "simple-mfd";
> + reg = <0xf7e10000 0x10000>;
> +
> + clk: clock {
> + compatible = "syna,sl261x-soc-clk";
> + #clock-cells = <1>;
> + clocks = <&osc>;
> + };
> +
> + pinctrl: pin-controller {
> + compatible = "syna,sl261x-soc-pinctrl";
> + };
> +
> + rst: reset {
> + compatible = "syna,sl261x-soc-reset";
> + #reset-cells = <1>;
> + };
> + };
> +
> + cpu_wrp: cpu-wrp@f7e30000 {
Please don't make up new node names for your device, use something
established like "system-controller" or "syscon" please.
pw-bot: changes-requested
Thanks,
Conor.
> + compatible = "syna,sl261x-cpu-wrp", "syscon", "simple-mfd";
> + reg = <0xf7e30000 0x4000>;
> +
> + cpuclk: clock {
> + compatible = "syna,sl261x-cpu-clk";
> + #clock-cells = <1>;
> + clocks = <&osc>;
> + syna,gbl-syscon = <&chip>;
> + };
> + };
> +
> + mcu_gbl: mcu-gbl@e5025000 {
> + compatible = "syna,sl261x-mcu-gbl", "syscon", "simple-mfd";
> + reg = <0xe5025000 0x1000>;
> +
> + sm_clk: clock {
> + compatible = "syna,sl261x-system-clk";
> + #clock-cells = <1>;
> + };
> +
> + sm_pinctrl: pin-controller {
> + compatible = "syna,sl261x-system-pinctrl";
> + };
> +
> + sm_rst: reset {
> + compatible = "syna,sl261x-system-reset";
> + #reset-cells = <1>;
> + };
> + };
> +...
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 18/20] regulator: dt-bindings: sy8827n: support standard properties
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (16 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 17/20] dt-bindings: mfd: Add Synaptics SL261x global block binding Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 19:40 ` Conor Dooley
2026-09-29 6:14 ` [PATCH 19/20] dt-bindings: arm: berlin: Add Synaptics SL261X SoC and RDK board Jisheng Zhang
` (2 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Support standard properties regulator.yaml, such as
regulator-active-discharge', 'regulator-always-on',
'regulator-boot-on', 'regulator-max-microvolt',
'regulator-min-microvolt', 'regulator-name' and on.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../devicetree/bindings/regulator/silergy,sy8827n.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/regulator/silergy,sy8827n.yaml b/Documentation/devicetree/bindings/regulator/silergy,sy8827n.yaml
index b222adabc7b4..0baf93ca67ca 100644
--- a/Documentation/devicetree/bindings/regulator/silergy,sy8827n.yaml
+++ b/Documentation/devicetree/bindings/regulator/silergy,sy8827n.yaml
@@ -31,7 +31,10 @@ required:
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: regulator.yaml#
+
+unevaluatedProperties: false
examples:
- |
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 18/20] regulator: dt-bindings: sy8827n: support standard properties
2026-09-29 6:14 ` [PATCH 18/20] regulator: dt-bindings: sy8827n: support standard properties Jisheng Zhang
@ 2026-09-29 19:40 ` Conor Dooley
0 siblings, 0 replies; 31+ messages in thread
From: Conor Dooley @ 2026-09-29 19:40 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 19/20] dt-bindings: arm: berlin: Add Synaptics SL261X SoC and RDK board
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (17 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 18/20] regulator: dt-bindings: sy8827n: support standard properties Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 6:14 ` [PATCH 20/20] arm64: dts: synaptics: " Jisheng Zhang
2026-09-29 19:38 ` [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Conor Dooley
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add devicetree binding for the Synaptics SL261X SoCs and corresponding
RDK boards.
The SL261X include five pin-to-pin compatible SoCs: SL2611, SL2613,
SL2615, SL2617, and SL2619.
The corresponding RDK boards are based on the these SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
.../bindings/arm/marvell,berlin.yaml | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.yaml b/Documentation/devicetree/bindings/arm/marvell,berlin.yaml
index 4e8442980dcb..30d94059e2f2 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.yaml
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.yaml
@@ -41,5 +41,25 @@ properties:
- marvell,berlin4ct-stb
- const: marvell,berlin4ct
- const: marvell,berlin
+ - items:
+ - enum:
+ - syna,sl2611-rdk
+ - const: syna,sl2611
+ - items:
+ - enum:
+ - syna,sl2613-rdk
+ - const: syna,sl2613
+ - items:
+ - enum:
+ - syna,sl2615-rdk
+ - const: syna,sl2615
+ - items:
+ - enum:
+ - syna,sl2617-rdk
+ - const: syna,sl2617
+ - items:
+ - enum:
+ - syna,sl2619-rdk
+ - const: syna,sl2619
additionalProperties: true
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 20/20] arm64: dts: synaptics: Add Synaptics SL261X SoC and RDK board
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (18 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 19/20] dt-bindings: arm: berlin: Add Synaptics SL261X SoC and RDK board Jisheng Zhang
@ 2026-09-29 6:14 ` Jisheng Zhang
2026-09-29 19:38 ` [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Conor Dooley
20 siblings, 0 replies; 31+ messages in thread
From: Jisheng Zhang @ 2026-09-29 6:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth
Cc: devicetree, linux-kernel, linux-clk, linux-i2c, linux-i3c, mfd,
linux-gpio, linux-serial, linux-spi, linux-arm-kernel
Add dts(i) files for the Synaptics SL261X SoCs and corresponding
RDK boards.
The SL261X include five pin-to-pin compatible SoCs: SL2611, SL2613,
SL2615, SL2617, and SL2619.
The corresponding RDK boards are based on the these SoCs.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/arm64/boot/dts/synaptics/Makefile | 5 +
arch/arm64/boot/dts/synaptics/sl2611-rdk.dts | 16 +
arch/arm64/boot/dts/synaptics/sl2611.dtsi | 490 ++++++++++++++++++
arch/arm64/boot/dts/synaptics/sl2613-rdk.dts | 16 +
arch/arm64/boot/dts/synaptics/sl2613.dtsi | 12 +
arch/arm64/boot/dts/synaptics/sl2615-rdk.dts | 16 +
arch/arm64/boot/dts/synaptics/sl2615.dtsi | 46 ++
arch/arm64/boot/dts/synaptics/sl2617-rdk.dts | 16 +
arch/arm64/boot/dts/synaptics/sl2617.dtsi | 46 ++
arch/arm64/boot/dts/synaptics/sl2619-rdk.dts | 16 +
arch/arm64/boot/dts/synaptics/sl2619.dtsi | 44 ++
.../boot/dts/synaptics/sl261x-rdk-common.dtsi | 135 +++++
12 files changed, 858 insertions(+)
create mode 100644 arch/arm64/boot/dts/synaptics/sl2611-rdk.dts
create mode 100644 arch/arm64/boot/dts/synaptics/sl2611.dtsi
create mode 100644 arch/arm64/boot/dts/synaptics/sl2613-rdk.dts
create mode 100644 arch/arm64/boot/dts/synaptics/sl2613.dtsi
create mode 100644 arch/arm64/boot/dts/synaptics/sl2615-rdk.dts
create mode 100644 arch/arm64/boot/dts/synaptics/sl2615.dtsi
create mode 100644 arch/arm64/boot/dts/synaptics/sl2617-rdk.dts
create mode 100644 arch/arm64/boot/dts/synaptics/sl2617.dtsi
create mode 100644 arch/arm64/boot/dts/synaptics/sl2619-rdk.dts
create mode 100644 arch/arm64/boot/dts/synaptics/sl2619.dtsi
create mode 100644 arch/arm64/boot/dts/synaptics/sl261x-rdk-common.dtsi
diff --git a/arch/arm64/boot/dts/synaptics/Makefile b/arch/arm64/boot/dts/synaptics/Makefile
index de71ddda6835..810d0d08c2de 100644
--- a/arch/arm64/boot/dts/synaptics/Makefile
+++ b/arch/arm64/boot/dts/synaptics/Makefile
@@ -2,3 +2,8 @@
# Berlin SoC Family
dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += sl2611-rdk.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += sl2613-rdk.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += sl2615-rdk.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += sl2617-rdk.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += sl2619-rdk.dtb
diff --git a/arch/arm64/boot/dts/synaptics/sl2611-rdk.dts b/arch/arm64/boot/dts/synaptics/sl2611-rdk.dts
new file mode 100644
index 000000000000..585872307834
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2611-rdk.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "sl2611.dtsi"
+#include "sl261x-rdk-common.dtsi"
+
+/ {
+ model = "Synaptics SL2611 RDK";
+ compatible = "syna,sl2611-rdk", "syna,sl2611";
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2611.dtsi b/arch/arm64/boot/dts/synaptics/sl2611.dtsi
new file mode 100644
index 000000000000..1d640ffe4c4b
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2611.dtsi
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/clock/syna,sl261x.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/syna,sl261x-reset.h>
+
+/ {
+ compatible = "syna,sl2611";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3>;
+ };
+ };
+
+ L3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <75>;
+ exit-latency-us = <155>;
+ min-residency-us = <50000>;
+ };
+ };
+ };
+
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ sm-bus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges = <0xa0000000 0x00000000 0x10000000>;
+
+ sm_chip: chip-control@e5025000 {
+ compatible = "syna,sl261x-mcu-gbl", "syscon", "simple-mfd";
+ reg = <0xe5025000 0x1000>;
+
+ sm_clk: clock {
+ compatible = "syna,sl261x-system-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+
+ sm_pinctrl: pin-controller {
+ compatible = "syna,sl261x-system-pinctrl";
+ };
+
+ sm_rst: reset {
+ compatible = "syna,sl261x-system-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ sm_uart0: serial@e5030000 {
+ compatible = "syna,sl261x-uart", "snps,dw-apb-uart";
+ reg = <0xe5030000 0x100>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sm_clk CLK_SER_UART0>, <&sm_clk CLK_CFG_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sm_uart1: serial@e5031000 {
+ compatible = "syna,sl261x-uart", "snps,dw-apb-uart";
+ reg = <0xe5031000 0x100>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sm_clk CLK_SER_UART1>, <&sm_clk CLK_CFG_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sm_uart2: serial@e5032000 {
+ compatible = "syna,sl261x-uart", "snps,dw-apb-uart";
+ reg = <0xe5032000 0x100>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sm_clk CLK_SER_UART2>, <&sm_clk CLK_CFG_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sm_uart3: serial@e5033000 {
+ compatible = "syna,sl261x-uart", "snps,dw-apb-uart";
+ reg = <0xe5033000 0x100>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sm_clk CLK_SER_UART3>, <&sm_clk CLK_CFG_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sm_spi1: spi@e5034000 {
+ compatible = "syna,sl261x-spi", "snps,dw-apb-ssi";
+ reg = <0xe5034000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ clocks = <&sm_clk CLK_SER_SPIM>, <&sm_clk CLK_CFG_SPIM>;
+ clock-names = "ssi_clk", "pclk";
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sm_i2c0: i2c@e5035000 {
+ compatible = "syna,sl261x-i2c", "snps,designware-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xe5035000 0x100>;
+ clocks = <&sm_clk CLK_SER_I2CM0>, <&sm_clk CLK_CFG_I2CM0>;
+ clock-names = "ref", "pclk";
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sm_i2c1: i2c@e5036000 {
+ compatible = "syna,sl261x-i2c", "snps,designware-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xe5036000 0x100>;
+ clocks = <&sm_clk CLK_SER_I2CM1>, <&sm_clk CLK_CFG_I2CM1>;
+ clock-names = "ref", "pclk";
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sm_i3c0: i3c@e5037000 {
+ compatible = "syna,sl261x-i3c", "snps,dw-i3c-master-1.00a";
+ #address-cells = <3>;
+ #size-cells = <0>;
+ reg = <0xe5037000 0x1000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&sm_rst RST_SM_I3CSRST>, <&sm_rst RST_SM_I3CPRST>;
+ clocks = <&sm_clk CLK_SER_I3C>, <&sm_clk CLK_CFG_I3C>;
+ clock-names = "core", "apb";
+ status = "disabled";
+ };
+
+ sm_gpio0: gpio@e5038000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xe5038000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sm_clk CLK_CFG_GPIO>, <&sm_clk CLK_DEB_GPIO>;
+ clock-names = "bus", "db";
+
+ portc: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ reg = <0>;
+ };
+ };
+
+ sm_gpio1: gpio@e5039000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xe5039000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sm_clk CLK_CFG_GPIO>, <&sm_clk CLK_DEB_GPIO>;
+ clock-names = "bus", "db";
+
+ portd: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ reg = <0>;
+ };
+ };
+
+ sm_gpio2: gpio@e503a000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xe503a000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sm_clk CLK_CFG_GPIO>, <&sm_clk CLK_DEB_GPIO>;
+ clock-names = "bus", "db";
+
+ porte: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ reg = <0>;
+ };
+ };
+
+ sm_gpio3: gpio@e503b000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xe503b000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sm_clk CLK_CFG_GPIO>, <&sm_clk CLK_DEB_GPIO>;
+ clock-names = "bus", "db";
+
+ portf: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ reg = <0>;
+ };
+ };
+ };
+
+ aviogbl: chip-control@f7490000 {
+ compatible = "syna,sl261x-avio-gbl", "syscon", "simple-mfd";
+ reg = <0xf7490000 0x4000>;
+
+ aioclk: clock {
+ compatible = "syna,sl261x-aio-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+ };
+
+ chip: chip-control@f7e10000 {
+ compatible = "syna,sl261x-chip-control", "syscon", "simple-mfd";
+ reg = <0xf7e10000 0x10000>;
+
+ clk: clock {
+ compatible = "syna,sl261x-soc-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+
+ pinctrl: pin-controller {
+ compatible = "syna,sl261x-soc-pinctrl";
+ };
+
+ rst: reset {
+ compatible = "syna,sl261x-soc-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ cpu_wrap: cpu-wrap@f7e30000{
+ compatible = "syna,sl261x-cpu-wrp", "syscon", "simple-mfd";
+ reg = <0xf7e30000 0x4000>;
+
+ cpuclk: clock {
+ compatible = "syna,sl261x-cpu-clk";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ syna,gbl-syscon = <&chip>;
+ };
+ };
+
+ gic: interrupt-controller@f7e59000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xf7e59000 0x1000>,
+ <0xf7e5a000 0x2000>,
+ <0xf7e5c000 0x2000>,
+ <0xf7e5e000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc_uart0: serial@f7f00000 {
+ compatible = "syna,sl261x-uart", "snps,dw-apb-uart";
+ reg = <0xf7f00000 0x100>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_APBUART0>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ soc_uart1: serial@f7f01000 {
+ compatible = "syna,sl261x-uart", "snps,dw-apb-uart";
+ reg = <0xf7f01000 0x100>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_APBUART1>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ soc_uart2: serial@f7f02000 {
+ compatible = "syna,sl261x-uart", "snps,dw-apb-uart";
+ reg = <0xf7f02000 0x100>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_APBUART2>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ soc_uart3: serial@f7f03000 {
+ compatible = "syna,sl261x-uart", "snps,dw-apb-uart";
+ reg = <0xf7f03000 0x100>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk CLK_APBUART3>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ soc_spi0: spi@f7f04000 {
+ compatible = "syna,sl261x-spi", "snps,dw-apb-ssi";
+ reg = <0xf7f04000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ clocks = <&clk CLK_APBSPI0>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ soc_i2c0: i2c@f7f05000 {
+ compatible = "syna,sl261x-i2c", "snps,designware-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf7f05000 0x100>;
+ clocks = <&clk CLK_APBI2C0>;
+ i2c-sda-hold-time-ns = <449>;
+ i2c-sda-falling-time-ns = <425>;
+ i2c-scl-falling-time-ns = <205>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ soc_i2c1: i2c@f7f06000 {
+ compatible = "syna,sl261x-i2c", "snps,designware-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf7f06000 0x100>;
+ clocks = <&clk CLK_APBI2C1>;
+ i2c-sda-hold-time-ns = <449>;
+ i2c-sda-falling-time-ns = <425>;
+ i2c-scl-falling-time-ns = <205>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ soc_gpio0: gpio@f7f07000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xf7f07000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_APBGPIO>;
+ clock-names = "bus";
+
+ porta: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ soc_spi1: spi@f7f0b000 {
+ compatible = "syna,sl261x-spi", "snps,dw-apb-ssi";
+ reg = <0xf7f0b000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ clocks = <&clk CLK_APBSPI1>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ soc_spi2: spi@f7f0c000 {
+ compatible = "syna,sl261x-spi", "snps,dw-apb-ssi";
+ reg = <0xf7f0c000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ clocks = <&clk CLK_APBSPI2>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ soc_spi3: spi@f7f0d000 {
+ compatible = "syna,sl261x-spi", "snps,dw-apb-ssi";
+ reg = <0xf7f0d000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ clocks = <&clk CLK_APBSPI3>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ soc_gpio1: gpio@f7f0e000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xf7f0e000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_APBGPIO>;
+ clock-names = "bus";
+
+ portb: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2613-rdk.dts b/arch/arm64/boot/dts/synaptics/sl2613-rdk.dts
new file mode 100644
index 000000000000..de75c9fab6a2
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2613-rdk.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "sl2613.dtsi"
+#include "sl261x-rdk-common.dtsi"
+
+/ {
+ model = "Synaptics SL2613 RDK";
+ compatible = "syna,sl2613-rdk", "syna,sl2613";
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2613.dtsi b/arch/arm64/boot/dts/synaptics/sl2613.dtsi
new file mode 100644
index 000000000000..379809901677
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2613.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "sl2611.dtsi"
+
+/ {
+ compatible = "syna,sl2613";
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2615-rdk.dts b/arch/arm64/boot/dts/synaptics/sl2615-rdk.dts
new file mode 100644
index 000000000000..ae03638a3a53
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2615-rdk.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "sl2615.dtsi"
+#include "sl261x-rdk-common.dtsi"
+
+/ {
+ model = "Synaptics SL2615 RDK";
+ compatible = "syna,sl2615-rdk", "syna,sl2615";
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2615.dtsi b/arch/arm64/boot/dts/synaptics/sl2615.dtsi
new file mode 100644
index 000000000000..11b1fe316aa6
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2615.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "sl2613.dtsi"
+
+/ {
+ compatible = "syna,sl2615";
+
+ cpus {
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_1>;
+
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3>;
+ };
+ };
+ };
+
+ pmu {
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2617-rdk.dts b/arch/arm64/boot/dts/synaptics/sl2617-rdk.dts
new file mode 100644
index 000000000000..ba4ea21ac505
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2617-rdk.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "sl2617.dtsi"
+#include "sl261x-rdk-common.dtsi"
+
+/ {
+ model = "Synaptics SL2617 RDK";
+ compatible = "syna,sl2617-rdk", "syna,sl2617";
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2617.dtsi b/arch/arm64/boot/dts/synaptics/sl2617.dtsi
new file mode 100644
index 000000000000..a0de686d1fae
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2617.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "sl2613.dtsi"
+
+/ {
+ compatible = "syna,sl2617";
+
+ cpus {
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_1>;
+
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3>;
+ };
+ };
+ };
+
+ pmu {
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2619-rdk.dts b/arch/arm64/boot/dts/synaptics/sl2619-rdk.dts
new file mode 100644
index 000000000000..58901ac2a050
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2619-rdk.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "sl2619.dtsi"
+#include "sl261x-rdk-common.dtsi"
+
+/ {
+ model = "Synaptics SL2619 RDK";
+ compatible = "syna,sl2619-rdk", "syna,sl2619";
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl2619.dtsi b/arch/arm64/boot/dts/synaptics/sl2619.dtsi
new file mode 100644
index 000000000000..96bd58bbed3e
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl2619.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "sl2613.dtsi"
+
+/ {
+ cpus {
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_1>;
+
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3>;
+ };
+ };
+ };
+
+ pmu {
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/synaptics/sl261x-rdk-common.dtsi b/arch/arm64/boot/dts/synaptics/sl261x-rdk-common.dtsi
new file mode 100644
index 000000000000..78a9b28fdf99
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/sl261x-rdk-common.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ aliases {
+ serial0 = &sm_uart0;
+ serial1 = &sm_uart1;
+ serial2 = &sm_uart2;
+ serial3 = &sm_uart3;
+ serial4 = &soc_uart0;
+ serial5 = &soc_uart1;
+ serial6 = &soc_uart2;
+ serial7 = &soc_uart3;
+ i2c0 = &sm_i2c0;
+ i2c1 = &sm_i2c1;
+ i2c2 = &soc_i2c0;
+ i2c3 = &soc_i2c1;
+ spi1 = &sm_spi1;
+ spi2 = &soc_spi0;
+ spi3 = &soc_spi1;
+ spi4 = &soc_spi2;
+ spi5 = &soc_spi3;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vcore>;
+ };
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&osc {
+ clock-frequency = <25000000>;
+};
+
+&pinctrl {
+ soc_i2c0_pmux: soc_i2c0-pmux {
+ groups = "GPIO23", "GPIO24";
+ function = "tw2";
+ drive-strength = <7>;
+ };
+};
+
+&sm_pinctrl {
+ sm_i2c0_pmux: i2c0-pmux {
+ groups = "SM_GPIO12", "SM_GPIO13";
+ function = "tw0";
+ drive-strength = <7>;
+ };
+
+ sm_i2c1_pmux: i2c1-pmux {
+ groups = "SM_GPIO3", "SM_GPIO4";
+ function = "tw1";
+ drive-strength = <7>;
+ };
+
+ vcore_gpio_pmux: vcore-gpio-pmux {
+ groups = "SM_GPIO5";
+ function = "gpio";
+ };
+};
+
+&sm_uart0 {
+ status = "okay";
+};
+
+&sm_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sm_i2c0_pmux>;
+ clock-frequency = <100000>;
+
+ expander0: gpio@43 {
+ compatible = "fcs,fxl6408";
+ reg = <0x43>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ expander1: gpio@44 {
+ compatible = "fcs,fxl6408";
+ reg = <0x44>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&sm_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sm_i2c1_pmux>;
+ clock-frequency = <100000>;
+
+ vcore: regulator@60 {
+ compatible = "silergy,sy8827n";
+ reg = <0x60>;
+ regulator-name = "vcore";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <987500>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-active-discharge = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcore_gpio_pmux>;
+ enable-gpios = <&portc 5 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&soc_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&soc_i2c0_pmux>;
+ clock-frequency = <100000>;
+};
+
+&sm_uart1 {
+ status = "okay";
+};
--
2.53.0
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards
2026-09-29 6:13 [PATCH 00/20] arm64: add Synaptics SL261X SoCs and RDK boards Jisheng Zhang
` (19 preceding siblings ...)
2026-09-29 6:14 ` [PATCH 20/20] arm64: dts: synaptics: " Jisheng Zhang
@ 2026-09-29 19:38 ` Conor Dooley
20 siblings, 0 replies; 31+ messages in thread
From: Conor Dooley @ 2026-09-29 19:38 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Stephen Boyd,
Brian Masney, Jerome Brunet, Andi Shyti, Alexandre Belloni,
Frank Li, Lee Jones, Linus Walleij, Liam Girdwood, Mark Brown,
Philipp Zabel, Greg Kroah-Hartman, Jiri Slaby,
Sebastian Hesselbarth, devicetree, linux-kernel, linux-clk,
linux-i2c, linux-i3c, mfd, linux-gpio, linux-serial, linux-spi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 6774 bytes --]
On Tue, Sep 29, 2026 at 02:13:57PM +0800, Jisheng Zhang wrote:
> Add initial support for the Synaptics SL261X SoCs and corresponding
> RDK boards.
>
> The SL261X SoCs include five pin-to-pin compatible SoCs: SL2611, SL2613,
> SL2615, SL2617, and SL2619.
>
> Only reset, pinctrl, clk/pll, uart, gpio, i2c, spi, i3c are included in
> this series. The support for Ethernet, USB, SDHCI, CAN, DMAC, XSPI will
> be submitted after this series is merged.
This series is filled with wildcard compatibles, which we don't permit
typically. The only case for SoCs that I've seen them accepted is when
the devices covered are actually just different binnings of the same
device. I took a look at the docs for this device, but it wasn't clear
to me if these are actually binnings or if there are different
integrations here. If they're binnings, I'd rather you used 0 as the
final digit, rather than x, since that matches the synaptics
documentation for the family. If they're not binnings, there's no
guarantee that they share the same errata etc, and must have different
compatibles.
Cheers,
Conor.
>
>
> Jisheng Zhang (20):
> dt-bindings: serial: snps-dw-apb-uart: Add Synaptics sl261x uart
> dt-bindings: i2c: dw: Add Synaptics sl261x i2c
> spi: dt-bindings: snps,dw-apb-ssi: Add Synaptics sl261x spi
> dt-bindings: i3c: dw: support up to two reset lines
> i3c: dw: switch to array-based exclusive reset control
> dt-bindings: i3c: Add Synaptics sl261x i3c
> arm64: kconfig: let ARCH_BERLIN cover Synaptics arm64 SoCs
> dt-bindings: reset: add Synaptics SL261X SoCs
> reset: add Synaptics SL261x reset support
> pinctrl: berlin: use u16 instead of u8 for the offset
> pinctrl: berlin: enable module build support
> pinctrl: berlin: add optional pinconf support
> dt-bindings: pinctrl: berlin: Support Synaptics SL261X SoCs
> pinctrl: berlin: support Synaptics SL261X SoCs
> dt-bindings: clock: add Synaptics SL261X clock
> clk: berlin: add Synaptics SL261X SoC clocks and plls
> dt-bindings: mfd: Add Synaptics SL261x global block binding
> regulator: dt-bindings: sy8827n: support standard properties
> dt-bindings: arm: berlin: Add Synaptics SL261X SoC and RDK board
> arm64: dts: synaptics: Add Synaptics SL261X SoC and RDK board
>
> .../bindings/arm/marvell,berlin.yaml | 20 +
> .../bindings/clock/syna,sl261x-clk.yaml | 92 +++
> .../bindings/i2c/snps,designware-i2c.yaml | 1 +
> .../bindings/i3c/snps,dw-i3c-master.yaml | 6 +-
> .../bindings/mfd/syna,sl261x-gbl.yaml | 208 +++++
> .../pinctrl/marvell,berlin2-soc-pinctrl.yaml | 10 +-
> .../bindings/regulator/silergy,sy8827n.yaml | 5 +-
> .../bindings/reset/syna,sl261x-reset.yaml | 40 +
> .../bindings/serial/snps-dw-apb-uart.yaml | 12 +-
> .../bindings/spi/snps,dw-apb-ssi.yaml | 1 +
> arch/arm64/Kconfig.platforms | 4 +-
> arch/arm64/boot/dts/synaptics/Makefile | 5 +
> arch/arm64/boot/dts/synaptics/sl2611-rdk.dts | 16 +
> arch/arm64/boot/dts/synaptics/sl2611.dtsi | 490 ++++++++++++
> arch/arm64/boot/dts/synaptics/sl2613-rdk.dts | 16 +
> arch/arm64/boot/dts/synaptics/sl2613.dtsi | 12 +
> arch/arm64/boot/dts/synaptics/sl2615-rdk.dts | 16 +
> arch/arm64/boot/dts/synaptics/sl2615.dtsi | 46 ++
> arch/arm64/boot/dts/synaptics/sl2617-rdk.dts | 16 +
> arch/arm64/boot/dts/synaptics/sl2617.dtsi | 46 ++
> arch/arm64/boot/dts/synaptics/sl2619-rdk.dts | 16 +
> arch/arm64/boot/dts/synaptics/sl2619.dtsi | 44 ++
> .../boot/dts/synaptics/sl261x-rdk-common.dtsi | 135 ++++
> drivers/clk/Kconfig | 1 +
> drivers/clk/berlin/Kconfig | 25 +
> drivers/clk/berlin/Makefile | 4 +
> drivers/clk/berlin/sl-clk.c | 279 +++++++
> drivers/clk/berlin/sl-clk.h | 31 +
> drivers/clk/berlin/sl-sysmgr-clk.c | 250 ++++++
> drivers/clk/berlin/sl-sysmgr-clk.h | 44 ++
> drivers/clk/berlin/sl261x-clks.c | 385 +++++++++
> drivers/clk/berlin/sl261x-pll.c | 145 ++++
> drivers/clk/berlin/sl261x-pll.h | 14 +
> drivers/i3c/master/dw-i3c-master.c | 24 +-
> drivers/i3c/master/dw-i3c-master.h | 2 +-
> drivers/pinctrl/berlin/Kconfig | 7 +
> drivers/pinctrl/berlin/Makefile | 1 +
> drivers/pinctrl/berlin/berlin.c | 259 +++++-
> drivers/pinctrl/berlin/berlin.h | 17 +-
> drivers/pinctrl/berlin/pinctrl-sl261x.c | 745 ++++++++++++++++++
> drivers/reset/Kconfig | 6 +
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-sl261x.c | 224 ++++++
> include/dt-bindings/clock/syna,sl261x.h | 131 +++
> include/dt-bindings/reset/syna,sl261x-reset.h | 80 ++
> 45 files changed, 3899 insertions(+), 33 deletions(-)
> create mode 100755 Documentation/devicetree/bindings/clock/syna,sl261x-clk.yaml
> create mode 100644 Documentation/devicetree/bindings/mfd/syna,sl261x-gbl.yaml
> create mode 100644 Documentation/devicetree/bindings/reset/syna,sl261x-reset.yaml
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2611-rdk.dts
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2611.dtsi
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2613-rdk.dts
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2613.dtsi
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2615-rdk.dts
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2615.dtsi
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2617-rdk.dts
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2617.dtsi
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2619-rdk.dts
> create mode 100644 arch/arm64/boot/dts/synaptics/sl2619.dtsi
> create mode 100644 arch/arm64/boot/dts/synaptics/sl261x-rdk-common.dtsi
> create mode 100644 drivers/clk/berlin/Kconfig
> create mode 100644 drivers/clk/berlin/sl-clk.c
> create mode 100644 drivers/clk/berlin/sl-clk.h
> create mode 100644 drivers/clk/berlin/sl-sysmgr-clk.c
> create mode 100644 drivers/clk/berlin/sl-sysmgr-clk.h
> create mode 100644 drivers/clk/berlin/sl261x-clks.c
> create mode 100644 drivers/clk/berlin/sl261x-pll.c
> create mode 100644 drivers/clk/berlin/sl261x-pll.h
> create mode 100644 drivers/pinctrl/berlin/pinctrl-sl261x.c
> create mode 100644 drivers/reset/reset-sl261x.c
> create mode 100644 include/dt-bindings/clock/syna,sl261x.h
> create mode 100644 include/dt-bindings/reset/syna,sl261x-reset.h
>
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread