[PATCH 0/4] powerpc/topology: Introduce llc_override debugfs

[PATCH 0/4] powerpc/topology: Introduce llc_override debugfs

[Shrikanth Hegde]

There is a new feature in scheduler called as Cache Aware Scheduling [1].
It tries to keep related tasks within the same LLC domain while
keeping the system reasonably balanced.

Cache Aware Scheduling assumes that the scheduler LLC domain is large enough
to be a useful placement target. This is true on many systems where an LLC spans
several cores, but not on PowerPC systems where the scheduler-visible LLC is at
the SMT level. In that case, sd_llc_size is effectively the SMT width.

This becomes visible in the capacity check:
        return !fits_capacity((mm->sc_stat.nr_running_avg * cpu_smt_num_threads),
                              scale * per_cpu(sd_llc_size, cpu));

As a result, Cache aware scheduling may be enabled but has no room to operate.

Hence provide a debugfs option to set LLC at specific domain so that
one can try experiment their workload with cache aware scheduling.
This also provides ways to explore it on system with SMT=4 to see if
there are any opportunities to improve or uncover bugs if there is any.

Note it is a debug option and it is recommended to keep it disabled.
There is no performance guarantees across different values.

[1]: https://lore.kernel.org/all/cover.1778703694.git.tim.c.chen@linux.intel.com/

Tim, Chenyu, Peter,
Are there any selftest or patches which is used for
functional validation of cache aware scheduling?
per-LLC occupancy in /proc/{PID}/schedstat may not tell the full
story when there are multiple processes and multiple LLC's.

Atleast for functional verification, we might need one if there is
not one already. The reason being,
- At present, we may need a custom workload. hackbench/schbench are
  wakeup intensive and typically bail out even before load balance.
- stress-ng is per process. So doesn't get cache aware scheduling.
- A selftest could spwan specific number of threads till llc size etc
  and ensure packing happens till core_count(llc_size) by default.
  This could also be used for tunable verfifications.
- Provide an ability to observe how much of the workload was contained
  within the LLC due to cache aware scheduling or number of load
  balances stopped due to preferred llc.

These are some initial thoughts I had. If it sounds ok, I can try to add
a new selftest/kunit test. 

Shrikanth Hegde (4):
  powerpc/topology: Introduce llc_override debug knob
  powerpc/topology: Add docs for llc_override
  powerpc/topology: Update mc/pkg flags based on llc_override
  powerpc/topology: Rebuild sched domains on llc_override change

 Documentation/arch/powerpc/index.rst    |   1 +
 Documentation/arch/powerpc/topology.rst |  27 +++++
 arch/powerpc/kernel/smp.c               | 128 +++++++++++++++++++++++-
 3 files changed, 151 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/arch/powerpc/topology.rst

-- 
2.52.0

[PATCH 1/4] powerpc/topology: Introduce llc_override debug knob

[Shrikanth Hegde]

There is a new feature in scheduler called as Cache Aware Scheduling.
It tries to keep related tasks within the same LLC domain while
keeping the system reasonably balanced.

Cache Aware Scheduling assumes that the scheduler LLC domain is large
enough to be a useful placement target. This is true on many systems
where an LLC spans several cores, but not on PowerPC systems where the
scheduler-visible LLC is at the SMT level.
In that case, sd_llc_size is effectively the SMT width.

This becomes visible in the capacity check:

  !fits_capacity((mm->sc_stat.nr_running_avg * cpu_smt_num_threads),
                  scale * per_cpu(sd_llc_size, cpu));

As a result, it may be enabled but has no room to operate.
Hence provide a debugfs option one can set to try experiment their
workload with cache aware scheduling. This also provides ways to explore
it on system with SMT=4 to see if there are any opportunities
to improve or uncover bugs if there is any.

This does not change the hardware cache topology. It only changes the
sched-domain level at which SD_SHARE_LLC is set.

Initially start with,
- New debugs file called llc_override. It can be set/get on
  /sys/kernel/debug/powerpc/llc_override
- Adds parser logic for the debug knob.

There is no point in setting NUMA as the LLC domain. So give option
until pkg to experiment with.

Actual flag manipulations and rebuilding sched domains are introduced
in subsequent patches.

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
PS: Split is deliberate. If squashing all this into one patch helps,
    let me know.

 arch/powerpc/kernel/smp.c | 90 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 6a5a5469aaae..433757511adb 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -36,6 +36,7 @@
 #include <linux/pgtable.h>
 #include <linux/clockchips.h>
 #include <linux/kexec.h>
+#include <linux/debugfs.h>
 
 #include <asm/ptrace.h>
 #include <linux/atomic.h>
@@ -1826,3 +1827,92 @@ void __noreturn arch_cpu_idle_dead(void)
 }
 
 #endif
+
+enum llc_override_values {
+	LLC_OVERRIDE_DISABLED,
+	LLC_OVERRIDE_SMT,
+	LLC_OVERRIDE_MC,
+	LLC_OVERRIDE_PKG,
+};
+
+static int llc_override;
+static int llc_override_changed;
+static DEFINE_MUTEX(llc_override_mutex);
+
+static const char * const llc_override_str[] = {
+	[LLC_OVERRIDE_DISABLED]	= "0",
+	[LLC_OVERRIDE_SMT]	= "smt",
+	[LLC_OVERRIDE_MC]	= "mc",
+	[LLC_OVERRIDE_PKG]	= "pkg",
+};
+
+static ssize_t llc_override_get(struct file *file, char __user *ubuf,
+				size_t count, loff_t *ppos)
+{
+	int override;
+	char buf[8];
+	int len;
+
+	override = READ_ONCE(llc_override);
+	len = scnprintf(buf, sizeof(buf), "%s\n", llc_override_str[override]);
+	return simple_read_from_buffer(ubuf, count, ppos, buf, len);
+}
+
+static ssize_t llc_override_set(struct file *file, const char __user *ubuf,
+				size_t count, loff_t *ppos)
+{
+	char buf[8];
+	int override;
+
+	if (!count || count >= sizeof(buf))
+		return -EINVAL;
+
+	if (copy_from_user(buf, ubuf, count))
+		return -EFAULT;
+
+	buf[count] = '\0';
+	strim(buf);
+
+	if (!strcmp(buf, "0"))
+		override = LLC_OVERRIDE_DISABLED;
+	else if (!strcasecmp(buf, "smt"))
+		override = LLC_OVERRIDE_SMT;
+	else if (!strcasecmp(buf, "mc"))
+		override = LLC_OVERRIDE_MC;
+	else if (!strcasecmp(buf, "pkg"))
+		override = LLC_OVERRIDE_PKG;
+	else
+		return -EINVAL;
+
+	if (override == LLC_OVERRIDE_MC && !has_coregroup_support())
+		return -EINVAL;
+
+	mutex_lock(&llc_override_mutex);
+
+	if (override != READ_ONCE(llc_override)) {
+		WRITE_ONCE(llc_override, override);
+		WRITE_ONCE(llc_override_changed, 1);
+		pr_info("sched LLC override set to %s\n",
+			llc_override_str[override]);
+
+		/* Will be calling rebuild sched domain in later patches */
+	}
+
+	mutex_unlock(&llc_override_mutex);
+	return count;
+}
+
+static const struct file_operations llc_override_fops = {
+	.open		= simple_open,
+	.read		= llc_override_get,
+	.write		= llc_override_set,
+	.llseek		= default_llseek,
+};
+
+static __init int llc_override_debugfs_init(void)
+{
+	debugfs_create_file("llc_override", 0600, arch_debugfs_dir, NULL,
+			    &llc_override_fops);
+	return 0;
+}
+device_initcall(llc_override_debugfs_init);
-- 
2.52.0

[PATCH 2/4] powerpc/topology: Add docs for llc_override

[Shrikanth Hegde]

Provide documentation for the newly introduced debug knob
named as llc_override.

This may help one if they want to experiment with cache aware
scheduling.

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
 Documentation/arch/powerpc/index.rst    |  1 +
 Documentation/arch/powerpc/topology.rst | 27 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 Documentation/arch/powerpc/topology.rst

diff --git a/Documentation/arch/powerpc/index.rst b/Documentation/arch/powerpc/index.rst
index 40419bea8e10..0f4caf50a9e7 100644
--- a/Documentation/arch/powerpc/index.rst
+++ b/Documentation/arch/powerpc/index.rst
@@ -33,6 +33,7 @@ powerpc
     qe_firmware
     syscall64-abi
     transactional_memory
+    topology
     ultravisor
     vas-api
     vcpudispatch_stats
diff --git a/Documentation/arch/powerpc/topology.rst b/Documentation/arch/powerpc/topology.rst
new file mode 100644
index 000000000000..9ed3cf7ade69
--- /dev/null
+++ b/Documentation/arch/powerpc/topology.rst
@@ -0,0 +1,27 @@
+.. SPDX-License-Identifier: GPL-2.0
+.. _topology:
+
+
+llc_override
+==============
+
+Override the scheduler-visible LLC domain on PowerPC.
+
+Having LLC(last level cache) at MC/PKG helps to experiment with new
+scheduler feature called cache aware scheduling which expects LLC to have
+at least more than 1 core. Scheduler uses notion of LLC for wakeup and
+load balancing decisions.
+
+Accepted values are:
+
+  0    Disable the override and use the platform default.
+  smt  LLC will be at SMT domain.
+  mc   LLC will be at MC domain, including at SMT domains.
+  pkg  LLC will be at PKG domain, including at MC and SMT domains,
+
+Writing a new value rebuilds the scheduler domains. One can check the
+domain flags and look for SD_SHARE_LLC to confirm if it took effect.
+
+Note that this doesn't change HW cache topology. It is only a debug knob
+to experiment with scheduler related functionalities. So set it to sensible
+values. Also note that there is no performance guarantees across the values.
-- 
2.52.0

[PATCH 3/4] powerpc/topology: Update mc/pkg flags based on llc_override

[Shrikanth Hegde]

Update the flags passed for building the scheduler topology.

SD_SHARE_LLC is used to determine the highest domain where the LLC is.
Also when set at a particular domain, all the child domains are expected
to have it set as well.

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
 arch/powerpc/kernel/smp.c | 63 +++++++++++++++++++++++++--------------
 1 file changed, 40 insertions(+), 23 deletions(-)

diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 433757511adb..4b6512d25f73 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -141,6 +141,24 @@ volatile unsigned int cpu_callin_map[NR_CPUS];
 
 int smt_enabled_at_boot = 1;
 
+enum llc_override_values {
+	LLC_OVERRIDE_DISABLED,
+	LLC_OVERRIDE_SMT,
+	LLC_OVERRIDE_MC,
+	LLC_OVERRIDE_PKG,
+};
+
+static int llc_override;
+static int llc_override_changed;
+static DEFINE_MUTEX(llc_override_mutex);
+
+static const char * const llc_override_str[] = {
+	[LLC_OVERRIDE_DISABLED]	= "0",
+	[LLC_OVERRIDE_SMT]	= "smt",
+	[LLC_OVERRIDE_MC]	= "mc",
+	[LLC_OVERRIDE_PKG]	= "pkg",
+};
+
 /*
  * Returns 1 if the specified cpu should be brought up during boot.
  * Used to inhibit booting threads if they've been disabled or
@@ -1022,14 +1040,31 @@ static int powerpc_shared_cache_flags(void)
 	return SD_SHARE_LLC;
 }
 
-static int powerpc_shared_proc_flags(void)
+static int powerpc_mc_flags(void)
 {
+	int flags = 0;
+
 	if (static_branch_unlikely(&splpar_asym_pack))
-		return SD_ASYM_PACKING;
+		flags |= SD_ASYM_PACKING;
 
-	return 0;
+	if (READ_ONCE(llc_override) >= LLC_OVERRIDE_MC)
+		flags |= SD_SHARE_LLC;
+
+	return flags;
 }
 
+static int powerpc_pkg_flags(void)
+{
+	int flags = 0;
+
+	if (static_branch_unlikely(&splpar_asym_pack))
+		flags |= SD_ASYM_PACKING;
+
+	if (READ_ONCE(llc_override) >= LLC_OVERRIDE_PKG)
+		flags |= SD_SHARE_LLC;
+
+	return flags;
+}
 /*
  * We can't just pass cpu_l2_cache_mask() directly because
  * returns a non-const pointer and the compiler barfs on that.
@@ -1737,10 +1772,10 @@ static void __init build_sched_topology(void)
 
 	if (has_coregroup_support()) {
 		powerpc_topology[i++] =
-			SDTL_INIT(tl_mc_mask, powerpc_shared_proc_flags, MC);
+			SDTL_INIT(tl_mc_mask, powerpc_mc_flags, MC);
 	}
 
-	powerpc_topology[i++] = SDTL_INIT(tl_pkg_mask, powerpc_shared_proc_flags, PKG);
+	powerpc_topology[i++] = SDTL_INIT(tl_pkg_mask, powerpc_pkg_flags, PKG);
 
 	/* There must be one trailing NULL entry left.  */
 	BUG_ON(i >= ARRAY_SIZE(powerpc_topology) - 1);
@@ -1828,24 +1863,6 @@ void __noreturn arch_cpu_idle_dead(void)
 
 #endif
 
-enum llc_override_values {
-	LLC_OVERRIDE_DISABLED,
-	LLC_OVERRIDE_SMT,
-	LLC_OVERRIDE_MC,
-	LLC_OVERRIDE_PKG,
-};
-
-static int llc_override;
-static int llc_override_changed;
-static DEFINE_MUTEX(llc_override_mutex);
-
-static const char * const llc_override_str[] = {
-	[LLC_OVERRIDE_DISABLED]	= "0",
-	[LLC_OVERRIDE_SMT]	= "smt",
-	[LLC_OVERRIDE_MC]	= "mc",
-	[LLC_OVERRIDE_PKG]	= "pkg",
-};
-
 static ssize_t llc_override_get(struct file *file, char __user *ubuf,
 				size_t count, loff_t *ppos)
 {
-- 
2.52.0

[PATCH 4/4] powerpc/topology: Rebuild sched domains on llc_override change

[Shrikanth Hegde]

On changing the llc_override, rebuild the sched domains.

For the rebuild to happen, indicate it to the scheduler that
complete rebuild of the sched domains need to happen
via arch_update_cpu_topology(). 

With this, llc_override functionality is complete.

For example, on CPU10, 
domain0/name:SMT
domain1/name:MC
domain2/name:PKG

echo 0 > /sys/kernel/debug/powerpc/llc_override
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_SHARE_CPUCAPACITY SD_SHARE_LLC SD_PREFER_SIBLING
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_PREFER_SIBLING
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_PREFER_SIBLING

echo mc > /sys/kernel/debug/powerpc/llc_override
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_SHARE_CPUCAPACITY SD_SHARE_LLC SD_PREFER_SIBLING
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_SHARE_LLC SD_PREFER_SIBLING
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_PREFER_SIBLING

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
 arch/powerpc/kernel/smp.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 4b6512d25f73..6a4ee7d3b8e5 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -37,6 +37,7 @@
 #include <linux/clockchips.h>
 #include <linux/kexec.h>
 #include <linux/debugfs.h>
+#include <linux/cpuset.h>
 
 #include <asm/ptrace.h>
 #include <linux/atomic.h>
@@ -1863,6 +1864,16 @@ void __noreturn arch_cpu_idle_dead(void)
 
 #endif
 
+int arch_update_cpu_topology(void)
+{
+	if (READ_ONCE(llc_override_changed)) {
+		WRITE_ONCE(llc_override_changed, 0);
+		return 1;
+	}
+
+	return 0;
+}
+
 static ssize_t llc_override_get(struct file *file, char __user *ubuf,
 				size_t count, loff_t *ppos)
 {
@@ -1909,10 +1920,10 @@ static ssize_t llc_override_set(struct file *file, const char __user *ubuf,
 	if (override != READ_ONCE(llc_override)) {
 		WRITE_ONCE(llc_override, override);
 		WRITE_ONCE(llc_override_changed, 1);
-		pr_info("sched LLC override set to %s\n",
+		pr_info("sched LLC override set to %s. Rebuilding sched domains\n",
 			llc_override_str[override]);
 
-		/* Will be calling rebuild sched domain in later patches */
+		rebuild_sched_domains();
 	}
 
 	mutex_unlock(&llc_override_mutex);
-- 
2.52.0

Re: [PATCH 1/4] powerpc/topology: Introduce llc_override debug knob

[Srikar Dronamraju]

* Shrikanth Hegde <sshegde@linux.ibm.com> [2026-10-12 15:50:34]:

Hi Shrikanth,

> 
> As a result, it may be enabled but has no room to operate.
> Hence provide a debugfs option one can set to try experiment their
> workload with cache aware scheduling. This also provides ways to explore
> it on system with SMT=4 to see if there are any opportunities
> to improve or uncover bugs if there is any.
> 
> This does not change the hardware cache topology. It only changes the
> sched-domain level at which SD_SHARE_LLC is set.
> 
> Initially start with,
> - New debugs file called llc_override. It can be set/get on
>   /sys/kernel/debug/powerpc/llc_override
> - Adds parser logic for the debug knob.
> 

This is a good way to allow experimenting to know if a software override of
the LLC esp given the latency numbers within hemisphere and chip.

> There is no point in setting NUMA as the LLC domain. So give option
> until pkg to experiment with.
> 
> Actual flag manipulations and rebuilding sched domains are introduced
> in subsequent patches.
> 
> Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
> ---
> PS: Split is deliberate. If squashing all this into one patch helps,
>     let me know.
> 
>  arch/powerpc/kernel/smp.c | 90 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 90 insertions(+)
> 
> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> index 6a5a5469aaae..433757511adb 100644
> --- a/arch/powerpc/kernel/smp.c
> +++ b/arch/powerpc/kernel/smp.c
> @@ -36,6 +36,7 @@
>  #include <linux/pgtable.h>
>  #include <linux/clockchips.h>
>  #include <linux/kexec.h>
> +#include <linux/debugfs.h>
>  
>  #include <asm/ptrace.h>
>  #include <linux/atomic.h>
> @@ -1826,3 +1827,92 @@ void __noreturn arch_cpu_idle_dead(void)
>  }
>  
>  #endif
> +
> +enum llc_override_values {
> +	LLC_OVERRIDE_DISABLED,
> +	LLC_OVERRIDE_SMT,
> +	LLC_OVERRIDE_MC,
> +	LLC_OVERRIDE_PKG,
> +};
> +

For the current experiments, would it help to keep it simple and have just
SMT and MC. I mean we can include disabled and pkg based on our experiments.


-- 
Thanks and Regards
Srikar Dronamraju

Re: [PATCH 0/4] powerpc/topology: Introduce llc_override debugfs

[Srikar Dronamraju]

* Shrikanth Hegde <sshegde@linux.ibm.com> [2026-10-12 15:50:33]:


Hi Shrikanth,

> There is a new feature in scheduler called as Cache Aware Scheduling [1].
> It tries to keep related tasks within the same LLC domain while
> keeping the system reasonably balanced.
> 
> Cache Aware Scheduling assumes that the scheduler LLC domain is large enough
> to be a useful placement target. This is true on many systems where an LLC spans
> several cores, but not on PowerPC systems where the scheduler-visible LLC is at
> the SMT level. In that case, sd_llc_size is effectively the SMT width.
> 

Can we add a reference to the earlier attempt to try MCLLC a few years back.

-- 
Thanks and Regards
Srikar Dronamraju

Re: [PATCH 1/4] powerpc/topology: Introduce llc_override debug knob

[Shrikanth Hegde]

Hi Srikar. Thanks for taking a look at the patches.
    
>>   #endif
>> +
>> +enum llc_override_values {
>> +	LLC_OVERRIDE_DISABLED,
>> +	LLC_OVERRIDE_SMT,
>> +	LLC_OVERRIDE_MC,
>> +	LLC_OVERRIDE_PKG,
>> +};
>> +
> 
> For the current experiments, would it help to keep it simple and have just
> SMT and MC. I mean we can include disabled and pkg based on our experiments.
> 
I think we should keep disabled. So it is clear when disabled, there is no adverse
effect of it.

I think keeping pkg for experimentation seems okay. If not necessary we can remove it later.
Having at pkg gives you to try increased number of cores in a llc. So it may be a useful
too IMHO.

Re: [PATCH 0/4] powerpc/topology: Introduce llc_override debugfs

[Shrikanth Hegde]

On 10/12/26 5:49 PM, Srikar Dronamraju wrote:
> * Shrikanth Hegde <sshegde@linux.ibm.com> [2026-10-12 15:50:33]:
> 
> 
> Hi Shrikanth,
> 
>> There is a new feature in scheduler called as Cache Aware Scheduling [1].
>> It tries to keep related tasks within the same LLC domain while
>> keeping the system reasonably balanced.
>>
>> Cache Aware Scheduling assumes that the scheduler LLC domain is large enough
>> to be a useful placement target. This is true on many systems where an LLC spans
>> several cores, but not on PowerPC systems where the scheduler-visible LLC is at
>> the SMT level. In that case, sd_llc_size is effectively the SMT width.
>>
> 
> Can we add a reference to the earlier attempt to try MCLLC a few years back.
> 

Ah yes. will add it.

It is this one.
https://lore.kernel.org/all/1617341874-1205-1-git-send-email-ego@linux.vnet.ibm.com/

But I couldn't find an email id of Gautham which won't bounce. Based on what i know :)

Re: [PATCH 0/4] powerpc/topology: Introduce llc_override debugfs

[Tim Chen]

On Mon, 2026-10-12 at 15:50 +0530, Shrikanth Hegde wrote:
> There is a new feature in scheduler called as Cache Aware Scheduling [1].
> It tries to keep related tasks within the same LLC domain while
> keeping the system reasonably balanced.
> 
> Cache Aware Scheduling assumes that the scheduler LLC domain is large enough
> to be a useful placement target. This is true on many systems where an LLC spans
> several cores, but not on PowerPC systems where the scheduler-visible LLC is at
> the SMT level. In that case, sd_llc_size is effectively the SMT width.
> 
> This becomes visible in the capacity check:
>         return !fits_capacity((mm->sc_stat.nr_running_avg * cpu_smt_num_threads),
>                               scale * per_cpu(sd_llc_size, cpu));
> 
> As a result, Cache aware scheduling may be enabled but has no room to operate.
> 
> Hence provide a debugfs option to set LLC at specific domain so that
> one can try experiment their workload with cache aware scheduling.
> This also provides ways to explore it on system with SMT=4 to see if
> there are any opportunities to improve or uncover bugs if there is any.
> 
> Note it is a debug option and it is recommended to keep it disabled.
> There is no performance guarantees across different values.
> 
> [1]: https://lore.kernel.org/all/cover.1778703694.git.tim.c.chen@linux.intel.com/

Shrikanth,

This is an interesting idea. One question from a quick look at the code.

The override moves sd_llc, sd_llc_size and sd_llc_shared, but not
sd_llc_id. The id comes from arch_llc_mask(), which is
cpu_l2_cache_mask() on powerpc, so after your patches it is still
unique per core. It is also sticky: build_sched_domains() assigns it
only when it is -1, and it is reset only on CPU offline. So a rebuild
from the knob keeps the old ids.

Cache aware scheduling uses this id as the identity of an LLC:
p->preferred_llc, nr_pref_dst_llc/llc_counts[], and the
llc_id(cpu) == llc_id(grp->cpu) check in task_cache_work(). In that
loop the occupancy is now summed over the MC span, but the id check
rarely matches and is broken.

To make this work, arch_llc_mask() needs to follow the override, and
the llc ids need to be reset when the topology is forced to rebuild.

> 
> Tim, Chenyu, Peter,
> Are there any selftest or patches which is used for
> functional validation of cache aware scheduling?

We haven't created one. We validate mostly with workloads such as
hackbench, schbench and yogini (which can vary the number of threads
over time and track CPU assignment). I agree they are not ideal for
functional checks of the load balance path.

> per-LLC occupancy in /proc/{PID}/schedstat may not tell the full
> story when there are multiple processes and multiple LLC's.
> 
> Atleast for functional verification, we might need one if there is
> not one already. The reason being,
> - At present, we may need a custom workload. hackbench/schbench are
>   wakeup intensive and typically bail out even before load balance.
> - stress-ng is per process. So doesn't get cache aware scheduling.
> - A selftest could spwan specific number of threads till llc size etc
>   and ensure packing happens till core_count(llc_size) by default.
>   This could also be used for tunable verfifications.
> - Provide an ability to observe how much of the workload was contained
>   within the LLC due to cache aware scheduling or number of load
>   balances stopped due to preferred llc.

A selftest would be great and much welcomed.  

Tim

> 
> These are some initial thoughts I had. If it sounds ok, I can try to add
> a new selftest/kunit test. 
> 
> Shrikanth Hegde (4):
>   powerpc/topology: Introduce llc_override debug knob
>   powerpc/topology: Add docs for llc_override
>   powerpc/topology: Update mc/pkg flags based on llc_override
>   powerpc/topology: Rebuild sched domains on llc_override change
> 
>  Documentation/arch/powerpc/index.rst    |   1 +
>  Documentation/arch/powerpc/topology.rst |  27 +++++
>  arch/powerpc/kernel/smp.c               | 128 +++++++++++++++++++++++-
>  3 files changed, 151 insertions(+), 5 deletions(-)
>  create mode 100644 Documentation/arch/powerpc/topology.rst