[PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Abel Vesa]

According to internal documentation, the UFS AXI PHY clock requires
FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
the UFS controller fails when operating in MCQ mode, which is already
enabled in the device tree.

The UFS PHY ICE core clock already has this bit set, so apply the same
configuration to the UFS PHY AXI clock.

Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
Reported-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-eliza.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c
index 06ee1469badd..338494385752 100644
--- a/drivers/clk/qcom/gcc-eliza.c
+++ b/drivers/clk/qcom/gcc-eliza.c
@@ -3046,8 +3046,9 @@ static const struct regmap_config gcc_eliza_regmap_config = {
 
 static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap)
 {
-	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
+	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
 	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
 }
 
 static struct qcom_cc_driver_data gcc_eliza_driver_data = {

---
base-commit: 09c0f7f1bcdbc3c37a5a760cbec76bf18f278406
change-id: 20260323-eliza-gcc-set-ufs-axi-phyforce-mem-core-on-2ef9984ed022

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Dmitry Baryshkov]

On Mon, Mar 23, 2026 at 08:57:12PM +0200, Abel Vesa wrote:
> According to internal documentation, the UFS AXI PHY clock requires
> FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
> the UFS controller fails when operating in MCQ mode, which is already
> enabled in the device tree.
> 
> The UFS PHY ICE core clock already has this bit set, so apply the same
> configuration to the UFS PHY AXI clock.
> 
> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
> Reported-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/gcc-eliza.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

Do we need to apply the same fix to any other platform?

-- 
With best wishes
Dmitry

Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Konrad Dybcio]

On 3/23/26 8:25 PM, Dmitry Baryshkov wrote:
> On Mon, Mar 23, 2026 at 08:57:12PM +0200, Abel Vesa wrote:
>> According to internal documentation, the UFS AXI PHY clock requires
>> FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
>> the UFS controller fails when operating in MCQ mode, which is already
>> enabled in the device tree.
>>
>> The UFS PHY ICE core clock already has this bit set, so apply the same
>> configuration to the UFS PHY AXI clock.
>>
>> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
>> Reported-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> ---
>>  drivers/clk/qcom/gcc-eliza.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> 
> Do we need to apply the same fix to any other platform?

Most of them, actually

Konrad

Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Nitin Rawat]

On 3/24/2026 2:44 PM, Konrad Dybcio wrote:
> On 3/23/26 8:25 PM, Dmitry Baryshkov wrote:
>> On Mon, Mar 23, 2026 at 08:57:12PM +0200, Abel Vesa wrote:
>>> According to internal documentation, the UFS AXI PHY clock requires
>>> FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
>>> the UFS controller fails when operating in MCQ mode, which is already
>>> enabled in the device tree.
>>>
>>> The UFS PHY ICE core clock already has this bit set, so apply the same
>>> configuration to the UFS PHY AXI clock.
>>>
>>> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
>>> Reported-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>>   drivers/clk/qcom/gcc-eliza.c | 3 ++-
>>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>>
>> Do we need to apply the same fix to any other platform?
> 
> Most of them, actually
Only SM8850 is missing.
SM8650 and SM8750 has the change.

Regards,
NItin


> 
> Konrad

Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Dmitry Baryshkov]

On Tue, Mar 24, 2026 at 05:28:48PM +0530, Nitin Rawat wrote:
> 
> 
> On 3/24/2026 2:44 PM, Konrad Dybcio wrote:
> > On 3/23/26 8:25 PM, Dmitry Baryshkov wrote:
> > > On Mon, Mar 23, 2026 at 08:57:12PM +0200, Abel Vesa wrote:
> > > > According to internal documentation, the UFS AXI PHY clock requires
> > > > FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
> > > > the UFS controller fails when operating in MCQ mode, which is already
> > > > enabled in the device tree.
> > > > 
> > > > The UFS PHY ICE core clock already has this bit set, so apply the same
> > > > configuration to the UFS PHY AXI clock.
> > > > 
> > > > Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
> > > > Reported-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
> > > > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > > > ---
> > > >   drivers/clk/qcom/gcc-eliza.c | 3 ++-
> > > >   1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > > 
> > > Do we need to apply the same fix to any other platform?
> > 
> > Most of them, actually
> Only SM8850 is missing.

Could you please fix it too (in a new iteration or as a followup).

> SM8650 and SM8750 has the change.
> 
> Regards,
> NItin
> 
> 
> > 
> > Konrad
> 

-- 
With best wishes
Dmitry

Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Konrad Dybcio]

On 3/23/26 8:25 PM, Dmitry Baryshkov wrote:
> On Mon, Mar 23, 2026 at 08:57:12PM +0200, Abel Vesa wrote:
>> According to internal documentation, the UFS AXI PHY clock requires
>> FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
>> the UFS controller fails when operating in MCQ mode, which is already
>> enabled in the device tree.
>>
>> The UFS PHY ICE core clock already has this bit set, so apply the same
>> configuration to the UFS PHY AXI clock.
>>
>> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
>> Reported-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> ---
>>  drivers/clk/qcom/gcc-eliza.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> 
> Do we need to apply the same fix to any other platform?

FWIW on msm-5.10 (8450 kernel, from before-MCQ times) there's this
excerpt in ufs-qcom.c:


static void ufs_qcom_force_mem_config(struct ufs_hba *hba)
{
        struct ufs_clk_info *clki;

        /*
         * Configure the behavior of ufs clocks core and peripheral
         * memory state when they are turned off.
         * This configuration is required to allow retaining
         * ICE crypto configuration (including keys) when
         * core_clk_ice is turned off, and powering down
         * non-ICE RAMs of host controller.
         *
         * This is applicable only to gcc clocks.
         */
        list_for_each_entry(clki, &hba->clk_list_head, list) {

                /* skip it for non-gcc (rpmh) clocks */
                if (!strcmp(clki->name, "ref_clk"))
                        continue;

                if (!strcmp(clki->name, "core_clk_ice") ||
                        !strcmp(clki->name, "core_clk_ice_hw_ctl"))
                        qcom_clk_set_flags(clki->clk, CLKFLAG_RETAIN_MEM);
                else
                        qcom_clk_set_flags(clki->clk, CLKFLAG_NORETAIN_MEM);
                qcom_clk_set_flags(clki->clk, CLKFLAG_NORETAIN_PERIPH);
                qcom_clk_set_flags(clki->clk, CLKFLAG_PERIPH_OFF_CLEAR);
        }
}


i.e.:

* force_mem_core(true) for ICE, force_mem_core(false) otherwise
* set_force_periph_on(false) for all
* set_force_periph_off(false) for all


Notably, the Adreno driver messes with some of these settings too, as does
the DWC3 one. Older kernels (msm-4.19) also do so in MDSS, GDSC, CVP, 
camera MMC, PCIe drivers

Konrad

Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Konrad Dybcio]

On 3/23/26 7:57 PM, Abel Vesa wrote:
> According to internal documentation, the UFS AXI PHY clock requires
> FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
> the UFS controller fails when operating in MCQ mode, which is already
> enabled in the device tree.
> 
> The UFS PHY ICE core clock already has this bit set, so apply the same
> configuration to the UFS PHY AXI clock.
> 
> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
> Reported-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Taniya Das]

On 3/24/2026 12:27 AM, Abel Vesa wrote:
> diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c
> index 06ee1469badd..338494385752 100644
> --- a/drivers/clk/qcom/gcc-eliza.c
> +++ b/drivers/clk/qcom/gcc-eliza.c
> @@ -3046,8 +3046,9 @@ static const struct regmap_config gcc_eliza_regmap_config = {
>  
>  static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap)
>  {
> -	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> +	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
>  	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
> +	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
>  }
>  
>  static struct qcom_cc_driver_data gcc_eliza_driver_data = {
> 
> ---
> base-commit: 09c0f7f1bcdbc3c37a5a760cbec76bf18f278406
> change-id: 20260323-eliza-gcc-set-ufs-axi-phyforce-mem-core-on-2ef9984ed022

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>

-- 
Thanks,
Taniya Das

Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Bjorn Andersson]

On Mon, 23 Mar 2026 20:57:12 +0200, Abel Vesa wrote:
> According to internal documentation, the UFS AXI PHY clock requires
> FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
> the UFS controller fails when operating in MCQ mode, which is already
> enabled in the device tree.
> 
> The UFS PHY ICE core clock already has this bit set, so apply the same
> configuration to the UFS PHY AXI clock.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock
      commit: 3006f7fbc7ef53bf8316b02d7f23f647b24c3eca

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>