* [PATCH v4 0/2] Enable CTCU device for QCS8300
@ 2025-11-03 7:06 Jie Gan
2025-11-03 7:06 ` [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco Jie Gan
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Jie Gan @ 2025-11-03 7:06 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Jie Gan, Konrad Dybcio, Krzysztof Kozlowski
Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
configurations as SA8775p platform.
Changes in V4:
1. dtsi file has been renamed from qcs8300.dtsi -> monaco.dtsi
Link to V3 - https://lore.kernel.org/all/20251013-enable-ctcu-for-qcs8300-v3-0-611e6e0d3085@oss.qualcomm.com/
Changes in V3:
1. rebased on tag next-20251010
Link to V2 - https://lore.kernel.org/all/20250624095905.7609-1-jie.gan@oss.qualcomm.com/
Changes in V2:
1. Add Krzysztof's R-B tag for dt-binding patch.
2. Add Konrad's Acked-by tag for dt patch.
3. Rebased on tag next-20250623.
4. Missed email addresses for coresight's maintainers in V1, loop them.
Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-jie.gan@oss.qualcomm.com/
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Jie Gan (2):
dt-bindings: arm: add CTCU device for monaco
arm64: dts: qcom: monaco: Add CTCU and ETR nodes
.../bindings/arm/qcom,coresight-ctcu.yaml | 9 +-
arch/arm64/boot/dts/qcom/monaco.dtsi | 153 +++++++++++++++++++++
2 files changed, 160 insertions(+), 2 deletions(-)
---
base-commit: 9823120909776bbca58a3c55ef1f27d49283c1f3
change-id: 20251103-enable-ctcu-for-monaco-0db252ddf010
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco
2025-11-03 7:06 [PATCH v4 0/2] Enable CTCU device for QCS8300 Jie Gan
@ 2025-11-03 7:06 ` Jie Gan
2025-11-10 1:29 ` Jie Gan
` (2 more replies)
2025-11-03 7:06 ` [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes Jie Gan
` (2 subsequent siblings)
3 siblings, 3 replies; 13+ messages in thread
From: Jie Gan @ 2025-11-03 7:06 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Jie Gan, Krzysztof Kozlowski
The CTCU device for monaco shares the same configurations as SA8775p. Add
a fallback to enable the CTCU for monaco to utilize the compitable of the
SA8775p.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
index c969c16c21ef..460f38ddbd73 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
@@ -26,8 +26,13 @@ description: |
properties:
compatible:
- enum:
- - qcom,sa8775p-ctcu
+ oneOf:
+ - items:
+ - enum:
+ - qcom,qcs8300-ctcu
+ - const: qcom,sa8775p-ctcu
+ - enum:
+ - qcom,sa8775p-ctcu
reg:
maxItems: 1
--
2.34.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes
2025-11-03 7:06 [PATCH v4 0/2] Enable CTCU device for QCS8300 Jie Gan
2025-11-03 7:06 ` [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco Jie Gan
@ 2025-11-03 7:06 ` Jie Gan
2025-12-22 3:06 ` Jie Gan
` (2 more replies)
2025-12-19 14:01 ` (subset) [PATCH v4 0/2] Enable CTCU device for QCS8300 Suzuki K Poulose
2026-01-10 19:11 ` Bjorn Andersson
3 siblings, 3 replies; 13+ messages in thread
From: Jie Gan @ 2025-11-03 7:06 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Jie Gan, Konrad Dybcio
Add CTCU and ETR nodes in DT to enable expected functionalities.
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 153 +++++++++++++++++++++++++++++++++++
1 file changed, 153 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 816fa2af8a9a..1966dfad2dcc 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2483,6 +2483,35 @@ lpass_ag_noc: interconnect@3c40000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ctcu@4001000 {
+ compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu";
+ reg = <0x0 0x04001000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ctcu_in0: endpoint {
+ remote-endpoint = <&etr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ctcu_in1: endpoint {
+ remote-endpoint = <&etr1_out>;
+ };
+ };
+ };
+ };
+
stm@4002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x04002000 0x0 0x1000>,
@@ -2677,6 +2706,122 @@ qdss_funnel_out: endpoint {
};
};
+ replicator@4046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x04046000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ qdss_rep_in: endpoint {
+ remote-endpoint = <&swao_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_rep_out0: endpoint {
+ remote-endpoint = <&etr_rep_in>;
+ };
+ };
+ };
+ };
+
+ tmc@4048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x04048000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04c0 0x00>;
+
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr0_in: endpoint {
+ remote-endpoint = <&etr_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr0_out: endpoint {
+ remote-endpoint = <&ctcu_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@404e000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x0404e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etr_rep_in: endpoint {
+ remote-endpoint = <&qdss_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ etr_rep_out0: endpoint {
+ remote-endpoint = <&etr0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ etr_rep_out1: endpoint {
+ remote-endpoint = <&etr1_in>;
+ };
+ };
+ };
+ };
+
+ tmc@404f000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x0404f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04a0 0x40>;
+
+ arm,scatter-gather;
+ arm,buffer-size = <0x400000>;
+
+ in-ports {
+ port {
+ etr1_in: endpoint {
+ remote-endpoint = <&etr_rep_out1>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr1_out: endpoint {
+ remote-endpoint = <&ctcu_in1>;
+ };
+ };
+ };
+ };
+
tpdm@4841000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x04841000 0x0 0x1000>;
@@ -3106,6 +3251,14 @@ out-ports {
#address-cells = <1>;
#size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ swao_rep_out0: endpoint {
+ remote-endpoint = <&qdss_rep_in>;
+ };
+ };
+
port@1 {
reg = <1>;
--
2.34.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco
2025-11-03 7:06 ` [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco Jie Gan
@ 2025-11-10 1:29 ` Jie Gan
2025-11-21 8:26 ` Jie Gan
2025-12-19 9:08 ` Jie Gan
2 siblings, 0 replies; 13+ messages in thread
From: Jie Gan @ 2025-11-10 1:29 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Krzysztof Kozlowski
On 11/3/2025 3:06 PM, Jie Gan wrote:
> The CTCU device for monaco shares the same configurations as SA8775p. Add
> a fallback to enable the CTCU for monaco to utilize the compitable of the
> SA8775p.
>
Gentle reminder. Not sure do we have a change to apply this patch?
Thanks,
Jie
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Reviewed-by: Bjorn Andersson <andersson@kernel.org>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> index c969c16c21ef..460f38ddbd73 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> @@ -26,8 +26,13 @@ description: |
>
> properties:
> compatible:
> - enum:
> - - qcom,sa8775p-ctcu
> + oneOf:
> + - items:
> + - enum:
> + - qcom,qcs8300-ctcu
> + - const: qcom,sa8775p-ctcu
> + - enum:
> + - qcom,sa8775p-ctcu
>
> reg:
> maxItems: 1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco
2025-11-03 7:06 ` [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco Jie Gan
2025-11-10 1:29 ` Jie Gan
@ 2025-11-21 8:26 ` Jie Gan
2025-12-19 9:08 ` Jie Gan
2 siblings, 0 replies; 13+ messages in thread
From: Jie Gan @ 2025-11-21 8:26 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Krzysztof Kozlowski
On 11/3/2025 3:06 PM, Jie Gan wrote:
> The CTCU device for monaco shares the same configurations as SA8775p. Add
> a fallback to enable the CTCU for monaco to utilize the compitable of the
> SA8775p.
Hi Maintainers,
Greeting for the Friday!
Do we have a chance to apply this patch for 6.19?
Thanks for checking!
Jie
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Reviewed-by: Bjorn Andersson <andersson@kernel.org>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> index c969c16c21ef..460f38ddbd73 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> @@ -26,8 +26,13 @@ description: |
>
> properties:
> compatible:
> - enum:
> - - qcom,sa8775p-ctcu
> + oneOf:
> + - items:
> + - enum:
> + - qcom,qcs8300-ctcu
> + - const: qcom,sa8775p-ctcu
> + - enum:
> + - qcom,sa8775p-ctcu
>
> reg:
> maxItems: 1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco
2025-11-03 7:06 ` [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco Jie Gan
2025-11-10 1:29 ` Jie Gan
2025-11-21 8:26 ` Jie Gan
@ 2025-12-19 9:08 ` Jie Gan
2025-12-19 12:11 ` Suzuki K Poulose
2 siblings, 1 reply; 13+ messages in thread
From: Jie Gan @ 2025-12-19 9:08 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Krzysztof Kozlowski
On 11/3/2025 3:06 PM, Jie Gan wrote:
> The CTCU device for monaco shares the same configurations as SA8775p. Add
> a fallback to enable the CTCU for monaco to utilize the compitable of the
> SA8775p.
>
Gentle reminder.
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Reviewed-by: Bjorn Andersson <andersson@kernel.org>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> index c969c16c21ef..460f38ddbd73 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> @@ -26,8 +26,13 @@ description: |
>
> properties:
> compatible:
> - enum:
> - - qcom,sa8775p-ctcu
> + oneOf:
> + - items:
> + - enum:
> + - qcom,qcs8300-ctcu
> + - const: qcom,sa8775p-ctcu
> + - enum:
> + - qcom,sa8775p-ctcu
>
> reg:
> maxItems: 1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco
2025-12-19 9:08 ` Jie Gan
@ 2025-12-19 12:11 ` Suzuki K Poulose
2025-12-19 12:27 ` Konrad Dybcio
0 siblings, 1 reply; 13+ messages in thread
From: Suzuki K Poulose @ 2025-12-19 12:11 UTC (permalink / raw)
To: Jie Gan, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Krzysztof Kozlowski
On 19/12/2025 09:08, Jie Gan wrote:
>
>
> On 11/3/2025 3:06 PM, Jie Gan wrote:
>> The CTCU device for monaco shares the same configurations as SA8775p. Add
>> a fallback to enable the CTCU for monaco to utilize the compitable of the
>> SA8775p.
>>
>
> Gentle reminder.
I was under the assumption that this was going via msm tree ? Sorry, I
misunderstood. I can pull this in for v6.20
Suzuki
>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Reviewed-by: Bjorn Andersson <andersson@kernel.org>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +
>> ++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-
>> ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-
>> ctcu.yaml
>> index c969c16c21ef..460f38ddbd73 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>> @@ -26,8 +26,13 @@ description: |
>> properties:
>> compatible:
>> - enum:
>> - - qcom,sa8775p-ctcu
>> + oneOf:
>> + - items:
>> + - enum:
>> + - qcom,qcs8300-ctcu
>> + - const: qcom,sa8775p-ctcu
>> + - enum:
>> + - qcom,sa8775p-ctcu
>> reg:
>> maxItems: 1
>>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco
2025-12-19 12:11 ` Suzuki K Poulose
@ 2025-12-19 12:27 ` Konrad Dybcio
0 siblings, 0 replies; 13+ messages in thread
From: Konrad Dybcio @ 2025-12-19 12:27 UTC (permalink / raw)
To: Suzuki K Poulose, Jie Gan, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Krzysztof Kozlowski
On 12/19/25 1:11 PM, Suzuki K Poulose wrote:
> On 19/12/2025 09:08, Jie Gan wrote:
>>
>>
>> On 11/3/2025 3:06 PM, Jie Gan wrote:
>>> The CTCU device for monaco shares the same configurations as SA8775p. Add
>>> a fallback to enable the CTCU for monaco to utilize the compitable of the
>>> SA8775p.
>>>
>>
>> Gentle reminder.
>
> I was under the assumption that this was going via msm tree ? Sorry, I
> misunderstood. I can pull this in for v6.20
Please take it through your tree
Konrad
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: (subset) [PATCH v4 0/2] Enable CTCU device for QCS8300
2025-11-03 7:06 [PATCH v4 0/2] Enable CTCU device for QCS8300 Jie Gan
2025-11-03 7:06 ` [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco Jie Gan
2025-11-03 7:06 ` [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes Jie Gan
@ 2025-12-19 14:01 ` Suzuki K Poulose
2026-01-10 19:11 ` Bjorn Andersson
3 siblings, 0 replies; 13+ messages in thread
From: Suzuki K Poulose @ 2025-12-19 14:01 UTC (permalink / raw)
To: Mike Leach, James Clark, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Yuanfang Zhang, Mao Jinlong,
Bjorn Andersson, Konrad Dybcio, Jie Gan
Cc: Suzuki K Poulose, linux-arm-msm, coresight, linux-arm-kernel,
devicetree, linux-kernel, Konrad Dybcio, Krzysztof Kozlowski
On Mon, 03 Nov 2025 15:06:20 +0800, Jie Gan wrote:
> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> configurations as SA8775p platform.
>
> Changes in V4:
> 1. dtsi file has been renamed from qcs8300.dtsi -> monaco.dtsi
> Link to V3 - https://lore.kernel.org/all/20251013-enable-ctcu-for-qcs8300-v3-0-611e6e0d3085@oss.qualcomm.com/
>
> [...]
Applied, thanks!
[1/2] dt-bindings: arm: add CTCU device for monaco
https://git.kernel.org/coresight/c/51cd1fb70e08
Best regards,
--
Suzuki K Poulose <suzuki.poulose@arm.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes
2025-11-03 7:06 ` [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes Jie Gan
@ 2025-12-22 3:06 ` Jie Gan
2026-01-06 1:29 ` Jie Gan
2026-01-09 11:02 ` Jie Gan
2 siblings, 0 replies; 13+ messages in thread
From: Jie Gan @ 2025-12-22 3:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Tingwei Zhang, Mao Jinlong,
Suzuki K Poulose, Rob Herring
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Konrad Dybcio, Mike Leach, James Clark,
Krzysztof Kozlowski, Conor Dooley
On 11/3/2025 3:06 PM, Jie Gan wrote:
> Add CTCU and ETR nodes in DT to enable expected functionalities.
>
> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/monaco.dtsi | 153 +++++++++++++++++++++++++++++++++++
> 1 file changed, 153 insertions(+)
>
Gentle reminder.
The dt-binding patch has applied to Coresight tree.
> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index 816fa2af8a9a..1966dfad2dcc 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2483,6 +2483,35 @@ lpass_ag_noc: interconnect@3c40000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ctcu@4001000 {
> + compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu";
> + reg = <0x0 0x04001000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + ctcu_in0: endpoint {
> + remote-endpoint = <&etr0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + ctcu_in1: endpoint {
> + remote-endpoint = <&etr1_out>;
> + };
> + };
> + };
> + };
> +
> stm@4002000 {
> compatible = "arm,coresight-stm", "arm,primecell";
> reg = <0x0 0x04002000 0x0 0x1000>,
> @@ -2677,6 +2706,122 @@ qdss_funnel_out: endpoint {
> };
> };
>
> + replicator@4046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x04046000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + qdss_rep_in: endpoint {
> + remote-endpoint = <&swao_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + qdss_rep_out0: endpoint {
> + remote-endpoint = <&etr_rep_in>;
> + };
> + };
> + };
> + };
> +
> + tmc@4048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x04048000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + iommus = <&apps_smmu 0x04c0 0x00>;
> +
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr0_in: endpoint {
> + remote-endpoint = <&etr_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etr0_out: endpoint {
> + remote-endpoint = <&ctcu_in0>;
> + };
> + };
> + };
> + };
> +
> + replicator@404e000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x0404e000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + etr_rep_in: endpoint {
> + remote-endpoint = <&qdss_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + etr_rep_out0: endpoint {
> + remote-endpoint = <&etr0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + etr_rep_out1: endpoint {
> + remote-endpoint = <&etr1_in>;
> + };
> + };
> + };
> + };
> +
> + tmc@404f000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x0404f000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + iommus = <&apps_smmu 0x04a0 0x40>;
> +
> + arm,scatter-gather;
> + arm,buffer-size = <0x400000>;
> +
> + in-ports {
> + port {
> + etr1_in: endpoint {
> + remote-endpoint = <&etr_rep_out1>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etr1_out: endpoint {
> + remote-endpoint = <&ctcu_in1>;
> + };
> + };
> + };
> + };
> +
> tpdm@4841000 {
> compatible = "qcom,coresight-tpdm", "arm,primecell";
> reg = <0x0 0x04841000 0x0 0x1000>;
> @@ -3106,6 +3251,14 @@ out-ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + port@0 {
> + reg = <0>;
> +
> + swao_rep_out0: endpoint {
> + remote-endpoint = <&qdss_rep_in>;
> + };
> + };
> +
> port@1 {
> reg = <1>;
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes
2025-11-03 7:06 ` [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes Jie Gan
2025-12-22 3:06 ` Jie Gan
@ 2026-01-06 1:29 ` Jie Gan
2026-01-09 11:02 ` Jie Gan
2 siblings, 0 replies; 13+ messages in thread
From: Jie Gan @ 2026-01-06 1:29 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Tingwei Zhang,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Konrad Dybcio, Suzuki K Poulose, Mike Leach,
James Clark, Rob Herring, Mao Jinlong, Yuanfang Zhang
On 11/3/2025 3:06 PM, Jie Gan wrote:
> Add CTCU and ETR nodes in DT to enable expected functionalities.
>
Gentle ping, this patch should go through QCOM tree.
> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/monaco.dtsi | 153 +++++++++++++++++++++++++++++++++++
> 1 file changed, 153 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index 816fa2af8a9a..1966dfad2dcc 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2483,6 +2483,35 @@ lpass_ag_noc: interconnect@3c40000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ctcu@4001000 {
> + compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu";
> + reg = <0x0 0x04001000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + ctcu_in0: endpoint {
> + remote-endpoint = <&etr0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + ctcu_in1: endpoint {
> + remote-endpoint = <&etr1_out>;
> + };
> + };
> + };
> + };
> +
> stm@4002000 {
> compatible = "arm,coresight-stm", "arm,primecell";
> reg = <0x0 0x04002000 0x0 0x1000>,
> @@ -2677,6 +2706,122 @@ qdss_funnel_out: endpoint {
> };
> };
>
> + replicator@4046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x04046000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + qdss_rep_in: endpoint {
> + remote-endpoint = <&swao_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + qdss_rep_out0: endpoint {
> + remote-endpoint = <&etr_rep_in>;
> + };
> + };
> + };
> + };
> +
> + tmc@4048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x04048000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + iommus = <&apps_smmu 0x04c0 0x00>;
> +
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr0_in: endpoint {
> + remote-endpoint = <&etr_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etr0_out: endpoint {
> + remote-endpoint = <&ctcu_in0>;
> + };
> + };
> + };
> + };
> +
> + replicator@404e000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x0404e000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + etr_rep_in: endpoint {
> + remote-endpoint = <&qdss_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + etr_rep_out0: endpoint {
> + remote-endpoint = <&etr0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + etr_rep_out1: endpoint {
> + remote-endpoint = <&etr1_in>;
> + };
> + };
> + };
> + };
> +
> + tmc@404f000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x0404f000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + iommus = <&apps_smmu 0x04a0 0x40>;
> +
> + arm,scatter-gather;
> + arm,buffer-size = <0x400000>;
> +
> + in-ports {
> + port {
> + etr1_in: endpoint {
> + remote-endpoint = <&etr_rep_out1>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etr1_out: endpoint {
> + remote-endpoint = <&ctcu_in1>;
> + };
> + };
> + };
> + };
> +
> tpdm@4841000 {
> compatible = "qcom,coresight-tpdm", "arm,primecell";
> reg = <0x0 0x04841000 0x0 0x1000>;
> @@ -3106,6 +3251,14 @@ out-ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + port@0 {
> + reg = <0>;
> +
> + swao_rep_out0: endpoint {
> + remote-endpoint = <&qdss_rep_in>;
> + };
> + };
> +
> port@1 {
> reg = <1>;
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes
2025-11-03 7:06 ` [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes Jie Gan
2025-12-22 3:06 ` Jie Gan
2026-01-06 1:29 ` Jie Gan
@ 2026-01-09 11:02 ` Jie Gan
2 siblings, 0 replies; 13+ messages in thread
From: Jie Gan @ 2026-01-09 11:02 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Konrad Dybcio, Tingwei Zhang,
Mao Jinlong
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Suzuki K Poulose, Mike Leach, Rob Herring,
James Clark, Krzysztof Kozlowski, Conor Dooley
On 11/3/2025 3:06 PM, Jie Gan wrote:
> Add CTCU and ETR nodes in DT to enable expected functionalities.
>
Gentle ping. Do we have a chance to apply this patch?
Thanks,
Jie
> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/monaco.dtsi | 153 +++++++++++++++++++++++++++++++++++
> 1 file changed, 153 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index 816fa2af8a9a..1966dfad2dcc 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2483,6 +2483,35 @@ lpass_ag_noc: interconnect@3c40000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ctcu@4001000 {
> + compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu";
> + reg = <0x0 0x04001000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + ctcu_in0: endpoint {
> + remote-endpoint = <&etr0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + ctcu_in1: endpoint {
> + remote-endpoint = <&etr1_out>;
> + };
> + };
> + };
> + };
> +
> stm@4002000 {
> compatible = "arm,coresight-stm", "arm,primecell";
> reg = <0x0 0x04002000 0x0 0x1000>,
> @@ -2677,6 +2706,122 @@ qdss_funnel_out: endpoint {
> };
> };
>
> + replicator@4046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x04046000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + qdss_rep_in: endpoint {
> + remote-endpoint = <&swao_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + qdss_rep_out0: endpoint {
> + remote-endpoint = <&etr_rep_in>;
> + };
> + };
> + };
> + };
> +
> + tmc@4048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x04048000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + iommus = <&apps_smmu 0x04c0 0x00>;
> +
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr0_in: endpoint {
> + remote-endpoint = <&etr_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etr0_out: endpoint {
> + remote-endpoint = <&ctcu_in0>;
> + };
> + };
> + };
> + };
> +
> + replicator@404e000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x0 0x0404e000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + etr_rep_in: endpoint {
> + remote-endpoint = <&qdss_rep_out0>;
> + };
> + };
> + };
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + etr_rep_out0: endpoint {
> + remote-endpoint = <&etr0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + etr_rep_out1: endpoint {
> + remote-endpoint = <&etr1_in>;
> + };
> + };
> + };
> + };
> +
> + tmc@404f000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x0 0x0404f000 0x0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + iommus = <&apps_smmu 0x04a0 0x40>;
> +
> + arm,scatter-gather;
> + arm,buffer-size = <0x400000>;
> +
> + in-ports {
> + port {
> + etr1_in: endpoint {
> + remote-endpoint = <&etr_rep_out1>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + etr1_out: endpoint {
> + remote-endpoint = <&ctcu_in1>;
> + };
> + };
> + };
> + };
> +
> tpdm@4841000 {
> compatible = "qcom,coresight-tpdm", "arm,primecell";
> reg = <0x0 0x04841000 0x0 0x1000>;
> @@ -3106,6 +3251,14 @@ out-ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + port@0 {
> + reg = <0>;
> +
> + swao_rep_out0: endpoint {
> + remote-endpoint = <&qdss_rep_in>;
> + };
> + };
> +
> port@1 {
> reg = <1>;
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: (subset) [PATCH v4 0/2] Enable CTCU device for QCS8300
2025-11-03 7:06 [PATCH v4 0/2] Enable CTCU device for QCS8300 Jie Gan
` (2 preceding siblings ...)
2025-12-19 14:01 ` (subset) [PATCH v4 0/2] Enable CTCU device for QCS8300 Suzuki K Poulose
@ 2026-01-10 19:11 ` Bjorn Andersson
3 siblings, 0 replies; 13+ messages in thread
From: Bjorn Andersson @ 2026-01-10 19:11 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Yuanfang Zhang,
Mao Jinlong, Konrad Dybcio, Jie Gan
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Konrad Dybcio, Krzysztof Kozlowski
On Mon, 03 Nov 2025 15:06:20 +0800, Jie Gan wrote:
> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> configurations as SA8775p platform.
>
> Changes in V4:
> 1. dtsi file has been renamed from qcs8300.dtsi -> monaco.dtsi
> Link to V3 - https://lore.kernel.org/all/20251013-enable-ctcu-for-qcs8300-v3-0-611e6e0d3085@oss.qualcomm.com/
>
> [...]
Applied, thanks!
[2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes
commit: 4f791e008807a1e7743cf6048822bab259b2ad0c
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-01-10 19:11 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-11-03 7:06 [PATCH v4 0/2] Enable CTCU device for QCS8300 Jie Gan
2025-11-03 7:06 ` [PATCH v4 1/2] dt-bindings: arm: add CTCU device for monaco Jie Gan
2025-11-10 1:29 ` Jie Gan
2025-11-21 8:26 ` Jie Gan
2025-12-19 9:08 ` Jie Gan
2025-12-19 12:11 ` Suzuki K Poulose
2025-12-19 12:27 ` Konrad Dybcio
2025-11-03 7:06 ` [PATCH v4 2/2] arm64: dts: qcom: monaco: Add CTCU and ETR nodes Jie Gan
2025-12-22 3:06 ` Jie Gan
2026-01-06 1:29 ` Jie Gan
2026-01-09 11:02 ` Jie Gan
2025-12-19 14:01 ` (subset) [PATCH v4 0/2] Enable CTCU device for QCS8300 Suzuki K Poulose
2026-01-10 19:11 ` Bjorn Andersson
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