[PATCH 0/3] SC7280 DPU fixups

[PATCH 0/3] SC7280 DPU fixups

[Konrad Dybcio]

Found a couple mistakes, this series attempts to fix it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (3):
      drm/msm/dpu: Fix SC7280 PP length
      drm/msm/dpu: Add missing DPU_DSC_OUTPUT_CTRL to SC7280
      drm/msm/dpu: Fix SC7280 DSC block length

 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
---
base-commit: 926f75c8a5ab70567eb4c2d82fbc96963313e564
change-id: 20230920-topic-7280_dpu-59a29cedca6e

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@linaro.org>

[PATCH 1/3] drm/msm/dpu: Fix SC7280 PP length

[Konrad Dybcio]

Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
macros") unrolled a macro incorrectly. Fix that.

Fixes: 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 3b5061c4402a..dc3198335164 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -126,7 +126,7 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = {
 static const struct dpu_pingpong_cfg sc7280_pp[] = {
 	{
 		.name = "pingpong_0", .id = PINGPONG_0,
-		.base = 0x69000, .len = 0,
+		.base = 0x69000, .len = 0xd4,
 		.features = BIT(DPU_PINGPONG_DITHER),
 		.sblk = &sc7280_pp_sblk,
 		.merge_3d = 0,
@@ -134,7 +134,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
 		.intr_rdptr = -1,
 	}, {
 		.name = "pingpong_1", .id = PINGPONG_1,
-		.base = 0x6a000, .len = 0,
+		.base = 0x6a000, .len = 0xd4,
 		.features = BIT(DPU_PINGPONG_DITHER),
 		.sblk = &sc7280_pp_sblk,
 		.merge_3d = 0,
@@ -142,7 +142,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
 		.intr_rdptr = -1,
 	}, {
 		.name = "pingpong_2", .id = PINGPONG_2,
-		.base = 0x6b000, .len = 0,
+		.base = 0x6b000, .len = 0xd4,
 		.features = BIT(DPU_PINGPONG_DITHER),
 		.sblk = &sc7280_pp_sblk,
 		.merge_3d = 0,
@@ -150,7 +150,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
 		.intr_rdptr = -1,
 	}, {
 		.name = "pingpong_3", .id = PINGPONG_3,
-		.base = 0x6c000, .len = 0,
+		.base = 0x6c000, .len = 0xd4,
 		.features = BIT(DPU_PINGPONG_DITHER),
 		.sblk = &sc7280_pp_sblk,
 		.merge_3d = 0,

-- 
2.39.2

Re: [PATCH 1/3] drm/msm/dpu: Fix SC7280 PP length

[Abhinav Kumar]

On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
> Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
> macros") unrolled a macro incorrectly. Fix that.
> 

No, its correct from what i can tell.

Before inlining it was using PP_BLK_DITHER macro and not PP_BLK.

PP_BLK_DITHER has a len of 0 and not 0xd4.

Hence I cannot see whats wrong here.

> Fixes: 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 3b5061c4402a..dc3198335164 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -126,7 +126,7 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = {
>   static const struct dpu_pingpong_cfg sc7280_pp[] = {
>   	{
>   		.name = "pingpong_0", .id = PINGPONG_0,
> -		.base = 0x69000, .len = 0,
> +		.base = 0x69000, .len = 0xd4,
>   		.features = BIT(DPU_PINGPONG_DITHER),
>   		.sblk = &sc7280_pp_sblk,
>   		.merge_3d = 0,
> @@ -134,7 +134,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
>   		.intr_rdptr = -1,
>   	}, {
>   		.name = "pingpong_1", .id = PINGPONG_1,
> -		.base = 0x6a000, .len = 0,
> +		.base = 0x6a000, .len = 0xd4,
>   		.features = BIT(DPU_PINGPONG_DITHER),
>   		.sblk = &sc7280_pp_sblk,
>   		.merge_3d = 0,
> @@ -142,7 +142,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
>   		.intr_rdptr = -1,
>   	}, {
>   		.name = "pingpong_2", .id = PINGPONG_2,
> -		.base = 0x6b000, .len = 0,
> +		.base = 0x6b000, .len = 0xd4,
>   		.features = BIT(DPU_PINGPONG_DITHER),
>   		.sblk = &sc7280_pp_sblk,
>   		.merge_3d = 0,
> @@ -150,7 +150,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
>   		.intr_rdptr = -1,
>   	}, {
>   		.name = "pingpong_3", .id = PINGPONG_3,
> -		.base = 0x6c000, .len = 0,
> +		.base = 0x6c000, .len = 0xd4,
>   		.features = BIT(DPU_PINGPONG_DITHER),
>   		.sblk = &sc7280_pp_sblk,
>   		.merge_3d = 0,
> 

Re: [PATCH 1/3] drm/msm/dpu: Fix SC7280 PP length

[Konrad Dybcio]

On 9/21/23 01:41, Abhinav Kumar wrote:
> 
> 
> On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
>> Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
>> macros") unrolled a macro incorrectly. Fix that.
>>
> 
> No, its correct from what i can tell.
> 
> Before inlining it was using PP_BLK_DITHER macro and not PP_BLK.
> 
> PP_BLK_DITHER has a len of 0 and not 0xd4.
> 
> Hence I cannot see whats wrong here.
Right, I misread the thing..

Konrad

[PATCH 2/3] drm/msm/dpu: Add missing DPU_DSC_OUTPUT_CTRL to SC7280

[Konrad Dybcio]

DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
CFG 1.0.0. SC7280 is one of them. Add it.

Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index dc3198335164..b6a59d7b94c4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -164,7 +164,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
 	{
 		.name = "dce_0_0", .id = DSC_0,
 		.base = 0x80000, .len = 0x4,
-		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN) | BIT(DPU_DSC_OUTPUT_CTRL),
 		.sblk = &dsc_sblk_0,
 	},
 };

-- 
2.39.2

Re: [PATCH 2/3] drm/msm/dpu: Add missing DPU_DSC_OUTPUT_CTRL to SC7280

[Abhinav Kumar]

On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
> DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
> CFG 1.0.0. SC7280 is one of them. Add it.
> 

sc7280 and all other chipsets using DSC 1.2 use dpu_hw_dsc_init_1_2 and 
not dpu_hw_dsc_init.

dpu_hw_dsc_init_1_2 assigns the dsc_bind_pingpong_blk op by default.

So this change is not needed.

> Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index dc3198335164..b6a59d7b94c4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -164,7 +164,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
>   	{
>   		.name = "dce_0_0", .id = DSC_0,
>   		.base = 0x80000, .len = 0x4,
> -		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN) | BIT(DPU_DSC_OUTPUT_CTRL),
>   		.sblk = &dsc_sblk_0,
>   	},
>   };
> 

Re: [PATCH 2/3] drm/msm/dpu: Add missing DPU_DSC_OUTPUT_CTRL to SC7280

[Konrad Dybcio]

On 9/21/23 02:01, Abhinav Kumar wrote:
> 
> 
> On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
>> DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
>> CFG 1.0.0. SC7280 is one of them. Add it.
>>
> 
> sc7280 and all other chipsets using DSC 1.2 use dpu_hw_dsc_init_1_2 and 
> not dpu_hw_dsc_init.
> 
> dpu_hw_dsc_init_1_2 assigns the dsc_bind_pingpong_blk op by default.
> 
> So this change is not needed.
Gah, I don't like that we do it behind the scenes but I agree it's a NOP..

Konrad

[PATCH 3/3] drm/msm/dpu: Fix SC7280 DSC block length

[Konrad Dybcio]

Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
the block length from a wrong value to another wrong value.

Use the correct one this time.

Fixes: e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index b6a59d7b94c4..de5e1a57a142 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -163,7 +163,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
 static const struct dpu_dsc_cfg sc7280_dsc[] = {
 	{
 		.name = "dce_0_0", .id = DSC_0,
-		.base = 0x80000, .len = 0x4,
+		.base = 0x80000, .len = 0x10,
 		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN) | BIT(DPU_DSC_OUTPUT_CTRL),
 		.sblk = &dsc_sblk_0,
 	},

-- 
2.39.2

Re: [PATCH 3/3] drm/msm/dpu: Fix SC7280 DSC block length

[Abhinav Kumar]

On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
> Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
> the block length from a wrong value to another wrong value.
> 
> Use the correct one this time.
> 

No that change is correct as well.

After we moved to sub-blk parsing, we have enc and ctl blocks length 
used from the dsc_sblk_* instead:

static const struct dpu_dsc_sub_blks dsc_sblk_0 = {
         .enc = {.name = "enc", .base = 0x100, .len = 0x9c},
         .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10},
};

static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
         .enc = {.name = "enc", .base = 0x200, .len = 0x9c},
         .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
};

The main block has only one register now which is the DSC_CMN register.

Hence len = 0x4 is correct for that.

Sorry, but this is right too :)

> Fixes: e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index b6a59d7b94c4..de5e1a57a142 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -163,7 +163,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
>   static const struct dpu_dsc_cfg sc7280_dsc[] = {
>   	{
>   		.name = "dce_0_0", .id = DSC_0,
> -		.base = 0x80000, .len = 0x4,
> +		.base = 0x80000, .len = 0x10,
>   		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN) | BIT(DPU_DSC_OUTPUT_CTRL),
>   		.sblk = &dsc_sblk_0,
>   	},
>