* [PATCH v2 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
2026-02-03 4:31 [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
@ 2026-02-03 4:31 ` Sushrut Shree Trivedi
2026-02-03 9:22 ` Konrad Dybcio
2026-02-03 18:07 ` Dmitry Baryshkov
2026-02-03 4:31 ` [PATCH v2 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Sushrut Shree Trivedi
` (3 subsequent siblings)
4 siblings, 2 replies; 10+ messages in thread
From: Sushrut Shree Trivedi @ 2026-02-03 4:31 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Sushrut Shree Trivedi
Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
has three downstream ports.Two embedded Ethernet devices are present
on one of the downstream ports. All the ports present in the
node represent the downstream ports and embedded endpoints.
Power to the TC9563 is supplied through two LDO regulators, which
are on by default and are added as fixed regulators. TC9563 can be
configured through I2C.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 138 +++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 619a42b5ef48..89bbcab0908d 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -5,9 +5,47 @@
/dts-v1/;
/plugin/;
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+&{/} {
+
+ vreg_dc_12v: regulator-vreg-dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_DC_12V";
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ };
+
+ vreg_1p8: regulator-vreg-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_1P8";
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ vin-supply = <&vreg_dc_12v>;
+ };
+
+ vreg_0p9: regulator-vreg-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_0P9";
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ vin-supply = <&vreg_dc_12v>;
+ };
+};
+
&spi11 {
#address-cells = <1>;
#size-cells = <0>;
@@ -19,3 +57,103 @@ st33htpm0: tpm@0 {
spi-max-frequency = <20000000>;
};
};
+
+&pcie0 {
+ bus-range = <0x00 0xff>;
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>,
+ <0x208 &apps_smmu 0x1c04 0x1>,
+ <0x210 &apps_smmu 0x1c05 0x1>,
+ <0x218 &apps_smmu 0x1c06 0x1>,
+ <0x300 &apps_smmu 0x1c07 0x1>,
+ <0x400 &apps_smmu 0x1c08 0x1>,
+ <0x500 &apps_smmu 0x1c09 0x1>,
+ <0x501 &apps_smmu 0x1c10 0x1>;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pcie0_port {
+ pcie0_switch0_usp: pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+
+ vddc-supply = <&vreg_0p9>;
+ vdd18-supply = <&vreg_1p8>;
+ vdd09-supply = <&vreg_0p9>;
+ vddio1-supply = <&vreg_1p8>;
+ vddio2-supply = <&vreg_1p8>;
+ vddio18-supply = <&vreg_1p8>;
+
+ i2c-parent = <&i2c1 0x77>;
+
+ resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie0_switch0_dsp1: pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie0_switch0_dsp2: pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie0_switch0_dsp3: pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+
+ pcie0_switch0_eth0: pci@0,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie0_switch0_eth1: pci@0,1 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
+&tlmm {
+ pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
+ pins = "gpio78";
+ function = "gpio";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+};
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
2026-02-03 4:31 ` [PATCH v2 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Sushrut Shree Trivedi
@ 2026-02-03 9:22 ` Konrad Dybcio
2026-02-03 18:07 ` Dmitry Baryshkov
1 sibling, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2026-02-03 9:22 UTC (permalink / raw)
To: Sushrut Shree Trivedi, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 2/3/26 5:31 AM, Sushrut Shree Trivedi wrote:
> Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
> has three downstream ports.Two embedded Ethernet devices are present
> on one of the downstream ports. All the ports present in the
> node represent the downstream ports and embedded endpoints.
>
> Power to the TC9563 is supplied through two LDO regulators, which
> are on by default and are added as fixed regulators. TC9563 can be
> configured through I2C.
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
Largely the same label comments as in patch 2
[...]
> +&{/} {
> +
> + vreg_dc_12v: regulator-vreg-dc-12v {
> + compatible = "regulator-fixed";
> + regulator-name = "VREG_DC_12V";
> +
> + regulator-always-on;
> + regulator-boot-on;
Nit: please move these boolean properties below min/max-microvolt
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
2026-02-03 4:31 ` [PATCH v2 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Sushrut Shree Trivedi
2026-02-03 9:22 ` Konrad Dybcio
@ 2026-02-03 18:07 ` Dmitry Baryshkov
1 sibling, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-02-03 18:07 UTC (permalink / raw)
To: Sushrut Shree Trivedi
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Tue, Feb 03, 2026 at 10:01:28AM +0530, Sushrut Shree Trivedi wrote:
> Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
> has three downstream ports.Two embedded Ethernet devices are present
> on one of the downstream ports. All the ports present in the
> node represent the downstream ports and embedded endpoints.
>
> Power to the TC9563 is supplied through two LDO regulators, which
> are on by default and are added as fixed regulators. TC9563 can be
> configured through I2C.
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
> .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 138 +++++++++++++++++++++
> 1 file changed, 138 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> index 619a42b5ef48..89bbcab0908d 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> @@ -5,9 +5,47 @@
>
> /dts-v1/;
> /plugin/;
> +#include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
>
> +&{/} {
> +
> + vreg_dc_12v: regulator-vreg-dc-12v {
> + compatible = "regulator-fixed";
> + regulator-name = "VREG_DC_12V";
> +
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <24000000>;
> + regulator-max-microvolt = <24000000>;
> + };
> +
> + vreg_1p8: regulator-vreg-1p8 {
1p8 < dc-12v
> + compatible = "regulator-fixed";
> + regulator-name = "VREG_1P8";
> +
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + vin-supply = <&vreg_dc_12v>;
> + };
> +
> + vreg_0p9: regulator-vreg-0p9 {
> + compatible = "regulator-fixed";
> + regulator-name = "VREG_0P9";
> +
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> +
> + vin-supply = <&vreg_dc_12v>;
> + };
> +};
> +
> &spi11 {
> #address-cells = <1>;
> #size-cells = <0>;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
2026-02-03 4:31 [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
2026-02-03 4:31 ` [PATCH v2 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Sushrut Shree Trivedi
@ 2026-02-03 4:31 ` Sushrut Shree Trivedi
2026-02-03 9:21 ` Konrad Dybcio
2026-02-03 4:37 ` [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Sushrut Shree Trivedi @ 2026-02-03 4:31 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Sushrut Shree Trivedi
Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
in cascade to the first TC9563 switch via the former's downstream port.
Two embedded Ethernet devices are present on one of the downstream
ports of this second switch as well. All the ports present in the
node represent the downstream ports and embedded endpoints.
The second TC9563 is powered up via the same LDO regulators as the first
one, and these can be controlled via two GPIOs, which are already present
as fixed regulators. This TC9563 can also be configured through I2C.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 96 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +--
2 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 89bbcab0908d..1744c9c8bd50 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -146,6 +146,91 @@ pcie0_switch0_eth1: pci@0,1 {
};
};
+&pcie1 {
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>,
+ <0x208 &apps_smmu 0x1c84 0x1>,
+ <0x210 &apps_smmu 0x1c85 0x1>,
+ <0x218 &apps_smmu 0x1c86 0x1>,
+ <0x300 &apps_smmu 0x1c87 0x1>,
+ <0x408 &apps_smmu 0x1c90 0x1>,
+ <0x410 &apps_smmu 0x1c91 0x1>,
+ <0x418 &apps_smmu 0x1c92 0x1>,
+ <0x500 &apps_smmu 0x1c93 0x1>,
+ <0x600 &apps_smmu 0x1c94 0x1>,
+ <0x700 &apps_smmu 0x1c95 0x1>,
+ <0x701 &apps_smmu 0x1c96 0x1>,
+ <0x800 &apps_smmu 0x1c97 0x1>,
+ <0x900 &apps_smmu 0x1c98 0x1>,
+ <0x901 &apps_smmu 0x1c99 0x1>;
+};
+
+&pcie1_switch0_dsp1 {
+ pcie1_switch1_usp: pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x30000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+
+ vddc-supply = <&vdd_ntn_0p9>;
+ vdd18-supply = <&vdd_ntn_1p8>;
+ vdd09-supply = <&vdd_ntn_0p9>;
+ vddio1-supply = <&vdd_ntn_1p8>;
+ vddio2-supply = <&vdd_ntn_1p8>;
+ vddio18-supply = <&vdd_ntn_1p8>;
+
+ i2c-parent = <&i2c1 0x33>;
+
+ resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie1_switch1_dsp1: pcie@1,0 {
+ reg = <0x40800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie1_switch1_dsp2: pcie@2,0 {
+ reg = <0x41000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie1_switch1_dsp3: pcie@3,0 {
+ reg = <0x41800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+
+ pcie1_switch1_eth0: pci@0,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie1_switch1_eth1: pci@0,1 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
&tlmm {
pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
pins = "gpio78";
@@ -156,4 +241,15 @@ pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
output-enable;
power-source = <0>;
};
+
+ pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
+ pins = "gpio124";
+ function = "gpio";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+
};
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index e3d2f01881ae..ffe4521eb289 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -828,7 +828,7 @@ &pcie1_phy {
};
&pcie1_port0 {
- pcie@0,0 {
+ pcie1_switch0_usp: pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
@@ -852,7 +852,7 @@ pcie@0,0 {
pinctrl-0 = <&tc9563_resx_n>;
pinctrl-names = "default";
- pcie@1,0 {
+ pcie1_switch0_dsp1: pcie@1,0 {
reg = <0x20800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -862,7 +862,7 @@ pcie@1,0 {
bus-range = <0x3 0xff>;
};
- pcie@2,0 {
+ pcie1_switch0_dsp2: pcie@2,0 {
reg = <0x21000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -872,7 +872,7 @@ pcie@2,0 {
bus-range = <0x4 0xff>;
};
- pcie@3,0 {
+ pcie1_switch0_dsp3: pcie@3,0 {
reg = <0x21800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -880,7 +880,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
- pci@0,0 {
+ pcie1_switch0_eth0: pci@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -888,7 +888,7 @@ pci@0,0 {
ranges;
};
- pci@0,1 {
+ pcie1_switch0_eth1: pci@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
2026-02-03 4:31 ` [PATCH v2 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Sushrut Shree Trivedi
@ 2026-02-03 9:21 ` Konrad Dybcio
0 siblings, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2026-02-03 9:21 UTC (permalink / raw)
To: Sushrut Shree Trivedi, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 2/3/26 5:31 AM, Sushrut Shree Trivedi wrote:
> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
> in cascade to the first TC9563 switch via the former's downstream port.
>
> Two embedded Ethernet devices are present on one of the downstream
> ports of this second switch as well. All the ports present in the
> node represent the downstream ports and embedded endpoints.
>
> The second TC9563 is powered up via the same LDO regulators as the first
> one, and these can be controlled via two GPIOs, which are already present
> as fixed regulators. This TC9563 can also be configured through I2C.
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
> .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 96 ++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +--
> 2 files changed, 102 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> index 89bbcab0908d..1744c9c8bd50 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> @@ -146,6 +146,91 @@ pcie0_switch0_eth1: pci@0,1 {
> };
> };
>
> +&pcie1 {
> + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
> + <0x100 &apps_smmu 0x1c81 0x1>,
Please set your tab width to 8 and align the '<'s
[...]
> +&pcie1_switch0_dsp1 {
> + pcie1_switch1_usp: pcie@0,0 {
This label is unused
[...]
> + pcie1_switch1_dsp1: pcie@1,0 {
> + reg = <0x40800 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + };
> +
> + pcie1_switch1_dsp2: pcie@2,0 {
> + reg = <0x41000 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + };
> +
> + pcie1_switch1_dsp3: pcie@3,0 {
And so are all three of these
> + reg = <0x41800 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges;
> +
> + pcie1_switch1_eth0: pci@0,0 {
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges;
> + };
> +
> + pcie1_switch1_eth1: pci@0,1 {
These two are unused as well
[...]
> + pcie1_switch0_dsp1: pcie@1,0 {
This one is in use
> reg = <0x20800 0x0 0x0 0x0 0x0>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -862,7 +862,7 @@ pcie@1,0 {
> bus-range = <0x3 0xff>;
> };
>
> - pcie@2,0 {
> + pcie1_switch0_dsp2: pcie@2,0 {
> reg = <0x21000 0x0 0x0 0x0 0x0>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -872,7 +872,7 @@ pcie@2,0 {
> bus-range = <0x4 0xff>;
> };
>
> - pcie@3,0 {
> + pcie1_switch0_dsp3: pcie@3,0 {
But these two aren't. Plus the DSP3 seems to be hardwired to eth
so it seems like that won't ever change. DSP2 will understandably
be useful, since any derivative of this mezz could attach more
devices
> reg = <0x21800 0x0 0x0 0x0 0x0>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -880,7 +880,7 @@ pcie@3,0 {
> ranges;
> bus-range = <0x5 0xff>;
>
> - pci@0,0 {
> + pcie1_switch0_eth0: pci@0,0 {
> reg = <0x50000 0x0 0x0 0x0 0x0>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -888,7 +888,7 @@ pci@0,0 {
> ranges;
> };
>
> - pci@0,1 {
> + pcie1_switch0_eth1: pci@0,1 {
These two are again unused
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes
2026-02-03 4:31 [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
2026-02-03 4:31 ` [PATCH v2 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Sushrut Shree Trivedi
2026-02-03 4:31 ` [PATCH v2 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Sushrut Shree Trivedi
@ 2026-02-03 4:37 ` Sushrut Shree Trivedi
2026-02-03 8:48 ` Konrad Dybcio
2026-02-03 17:37 ` Rob Herring
2026-02-03 18:06 ` Dmitry Baryshkov
4 siblings, 1 reply; 10+ messages in thread
From: Sushrut Shree Trivedi @ 2026-02-03 4:37 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
Hi,
Apologies for the error, this is v1 series.
Thanks
On 2/3/2026 10:01 AM, Sushrut Shree Trivedi wrote:
> Add nodes for the two additional TC9563 PCIe switches present on the
> QCOM RB3Gen2 Industrial Mezzanine platform.
>
> One of the TC9563 is connected directly to the PCIe0 root-port while
> the second TC9563 switch is connected in cascade fashion to another
> already available TC9563 switch on PCIe1 via the former's downstream
> port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
> would look something like below:
>
> ┌────────────────────────────┐
> │ │
> │ │
> │ │
> │ SoC │
> │ │
> │ PCIe0 PCIe1 │
> │ ┌───┐ ┌───┐ │
> └────└─┬─┘───────────└─┬─┘───┘
> │ │
> │ │
> │ │
> ┌────────────────┘ └────────────────┐
> │ │
> │ │
> │ │
> ┌────────┴─────────┐ ┌──────────┴───────┐
> │ USP │ │ USP │
> │ │ │ │
> │ TC9563 │ │ TC9563 │
> │ │ │ │
> │ │ │ │
> │ DSP1 DSP2 DSP3 │ │ DSP1 DSP2 DSP3 │
> └──┬──────┬─────┬──┘ └───┬─────┬─────┬──┘
> │ │ │ │ │ │
> │ │ │ │ │ │
> │ │ │ │ │ │
> │ │ │ │ EP ETHERNET
> │ │ │ │
> │ │ │ └──────┐
> EP EP ETHERNET │
> │
> │
> ┌─────────┴────────┐
> │ USP │
> │ │
> │ TC9563 │
> │ │
> │ │
> │ DSP1 DSP2 DSP3 │
> └──┬──────┬─────┬──┘
> │ │ │
> │ │ │
> │ │ │
> │ │ │
> │ │ │
> EP EP ETHERNET
>
>
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
> Changes in v2:
> - EDITME: describe what is new in this series revision.
> - EDITME: use bulletpoints and terse descriptions.
> - Link to v1: https://lore.kernel.org/r/20260131-industrial-mezzanine-pcie-v1-0-b3c2905dd768@oss.qualcomm.com
>
> ---
> Sushrut Shree Trivedi (2):
> arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
> arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
>
> .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 234 +++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +-
> 2 files changed, 240 insertions(+), 6 deletions(-)
> ---
> base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
> change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04
>
> Best regards,
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes
2026-02-03 4:37 ` [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
@ 2026-02-03 8:48 ` Konrad Dybcio
0 siblings, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2026-02-03 8:48 UTC (permalink / raw)
To: Sushrut Shree Trivedi, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 2/3/26 5:37 AM, Sushrut Shree Trivedi wrote:
> Hi,
>
> Apologies for the error, this is v1 series.
Please make sure to send the next revision as v3, so that the tools
don't get confused by seeing two 'v2's
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes
2026-02-03 4:31 [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
` (2 preceding siblings ...)
2026-02-03 4:37 ` [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
@ 2026-02-03 17:37 ` Rob Herring
2026-02-03 18:06 ` Dmitry Baryshkov
4 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2026-02-03 17:37 UTC (permalink / raw)
To: Sushrut Shree Trivedi
Cc: devicetree, Konrad Dybcio, linux-arm-msm, Bjorn Andersson,
linux-kernel, Conor Dooley, Krzysztof Kozlowski
On Tue, 03 Feb 2026 10:01:27 +0530, Sushrut Shree Trivedi wrote:
> Add nodes for the two additional TC9563 PCIe switches present on the
> QCOM RB3Gen2 Industrial Mezzanine platform.
>
> One of the TC9563 is connected directly to the PCIe0 root-port while
> the second TC9563 switch is connected in cascade fashion to another
> already available TC9563 switch on PCIe1 via the former's downstream
> port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
> would look something like below:
>
> ┌────────────────────────────┐
> │ │
> │ │
> │ │
> │ SoC │
> │ │
> │ PCIe0 PCIe1 │
> │ ┌───┐ ┌───┐ │
> └────└─┬─┘───────────└─┬─┘───┘
> │ │
> │ │
> │ │
> ┌────────────────┘ └────────────────┐
> │ │
> │ │
> │ │
> ┌────────┴─────────┐ ┌──────────┴───────┐
> │ USP │ │ USP │
> │ │ │ │
> │ TC9563 │ │ TC9563 │
> │ │ │ │
> │ │ │ │
> │ DSP1 DSP2 DSP3 │ │ DSP1 DSP2 DSP3 │
> └──┬──────┬─────┬──┘ └───┬─────┬─────┬──┘
> │ │ │ │ │ │
> │ │ │ │ │ │
> │ │ │ │ │ │
> │ │ │ │ EP ETHERNET
> │ │ │ │
> │ │ │ └──────┐
> EP EP ETHERNET │
> │
> │
> ┌─────────┴────────┐
> │ USP │
> │ │
> │ TC9563 │
> │ │
> │ │
> │ DSP1 DSP2 DSP3 │
> └──┬──────┬─────┬──┘
> │ │ │
> │ │ │
> │ │ │
> │ │ │
> │ │ │
> EP EP ETHERNET
>
>
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
> Changes in v2:
> - EDITME: describe what is new in this series revision.
> - EDITME: use bulletpoints and terse descriptions.
> - Link to v1: https://lore.kernel.org/r/20260131-industrial-mezzanine-pcie-v1-0-b3c2905dd768@oss.qualcomm.com
>
> ---
> Sushrut Shree Trivedi (2):
> arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
> arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
>
> .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 234 +++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +-
> 2 files changed, 240 insertions(+), 6 deletions(-)
> ---
> base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
> change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04
>
> Best regards,
> --
> Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>
>
>
My bot found DTB warnings on the .dts/.dtsi files added or changed in
this series.
Some warnings may be existing warnings. Consider fixing existing
warnings before adding new features.
Perhaps the warnings are fixed by another series. If that is the case,
please set the base commit and any dependencies for the series using
"b4".
Ultimately, it is up to the platform maintainer whether these warnings
are acceptable or not.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: 4f938c7d3b25d87b356af4106c2682caf8c835a2 (use --merge-base to override)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com:
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:86.3-35: Warning (reg_format): /fragment@4/__overlay__/pcie@0,0:reg: property has invalid length (20 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:171.3-35: Warning (reg_format): /fragment@6/__overlay__/pcie@0,0:reg: property has invalid length (20 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:91.3-10: Warning (ranges_format): /fragment@4/__overlay__/pcie@0,0:ranges: empty "ranges" property but its #address-cells (3) differs from /fragment@4/__overlay__ (2)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:91.3-10: Warning (ranges_format): /fragment@4/__overlay__/pcie@0,0:ranges: empty "ranges" property but its #size-cells (2) differs from /fragment@4/__overlay__ (1)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:176.3-10: Warning (ranges_format): /fragment@6/__overlay__/pcie@0,0:ranges: empty "ranges" property but its #address-cells (3) differs from /fragment@6/__overlay__ (2)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:176.3-10: Warning (ranges_format): /fragment@6/__overlay__/pcie@0,0:ranges: empty "ranges" property but its #size-cells (2) differs from /fragment@6/__overlay__ (1)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtbo: Warning (pci_device_reg): Failed prerequisite 'reg_format'
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtbo: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtbo: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtbo: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:84.30-146.4: Warning (avoid_default_addr_size): /fragment@4/__overlay__/pcie@0,0: Relying on default #address-cells value
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:84.30-146.4: Warning (avoid_default_addr_size): /fragment@4/__overlay__/pcie@0,0: Relying on default #size-cells value
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:169.30-231.4: Warning (avoid_default_addr_size): /fragment@6/__overlay__/pcie@0,0: Relying on default #address-cells value
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso:169.30-231.4: Warning (avoid_default_addr_size): /fragment@6/__overlay__/pcie@0,0: Relying on default #size-cells value
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dtb: pmic@2 (qcom,pm8350c): pwm:nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dtb: pwm (qcom,pm8350c-pwm): nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0:pci@0,1: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0:pci@0,0: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'device_type', 'pci@0,0', 'pci@0,1', 'ranges', 'reg' were unexpected)
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@3,0: pci@0,1: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@3,0: pci@0,0: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0:pci@0,1: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0:pci@0,0: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@0,0 (pci1179,0623): pcie@3,0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'device_type', 'pci@0,0', 'pci@0,1', 'ranges', 'reg' were unexpected)
from schema $id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@3,0: pci@0,1: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pcie@3,0: pci@0,0: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pmic@2 (qcom,pm8350c): pwm:nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtb: pwm (qcom,pm8350c-pwm): nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtb: pmic@2 (qcom,pm8350c): pwm:nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtb: pwm (qcom,pm8350c-pwm): nvmem: [[390, 391]] is too short
from schema $id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes
2026-02-03 4:31 [PATCH v2 0/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch nodes Sushrut Shree Trivedi
` (3 preceding siblings ...)
2026-02-03 17:37 ` Rob Herring
@ 2026-02-03 18:06 ` Dmitry Baryshkov
4 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-02-03 18:06 UTC (permalink / raw)
To: Sushrut Shree Trivedi
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Tue, Feb 03, 2026 at 10:01:27AM +0530, Sushrut Shree Trivedi wrote:
> Add nodes for the two additional TC9563 PCIe switches present on the
> QCOM RB3Gen2 Industrial Mezzanine platform.
>
> One of the TC9563 is connected directly to the PCIe0 root-port while
> the second TC9563 switch is connected in cascade fashion to another
> already available TC9563 switch on PCIe1 via the former's downstream
> port (DSP). The final PCIe hierarchy on the Industrial Mezz platform
> would look something like below:
>
> ---
> Changes in v2:
> - EDITME: describe what is new in this series revision.
> - EDITME: use bulletpoints and terse descriptions.
The b4 tool should have warned you about this. Why was it ignored? Where
is the changelog?
> - Link to v1: https://lore.kernel.org/r/20260131-industrial-mezzanine-pcie-v1-0-b3c2905dd768@oss.qualcomm.com
>
> ---
> Sushrut Shree Trivedi (2):
> arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
> arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
>
> .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 234 +++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +-
> 2 files changed, 240 insertions(+), 6 deletions(-)
> ---
> base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
> change-id: 20260131-industrial-mezzanine-pcie-75dd851f5b04
>
> Best regards,
> --
> Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 10+ messages in thread