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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <helgaas@kernel.org>,
	Niklas Cassel <niklas.cassel@axis.com>
Cc: Niklas Cassel <niklass@axis.com>,
	Jesper Nilsson <jespern@axis.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Xiaowei Song <songxiaowei@hisilicon.com>,
	Peter Robinson <pbrobinson@gmail.com>,
	Tomasz Nowicki <tn@semihalf.com>,
	Gabriele Paoloni <gabriele.paoloni@huawei.com>,
	Duc Dang <dhdang@apm.com>, <linux-arm-kernel@axis.com>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 08/10] PCI: dwc: artpec6: add support for endpoint mode
Date: Wed, 18 Oct 2017 13:33:49 +0530	[thread overview]
Message-ID: <ebc64a29-4080-af88-c774-b3223115aef0@ti.com> (raw)
In-Reply-To: <20171016234326.GM25517@bhelgaas-glaptop.roam.corp.google.com>

Hi Bjorn,

On Tuesday 17 October 2017 05:13 AM, Bjorn Helgaas wrote:
> On Fri, Oct 13, 2017 at 06:09:11PM +0200, Niklas Cassel wrote:
>> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
>> ---
>>  .../devicetree/bindings/pci/axis,artpec6-pcie.txt  |   3 +-
>>  drivers/pci/dwc/Kconfig                            |  41 +++--
>>  drivers/pci/dwc/Makefile                           |   4 +-
>>  drivers/pci/dwc/pcie-artpec6.c                     | 202 ++++++++++++++++++++-
>>  4 files changed, 233 insertions(+), 17 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
>> index 4e4aee4439ea..33eef7ae5a23 100644
>> --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
>> +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
>> @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP
>>  and thus inherits all the common properties defined in designware-pcie.txt.
>>  
>>  Required properties:
>> -- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
>> +- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
>> +	      "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
>>  - reg: base addresses and lengths of the PCIe controller (DBI),
>>  	the PHY controller, and configuration address space.
>>  - reg-names: Must include the following entries:
>> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
>> index 22ec82fcdea2..e333283fb1ed 100644
>> --- a/drivers/pci/dwc/Kconfig
>> +++ b/drivers/pci/dwc/Kconfig
>> @@ -14,6 +14,36 @@ config PCIE_DW_EP
>>  	depends on PCI_ENDPOINT
>>  	select PCIE_DW
>>  
>> +config PCIE_ARTPEC6
>> +	bool "Axis ARTPEC-6 PCIe controller"
>> +	depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT
>> +	depends on MACH_ARTPEC6
>> +	help
>> +	  Say Y here to enable PCIe controller support on Axis ARTPEC-6
>> +	  SoCs.  This PCIe controller uses the DesignWare core.
>> +
>> +if PCIE_ARTPEC6
>> +
>> +config PCIE_ARTPEC6_HOST
>> +	bool "Axis ARTPEC-6 Host Mode"
>> +	depends on PCI
>> +	depends on PCI_MSI_IRQ_DOMAIN
>> +	select PCIEPORTBUS
>> +	select PCIE_DW_HOST
>> +	help
>> +	  Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
>> +	  host mode.
>> +
>> +config PCIE_ARTPEC6_EP
>> +	bool "Axis ARTPEC-6 Endpoint Mode"
>> +	depends on PCI_ENDPOINT
>> +	select PCIE_DW_EP
>> +	help
>> +	  Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
>> +	  endpoint mode.
>> +
>> +endif
>> +
>>  config PCI_DRA7XX
>>  	bool "TI DRA7xx PCIe controller"
>>  	depends on SOC_DRA7XX || COMPILE_TEST
>> @@ -148,17 +178,6 @@ config PCIE_ARMADA_8K
>>  	  DesignWare hardware and therefore the driver re-uses the
>>  	  DesignWare core functions to implement the driver.
>>  
>> -config PCIE_ARTPEC6
>> -	bool "Axis ARTPEC-6 PCIe controller"
>> -	depends on PCI
>> -	depends on MACH_ARTPEC6
>> -	depends on PCI_MSI_IRQ_DOMAIN
>> -	select PCIEPORTBUS
>> -	select PCIE_DW_HOST
>> -	help
>> -	  Say Y here to enable PCIe controller support on Axis ARTPEC-6
>> -	  SoCs.  This PCIe controller uses the DesignWare core.
>> -
>>  config PCIE_KIRIN
>>  	depends on OF && ARM64
>>  	bool "HiSilicon Kirin series SoCs PCIe controllers"
> 
>> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
>> index c61be9738cce..ac98242b83a9 100644
>> --- a/drivers/pci/dwc/Makefile
>> +++ b/drivers/pci/dwc/Makefile
>> @@ -2,6 +2,9 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
>>  obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>> +ifneq ($(filter y,$(CONFIG_PCIE_ARTPEC6_HOST) $(CONFIG_PCIE_ARTPEC6_EP)),)
>> +        obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
>> +endif
> 
> I see you're copying the DRA7XX style here, but I don't really
> understand it.  I guess the idea is to build pcie-artpec6.o if either
> CONFIG_PCIE_ARTPEC6_HOST or CONFIG_PCIE_ARTPEC6_EP is set (or both).
> 
> Is this really the simplest way to express that in Kconfig?  Both the
> "if PCIE_ARTPEC6" and this ifneq thing are complicated and relatively
> unusual.
> 
>>  ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)
>>          obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>>  endif
> 
>> +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> 
> Looks funny to have this dw_*() function in pcie-artpec6.c.  Intended?
> Or is this something other endpoint drivers could/should share?

yeah, dw_pcie_ep_reset_bar is already present in pcie-designware-ep.c which
should be made as library function to be used by other drivers. (pci-dra7xx.c
has also added something like above which should also be fixed).

Thanks
Kishon

  reply	other threads:[~2017-10-18  8:04 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-13 16:09 [PATCH 00/10] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Niklas Cassel
2017-10-13 16:09 ` [PATCH 01/10] PCI: dwc: use DMA-API for allocating MSI data Niklas Cassel
2017-10-13 16:42   ` David Laight
2017-10-16 11:43     ` Niklas Cassel
2017-10-13 16:43   ` Jingoo Han
2017-10-16 12:08     ` Niklas Cassel
2017-10-13 16:47   ` Jingoo Han
2017-10-16 12:11     ` Niklas Cassel
2017-10-16 22:16   ` Bjorn Helgaas
2017-10-13 16:09 ` [PATCH 02/10] PCI: designware-ep: set_msi should only set MMC bits Niklas Cassel
2017-10-16 22:26   ` Bjorn Helgaas
2017-10-13 16:09 ` [PATCH 03/10] PCI: designware-ep: read-only registers need DBI_RO_WR_EN to be writable Niklas Cassel
2017-10-13 16:09 ` [PATCH 04/10] PCI: designware-ep: pre-allocate memory for MSI in dw_pcie_ep_init Niklas Cassel
2017-10-13 16:09 ` [PATCH 05/10] PCI: artpec6: remove unused defines Niklas Cassel
2017-10-13 16:09 ` [PATCH 06/10] PCI: dwc: artpec6: use BIT and GENMASK macros Niklas Cassel
2017-10-13 16:09 ` [PATCH 07/10] PCI: dwc: artpec6: split artpec6_pcie_establish_link to smaller functions Niklas Cassel
2017-10-13 16:09 ` [PATCH 08/10] PCI: dwc: artpec6: add support for endpoint mode Niklas Cassel
2017-10-16 23:43   ` Bjorn Helgaas
2017-10-18  8:03     ` Kishon Vijay Abraham I [this message]
2017-10-18  8:15       ` Niklas Cassel
2017-10-18  8:47         ` Kishon Vijay Abraham I
2017-10-19  7:59     ` Christoph Hellwig
2017-10-19 10:57       ` Niklas Cassel
2017-10-19 11:40     ` Niklas Cassel
2017-10-17 22:24   ` Rob Herring
2017-10-18  8:46   ` Kishon Vijay Abraham I
2017-10-20 10:48     ` Niklas Cassel
2017-10-13 16:09 ` [PATCH 09/10] PCI: dwc: make cpu_addr_fixup take struct dw_pcie as argument Niklas Cassel
2017-10-16 12:40   ` Niklas Cassel
2017-10-13 16:09 ` [PATCH 10/10] PCI: dwc: artpec6: add support for the ARTPEC-7 SoC Niklas Cassel
2017-10-17 22:25   ` Rob Herring

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