* [PATCH] MIPS: SiByte: Add missing sb1_cache_error() prototype
@ 2026-11-10 22:36 Florian Fainelli
2026-11-12 19:21 ` Florian Fainelli
0 siblings, 1 reply; 2+ messages in thread
From: Florian Fainelli @ 2026-11-10 22:36 UTC (permalink / raw)
To: linux-mips; +Cc: macro, Florian Fainelli, Thomas Bogendoerfer, open list
Fixes the following warning:
arch/mips/mm/cerr-sb1.c:165:17: warning: no previous prototype for ‘sb1_cache_error’ [-Wmissing-prototypes]
165 | asmlinkage void sb1_cache_error(void)
| ^~~~~~~~~~~~~~~
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/mips/include/asm/sibyte/sb1250.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h
index de4b352256c8..e42b3c9f4b53 100644
--- a/arch/mips/include/asm/sibyte/sb1250.h
+++ b/arch/mips/include/asm/sibyte/sb1250.h
@@ -32,6 +32,8 @@ extern unsigned int soc_type;
extern unsigned int periph_rev;
extern unsigned int zbbus_mhz;
+void sb1_cache_error(void);
+
extern void sb1250_mask_irq(int cpu, int irq);
extern void sb1250_unmask_irq(int cpu, int irq);
--
2.53.0
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] MIPS: SiByte: Add missing sb1_cache_error() prototype
2026-11-10 22:36 [PATCH] MIPS: SiByte: Add missing sb1_cache_error() prototype Florian Fainelli
@ 2026-11-12 19:21 ` Florian Fainelli
0 siblings, 0 replies; 2+ messages in thread
From: Florian Fainelli @ 2026-11-12 19:21 UTC (permalink / raw)
To: linux-mips; +Cc: macro, Thomas Bogendoerfer, open list
On 11/10/26 14:36, Florian Fainelli wrote:
> Fixes the following warning:
>
> arch/mips/mm/cerr-sb1.c:165:17: warning: no previous prototype for ‘sb1_cache_error’ [-Wmissing-prototypes]
> 165 | asmlinkage void sb1_cache_error(void)
> | ^~~~~~~~~~~~~~~
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
There are many more, let me squash them all and resubmit.
--
Florian
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2026-11-10 22:36 [PATCH] MIPS: SiByte: Add missing sb1_cache_error() prototype Florian Fainelli
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