mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: mlevitsk@redhat.com
To: Paolo Bonzini <pbonzini@redhat.com>,
	linux-kernel@vger.kernel.org,  kvm@vger.kernel.org
Cc: d.riley@proxmox.com, jon@nutanix.com
Subject: Re: [PATCH 10/28] KVM: x86/mmu: pass PFERR_GUEST_PAGE/FINAL_MASK to kvm_translate_gpa
Date: Tue, 02 Jun 2026 10:23:33 -0400	[thread overview]
Message-ID: <1fa043a5573867db87ed572ae373330c5cfa3974.camel@redhat.com> (raw)
In-Reply-To: <20260505195226.563317-11-pbonzini@redhat.com>

On Tue, 2026-05-05 at 21:52 +0200, Paolo Bonzini wrote:
> The XS/XU bit for EPT are only applied to final accesses, and use the
> U bit from the page walk itself.  While strictly speaking not necessary
> (any value of PFERR_USER_MASK would be the same for page table accesses,
> because they're reads and writes only), it is clearer and less hackish
> to only apply MBEC to PFERR_GUEST_FINAL_MASK.  Allow kvm-intel.ko to
> distinguish the two cases.
> 
> Tested-by: David Riley <d.riley@proxmox.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  arch/x86/kvm/hyperv.c          | 3 ++-
>  arch/x86/kvm/mmu/mmu.c         | 3 ++-
>  arch/x86/kvm/mmu/paging_tmpl.h | 7 +++++--
>  arch/x86/kvm/x86.c             | 3 ++-
>  4 files changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
> index 9b140bbdc1d8..cf9dd565b894 100644
> --- a/arch/x86/kvm/hyperv.c
> +++ b/arch/x86/kvm/hyperv.c
> @@ -2041,7 +2041,8 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc)
>   * read with kvm_read_guest().
>   */
>   if (!hc->fast && is_guest_mode(vcpu)) {
> - hc->ingpa = translate_nested_gpa(vcpu, hc->ingpa, 0, NULL);
> + hc->ingpa = translate_nested_gpa(vcpu, hc->ingpa,
> + PFERR_GUEST_FINAL_MASK, NULL);
>   if (unlikely(hc->ingpa == INVALID_GPA))
>   return HV_STATUS_INVALID_HYPERCALL_INPUT;
>   }
> diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> index fa6a5e4ee09a..46412e4d207f 100644
> --- a/arch/x86/kvm/mmu/mmu.c
> +++ b/arch/x86/kvm/mmu/mmu.c
> @@ -4348,7 +4348,8 @@ static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
>  {
>   if (exception)
>   exception->error_code = 0;
> - return kvm_translate_gpa(vcpu, mmu, vaddr, access, exception);
> + return kvm_translate_gpa(vcpu, mmu, vaddr, access | PFERR_GUEST_FINAL_MASK,
> + exception);


This is an existing problem, but now that I look at this and at the next patch, it is not
100% clear what 'access' is, especially for someone who is not familiar with he code.

Also soon we will have 'pte_access', which can make this problem worse.

I think that there is a need for a comment here, in this or in the next patch to avoid
a confusion.
What do you think?

>  }
>  
>  static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
> diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmpl.h
> index fb1b5d8b23e5..567f8b77ffe0 100644
> --- a/arch/x86/kvm/mmu/paging_tmpl.h
> +++ b/arch/x86/kvm/mmu/paging_tmpl.h
> @@ -376,7 +376,8 @@ static int FNAME(walk_addr_generic)(struct guest_walker *walker,
>   walker->pte_gpa[walker->level - 1] = pte_gpa;
>  
>   real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(table_gfn),
> -      nested_access, &walker->fault);
> +      nested_access | PFERR_GUEST_PAGE_MASK,
> +      &walker->fault);
>  
>   /*
>   * FIXME: This can happen if emulation (for of an INS/OUTS
> @@ -444,7 +445,9 @@ static int FNAME(walk_addr_generic)(struct guest_walker *walker,
>   gfn += pse36_gfn_delta(pte);
>  #endif
>  
> - real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(gfn), access, &walker->fault);
> + real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(gfn),
> +      access | PFERR_GUEST_FINAL_MASK,
> +      &walker->fault);
>   if (real_gpa == INVALID_GPA)
>   return 0;
>  
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 0a1b63c63d1a..ef1e3ae13887 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -1072,7 +1072,8 @@ int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
>   * to an L1 GPA.
>   */
>   real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
> -      PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
> +      PFERR_USER_MASK | PFERR_WRITE_MASK |
> +      PFERR_GUEST_PAGE_MASK, NULL);
>   if (real_gpa == INVALID_GPA)
>   return 0;
>  

Looks correct to me otherwise.

Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Best regards,
	Maxim Levitsky



  reply	other threads:[~2026-06-02 14:23 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-05 19:51 [PATCH v6 00/28] KVM: combined patchset for MBEC/GMET support Paolo Bonzini
2026-05-05 19:51 ` [PATCH 01/28] KVM: TDX/VMX: rework EPT_VIOLATION_EXEC_FOR_RING3_LIN into PROT_MASK Paolo Bonzini
2026-06-02 14:19   ` mlevitsk
2026-05-05 19:52 ` [PATCH 02/28] KVM: x86/mmu: remove SPTE_PERM_MASK Paolo Bonzini
2026-06-02 14:20   ` mlevitsk
2026-05-05 19:52 ` [PATCH 03/28] KVM: x86/mmu: free up bit 10 of PTEs in preparation for MBEC Paolo Bonzini
2026-06-02 14:20   ` mlevitsk
2026-05-05 19:52 ` [PATCH 04/28] KVM: x86/mmu: shuffle high bits of SPTEs " Paolo Bonzini
2026-06-02 14:20   ` mlevitsk
2026-05-05 19:52 ` [PATCH 05/28] KVM: x86/mmu: remove SPTE_EPT_* Paolo Bonzini
2026-06-02 14:21   ` mlevitsk
2026-05-05 19:52 ` [PATCH 06/28] KVM: x86/mmu: merge make_spte_{non,}executable Paolo Bonzini
2026-06-02 14:22   ` mlevitsk
2026-05-05 19:52 ` [PATCH 07/28] KVM: x86/mmu: rename and clarify BYTE_MASK Paolo Bonzini
2026-06-02 14:22   ` mlevitsk
2026-05-05 19:52 ` [PATCH 08/28] KVM: x86/mmu: separate more EPT/non-EPT permission_fault() Paolo Bonzini
2026-05-07 14:35   ` Sean Christopherson
2026-06-02 14:22   ` mlevitsk
2026-05-05 19:52 ` [PATCH 09/28] KVM: x86/mmu: introduce ACC_READ_MASK Paolo Bonzini
2026-06-02 14:23   ` mlevitsk
2026-05-05 19:52 ` [PATCH 10/28] KVM: x86/mmu: pass PFERR_GUEST_PAGE/FINAL_MASK to kvm_translate_gpa Paolo Bonzini
2026-06-02 14:23   ` mlevitsk [this message]
2026-05-05 19:52 ` [PATCH 11/28] KVM: x86/mmu: pass pte_access for final nGPA->GPA walk Paolo Bonzini
2026-06-02 14:24   ` mlevitsk
2026-05-05 19:52 ` [PATCH 12/28] KVM: x86: make translate_nested_gpa vendor-specific Paolo Bonzini
2026-06-02 14:24   ` mlevitsk
2026-05-05 19:52 ` [PATCH 13/28] KVM: x86/mmu: split XS/XU bits for EPT Paolo Bonzini
2026-06-02 14:24   ` mlevitsk
2026-05-05 19:52 ` [PATCH 14/28] KVM: x86/mmu: move cr4_smep to base role Paolo Bonzini
2026-06-02 14:25   ` mlevitsk
2026-05-05 19:52 ` [PATCH 15/28] KVM: VMX: enable use of MBEC Paolo Bonzini
2026-05-07 14:40   ` Sean Christopherson
2026-06-02 14:26   ` mlevitsk
2026-05-05 19:52 ` [PATCH 16/28] KVM: nVMX: pass advanced EPT violation vmexit info to guest Paolo Bonzini
2026-06-02 14:26   ` mlevitsk
2026-05-05 19:52 ` [PATCH 17/28] KVM: nVMX: pass PFERR_USER_MASK to MMU on EPT violations Paolo Bonzini
2026-06-02 14:27   ` mlevitsk
2026-05-05 19:52 ` [PATCH 18/28] KVM: x86/mmu: add support for MBEC to EPT page table walks Paolo Bonzini
2026-06-02 14:28   ` mlevitsk
2026-05-05 19:52 ` [PATCH 19/28] KVM: nVMX: advertise MBEC to nested guests Paolo Bonzini
2026-06-02 14:28   ` mlevitsk
2026-05-05 19:52 ` [PATCH 20/28] KVM: nVMX: allow MBEC with EVMCS Paolo Bonzini
2026-06-02 14:28   ` mlevitsk
2026-06-02 15:29     ` Vitaly Kuznetsov
2026-05-05 19:52 ` [PATCH 21/28] KVM: x86/mmu: propagate access mask from root pages down Paolo Bonzini
2026-06-02 14:29   ` mlevitsk
2026-05-05 19:52 ` [PATCH 22/28] KVM: x86/mmu: introduce cpu_role bit for availability of PFEC.I/D Paolo Bonzini
2026-06-02 14:29   ` mlevitsk
2026-05-05 19:52 ` [PATCH 23/28] KVM: SVM: add GMET bit definitions Paolo Bonzini
2026-06-02 14:30   ` mlevitsk
2026-05-05 19:52 ` [PATCH 24/28] KVM: x86/mmu: hard code more bits in kvm_init_shadow_npt_mmu Paolo Bonzini
2026-06-02 14:30   ` mlevitsk
2026-05-05 19:52 ` [PATCH 25/28] KVM: x86/mmu: add support for GMET to NPT page table walks Paolo Bonzini
2026-06-02 14:31   ` mlevitsk
2026-05-05 19:52 ` [PATCH 26/28] KVM: SVM: enable GMET and set it in MMU role Paolo Bonzini
2026-06-02 14:31   ` mlevitsk
2026-05-05 19:52 ` [PATCH 27/28] KVM: SVM: work around errata 1218 Paolo Bonzini
2026-06-02 14:31   ` mlevitsk
2026-05-05 19:52 ` [PATCH 28/28] KVM: nSVM: enable GMET for guests Paolo Bonzini
2026-06-02 14:32   ` mlevitsk
2026-05-07 14:44 ` [PATCH v6 00/28] KVM: combined patchset for MBEC/GMET support Sean Christopherson
2026-05-07 17:49   ` Paolo Bonzini
2026-05-11 10:53 ` David Riley
2026-05-11 10:55   ` Paolo Bonzini
2026-05-11 11:07     ` David Riley
2026-05-14  2:11       ` Chao Gao
2026-05-14 19:13         ` Sean Christopherson
2026-05-12 14:32   ` Paolo Bonzini
2026-05-12 16:34     ` Paolo Bonzini
2026-05-15 14:53     ` David Riley
2026-05-15 18:31       ` Sean Christopherson
2026-05-19  8:02         ` David Riley
2026-08-05 12:35 ` Jonas Theisen
  -- strict thread matches above, loose matches on Subject: below --
2026-04-30 15:07 [PATCH v5 " Paolo Bonzini
2026-04-30 15:07 ` [PATCH 10/28] KVM: x86/mmu: pass PFERR_GUEST_PAGE/FINAL_MASK to kvm_translate_gpa Paolo Bonzini
2026-04-30 18:50   ` Sean Christopherson
2026-05-01  3:52     ` Paolo Bonzini
2026-04-28 11:09 [PATCH v4 00/28] KVM: combined patchset for MBEC/GMET support Paolo Bonzini
2026-04-28 11:09 ` [PATCH 10/28] KVM: x86/mmu: pass PFERR_GUEST_PAGE/FINAL_MASK to kvm_translate_gpa Paolo Bonzini

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1fa043a5573867db87ed572ae373330c5cfa3974.camel@redhat.com \
    --to=mlevitsk@redhat.com \
    --cc=d.riley@proxmox.com \
    --cc=jon@nutanix.com \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=pbonzini@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®