From: mlevitsk@redhat.com
To: Paolo Bonzini <pbonzini@redhat.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc: d.riley@proxmox.com, jon@nutanix.com
Subject: Re: [PATCH 07/28] KVM: x86/mmu: rename and clarify BYTE_MASK
Date: Tue, 02 Jun 2026 10:22:23 -0400 [thread overview]
Message-ID: <663ea0eaab130115fed8d6e06115085b9dabae14.camel@redhat.com> (raw)
In-Reply-To: <20260505195226.563317-8-pbonzini@redhat.com>
On Tue, 2026-05-05 at 21:52 +0200, Paolo Bonzini wrote:
> The BYTE_MASK macro is the central point of the black magic
> in update_permission_bitmask(). Rename it to something
> that relates to how it is used, and add a comment explaining
> how it works.
>
> Using shifts instead of powers of two was actually suggested by
> David Hildenbrand back in 2017 for clarity[1] but I evidently
> forgot his suggestion when applying to kvm.git.
>
> [1] https://lore.kernel.org/kvm/e4b5df86-31ae-2f4e-0666-393753e256df@redhat.com/
>
> Tested-by: David Riley <d.riley@proxmox.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> arch/x86/kvm/mmu/mmu.c | 63 ++++++++++++++++++++++++++++--------------
> 1 file changed, 43 insertions(+), 20 deletions(-)
>
> diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> index 24fbc9ea502a..d94a488db79d 100644
> --- a/arch/x86/kvm/mmu/mmu.c
> +++ b/arch/x86/kvm/mmu/mmu.c
> @@ -5529,31 +5529,55 @@ reset_ept_shadow_zero_bits_mask(struct kvm_mmu *context, bool execonly)
> max_huge_page_level);
> }
>
> -#define BYTE_MASK(access) \
> - ((1 & (access) ? 2 : 0) | \
> - (2 & (access) ? 4 : 0) | \
> - (3 & (access) ? 8 : 0) | \
> - (4 & (access) ? 16 : 0) | \
> - (5 & (access) ? 32 : 0) | \
> - (6 & (access) ? 64 : 0) | \
> - (7 & (access) ? 128 : 0))
> -
> +/*
> + * Build a mask with all combinations of PTE access rights that
> + * include the given access bit. The mask can be queried with
> + * "mask & (1 << access)", where access is a combination of
> + * ACC_* bits.
> + *
> + * By mixing and matching multiple masks returned by ACC_BITS_MASK,
> + * update_permission_bitmask() builds what is effectively a
> + * two-dimensional array of bools. The second dimension is
> + * provided by individual bits of permissions[pfec >> 1], and
> + * logical &, | and ~ operations operate on all the 8 possible
> + * combinations of ACC_* bits.
> + */
> +#define ACC_BITS_MASK(access) \
> + ((1 & (access) ? 1 << 1 : 0) | \
> + (2 & (access) ? 1 << 2 : 0) | \
> + (3 & (access) ? 1 << 3 : 0) | \
> + (4 & (access) ? 1 << 4 : 0) | \
> + (5 & (access) ? 1 << 5 : 0) | \
> + (6 & (access) ? 1 << 6 : 0) | \
> + (7 & (access) ? 1 << 7 : 0))
>
> static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept)
> {
> - unsigned byte;
> + unsigned index;
>
> - const u8 x = BYTE_MASK(ACC_EXEC_MASK);
> - const u8 w = BYTE_MASK(ACC_WRITE_MASK);
> - const u8 u = BYTE_MASK(ACC_USER_MASK);
> + const u8 x = ACC_BITS_MASK(ACC_EXEC_MASK);
> + const u8 w = ACC_BITS_MASK(ACC_WRITE_MASK);
> + const u8 u = ACC_BITS_MASK(ACC_USER_MASK);
>
> bool cr4_smep = is_cr4_smep(mmu);
> bool cr4_smap = is_cr4_smap(mmu);
> bool cr0_wp = is_cr0_wp(mmu);
> bool efer_nx = is_efer_nx(mmu);
>
> - for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
> - unsigned pfec = byte << 1;
> + /*
> + * In hardware, page fault error codes are generated (as the name
> + * suggests) on any kind of page fault. permission_fault() and
> + * paging_tmpl.h already use the same bits after a successful page
> + * table walk, to indicate the kind of access being performed.
> + *
> + * However, PFERR_PRESENT_MASK and PFERR_RSVD_MASK are never set here,
> + * exactly because the page walk is successful. PFERR_PRESENT_MASK is
> + * removed by the shift, while PFERR_RSVD_MASK is repurposed in
> + * permission_fault() to indicate accesses that are *not* subject to
> + * SMAP restrictions.
> + */
> + for (index = 0; index < ARRAY_SIZE(mmu->permissions); ++index) {
> + unsigned pfec = index << 1;
>
> /*
> * Each "*f" variable has a 1 bit for each UWX value
> @@ -5598,16 +5622,15 @@ static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept)
> * - The access is supervisor mode
> * - If implicit supervisor access or X86_EFLAGS_AC is clear
> *
> - * Here, we cover the first four conditions.
> - * The fifth is computed dynamically in permission_fault();
> - * PFERR_RSVD_MASK bit will be set in PFEC if the access is
> - * *not* subject to SMAP restrictions.
> + * Here, we cover the first four conditions. The fifth
> + * is computed dynamically in permission_fault() and
> + * communicated by setting PFERR_RSVD_MASK.
> */
> if (cr4_smap)
> smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
> }
>
> - mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
> + mmu->permissions[index] = ff | uf | wf | smepf | smapf;
> }
> }
>
Thanks a million for demystifying this black magic!
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Best regards,
Maxim Levitsky
next prev parent reply other threads:[~2026-06-02 14:22 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-05 19:51 [PATCH v6 00/28] KVM: combined patchset for MBEC/GMET support Paolo Bonzini
2026-05-05 19:51 ` [PATCH 01/28] KVM: TDX/VMX: rework EPT_VIOLATION_EXEC_FOR_RING3_LIN into PROT_MASK Paolo Bonzini
2026-06-02 14:19 ` mlevitsk
2026-05-05 19:52 ` [PATCH 02/28] KVM: x86/mmu: remove SPTE_PERM_MASK Paolo Bonzini
2026-06-02 14:20 ` mlevitsk
2026-05-05 19:52 ` [PATCH 03/28] KVM: x86/mmu: free up bit 10 of PTEs in preparation for MBEC Paolo Bonzini
2026-06-02 14:20 ` mlevitsk
2026-05-05 19:52 ` [PATCH 04/28] KVM: x86/mmu: shuffle high bits of SPTEs " Paolo Bonzini
2026-06-02 14:20 ` mlevitsk
2026-05-05 19:52 ` [PATCH 05/28] KVM: x86/mmu: remove SPTE_EPT_* Paolo Bonzini
2026-06-02 14:21 ` mlevitsk
2026-05-05 19:52 ` [PATCH 06/28] KVM: x86/mmu: merge make_spte_{non,}executable Paolo Bonzini
2026-06-02 14:22 ` mlevitsk
2026-05-05 19:52 ` [PATCH 07/28] KVM: x86/mmu: rename and clarify BYTE_MASK Paolo Bonzini
2026-06-02 14:22 ` mlevitsk [this message]
2026-05-05 19:52 ` [PATCH 08/28] KVM: x86/mmu: separate more EPT/non-EPT permission_fault() Paolo Bonzini
2026-05-07 14:35 ` Sean Christopherson
2026-06-02 14:22 ` mlevitsk
2026-05-05 19:52 ` [PATCH 09/28] KVM: x86/mmu: introduce ACC_READ_MASK Paolo Bonzini
2026-06-02 14:23 ` mlevitsk
2026-05-05 19:52 ` [PATCH 10/28] KVM: x86/mmu: pass PFERR_GUEST_PAGE/FINAL_MASK to kvm_translate_gpa Paolo Bonzini
2026-06-02 14:23 ` mlevitsk
2026-05-05 19:52 ` [PATCH 11/28] KVM: x86/mmu: pass pte_access for final nGPA->GPA walk Paolo Bonzini
2026-06-02 14:24 ` mlevitsk
2026-05-05 19:52 ` [PATCH 12/28] KVM: x86: make translate_nested_gpa vendor-specific Paolo Bonzini
2026-06-02 14:24 ` mlevitsk
2026-05-05 19:52 ` [PATCH 13/28] KVM: x86/mmu: split XS/XU bits for EPT Paolo Bonzini
2026-06-02 14:24 ` mlevitsk
2026-05-05 19:52 ` [PATCH 14/28] KVM: x86/mmu: move cr4_smep to base role Paolo Bonzini
2026-06-02 14:25 ` mlevitsk
2026-05-05 19:52 ` [PATCH 15/28] KVM: VMX: enable use of MBEC Paolo Bonzini
2026-05-07 14:40 ` Sean Christopherson
2026-06-02 14:26 ` mlevitsk
2026-05-05 19:52 ` [PATCH 16/28] KVM: nVMX: pass advanced EPT violation vmexit info to guest Paolo Bonzini
2026-06-02 14:26 ` mlevitsk
2026-05-05 19:52 ` [PATCH 17/28] KVM: nVMX: pass PFERR_USER_MASK to MMU on EPT violations Paolo Bonzini
2026-06-02 14:27 ` mlevitsk
2026-05-05 19:52 ` [PATCH 18/28] KVM: x86/mmu: add support for MBEC to EPT page table walks Paolo Bonzini
2026-06-02 14:28 ` mlevitsk
2026-05-05 19:52 ` [PATCH 19/28] KVM: nVMX: advertise MBEC to nested guests Paolo Bonzini
2026-06-02 14:28 ` mlevitsk
2026-05-05 19:52 ` [PATCH 20/28] KVM: nVMX: allow MBEC with EVMCS Paolo Bonzini
2026-06-02 14:28 ` mlevitsk
2026-06-02 15:29 ` Vitaly Kuznetsov
2026-05-05 19:52 ` [PATCH 21/28] KVM: x86/mmu: propagate access mask from root pages down Paolo Bonzini
2026-06-02 14:29 ` mlevitsk
2026-05-05 19:52 ` [PATCH 22/28] KVM: x86/mmu: introduce cpu_role bit for availability of PFEC.I/D Paolo Bonzini
2026-06-02 14:29 ` mlevitsk
2026-05-05 19:52 ` [PATCH 23/28] KVM: SVM: add GMET bit definitions Paolo Bonzini
2026-06-02 14:30 ` mlevitsk
2026-05-05 19:52 ` [PATCH 24/28] KVM: x86/mmu: hard code more bits in kvm_init_shadow_npt_mmu Paolo Bonzini
2026-06-02 14:30 ` mlevitsk
2026-05-05 19:52 ` [PATCH 25/28] KVM: x86/mmu: add support for GMET to NPT page table walks Paolo Bonzini
2026-06-02 14:31 ` mlevitsk
2026-05-05 19:52 ` [PATCH 26/28] KVM: SVM: enable GMET and set it in MMU role Paolo Bonzini
2026-06-02 14:31 ` mlevitsk
2026-05-05 19:52 ` [PATCH 27/28] KVM: SVM: work around errata 1218 Paolo Bonzini
2026-06-02 14:31 ` mlevitsk
2026-05-05 19:52 ` [PATCH 28/28] KVM: nSVM: enable GMET for guests Paolo Bonzini
2026-06-02 14:32 ` mlevitsk
2026-05-07 14:44 ` [PATCH v6 00/28] KVM: combined patchset for MBEC/GMET support Sean Christopherson
2026-05-07 17:49 ` Paolo Bonzini
2026-05-11 10:53 ` David Riley
2026-05-11 10:55 ` Paolo Bonzini
2026-05-11 11:07 ` David Riley
2026-05-14 2:11 ` Chao Gao
2026-05-14 19:13 ` Sean Christopherson
2026-05-12 14:32 ` Paolo Bonzini
2026-05-12 16:34 ` Paolo Bonzini
2026-05-15 14:53 ` David Riley
2026-05-15 18:31 ` Sean Christopherson
2026-05-19 8:02 ` David Riley
-- strict thread matches above, loose matches on Subject: below --
2026-04-30 15:07 [PATCH v5 " Paolo Bonzini
2026-04-30 15:07 ` [PATCH 07/28] KVM: x86/mmu: rename and clarify BYTE_MASK Paolo Bonzini
2026-04-30 18:39 ` Sean Christopherson
2026-04-28 11:09 [PATCH v4 00/28] KVM: combined patchset for MBEC/GMET support Paolo Bonzini
2026-04-28 11:09 ` [PATCH 07/28] KVM: x86/mmu: rename and clarify BYTE_MASK Paolo Bonzini
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