* [PATCH v2 1/5] spi: spi-nxp-fspi: extract function nxp_fspi_dll_override()
2025-09-17 7:27 [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR mode support Haibo Chen
@ 2025-09-17 7:27 ` Haibo Chen
2025-09-17 16:24 ` Frank Li
2025-09-17 7:27 ` [PATCH v2 2/5] spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHz Haibo Chen
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Haibo Chen @ 2025-09-17 7:27 UTC (permalink / raw)
To: Han Xu, Yogesh Gaur, Mark Brown, Frank Li
Cc: linux-spi, imx, linux-kernel, Haibo Chen
Extract function nxp_fspi_dll_override(), this is the suggested setting
when clock rate < 100MHz. Just the preparation of supportting DTR mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 848fa9319e36d65e8152931324b8e34eb162f5d3..db4b92490de957580c6298baeb8b68a310c23615 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -674,6 +674,17 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
dev_warn(f->dev, "DLL lock failed, please fix it!\n");
}
+/*
+ * Config the DLL register to default value, enable the target clock delay
+ * line delay cell override mode, and use 1 fixed delay cell in DLL delay
+ * chain, this is the suggested setting when clock rate < 100MHz.
+ */
+static void nxp_fspi_dll_override(struct nxp_fspi *f)
+{
+ fspi_writel(f, FSPI_DLLACR_OVRDEN, f->iobase + FSPI_DLLACR);
+ fspi_writel(f, FSPI_DLLBCR_OVRDEN, f->iobase + FSPI_DLLBCR);
+}
+
/*
* In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
* register and start base address of the target device.
@@ -1071,13 +1082,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
/* Disable the module */
fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
- /*
- * Config the DLL register to default value, enable the target clock delay
- * line delay cell override mode, and use 1 fixed delay cell in DLL delay
- * chain, this is the suggested setting when clock rate < 100MHz.
- */
- fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
- fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
+ nxp_fspi_dll_override(f);
/* enable module */
fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/5] spi: spi-nxp-fspi: extract function nxp_fspi_dll_override()
2025-09-17 7:27 ` [PATCH v2 1/5] spi: spi-nxp-fspi: extract function nxp_fspi_dll_override() Haibo Chen
@ 2025-09-17 16:24 ` Frank Li
0 siblings, 0 replies; 12+ messages in thread
From: Frank Li @ 2025-09-17 16:24 UTC (permalink / raw)
To: Haibo Chen; +Cc: Han Xu, Yogesh Gaur, Mark Brown, linux-spi, imx, linux-kernel
On Wed, Sep 17, 2025 at 03:27:06PM +0800, Haibo Chen wrote:
> Extract function nxp_fspi_dll_override(), this is the suggested setting
> when clock rate < 100MHz. Just the preparation of supportting DTR mode.
Remove "this is the suggested setting when clock rate < 100MHz", which is
not related this patch.
Extract nxp_fspi_dll_override() for preparation of DTR mode support.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
> drivers/spi/spi-nxp-fspi.c | 19 ++++++++++++-------
> 1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> index 848fa9319e36d65e8152931324b8e34eb162f5d3..db4b92490de957580c6298baeb8b68a310c23615 100644
> --- a/drivers/spi/spi-nxp-fspi.c
> +++ b/drivers/spi/spi-nxp-fspi.c
> @@ -674,6 +674,17 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
> dev_warn(f->dev, "DLL lock failed, please fix it!\n");
> }
>
> +/*
> + * Config the DLL register to default value, enable the target clock delay
> + * line delay cell override mode, and use 1 fixed delay cell in DLL delay
> + * chain, this is the suggested setting when clock rate < 100MHz.
> + */
> +static void nxp_fspi_dll_override(struct nxp_fspi *f)
> +{
> + fspi_writel(f, FSPI_DLLACR_OVRDEN, f->iobase + FSPI_DLLACR);
> + fspi_writel(f, FSPI_DLLBCR_OVRDEN, f->iobase + FSPI_DLLBCR);
> +}
> +
> /*
> * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
> * register and start base address of the target device.
> @@ -1071,13 +1082,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
> /* Disable the module */
> fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
>
> - /*
> - * Config the DLL register to default value, enable the target clock delay
> - * line delay cell override mode, and use 1 fixed delay cell in DLL delay
> - * chain, this is the suggested setting when clock rate < 100MHz.
> - */
> - fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
> - fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
> + nxp_fspi_dll_override(f);
>
> /* enable module */
> fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/5] spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHz
2025-09-17 7:27 [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR mode support Haibo Chen
2025-09-17 7:27 ` [PATCH v2 1/5] spi: spi-nxp-fspi: extract function nxp_fspi_dll_override() Haibo Chen
@ 2025-09-17 7:27 ` Haibo Chen
2025-09-17 16:26 ` Frank Li
2025-09-17 7:27 ` [PATCH v2 3/5] spi: spi-nxp-fspi: Add the DDR LUT command support Haibo Chen
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Haibo Chen @ 2025-09-17 7:27 UTC (permalink / raw)
To: Han Xu, Yogesh Gaur, Mark Brown, Frank Li
Cc: linux-spi, imx, linux-kernel, Haibo Chen
Preparation of supportting DTR mode. In nor suspend, driver will disable
DTR mode, and enable DTR mode back in nor resume. This require the flexspi
driver has the ability to set back to dll override mode in STR mode when
clock rate < 100MHz.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index db4b92490de957580c6298baeb8b68a310c23615..a1c9ad03379682dc1fc2908fbd83e1ae8e91588f 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -767,6 +767,8 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
*/
if (rate > 100000000)
nxp_fspi_dll_calibration(f);
+ else
+ nxp_fspi_dll_override(f);
f->selected = spi_get_chipselect(spi, 0);
}
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/5] spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHz
2025-09-17 7:27 ` [PATCH v2 2/5] spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHz Haibo Chen
@ 2025-09-17 16:26 ` Frank Li
0 siblings, 0 replies; 12+ messages in thread
From: Frank Li @ 2025-09-17 16:26 UTC (permalink / raw)
To: Haibo Chen; +Cc: Han Xu, Yogesh Gaur, Mark Brown, linux-spi, imx, linux-kernel
On Wed, Sep 17, 2025 at 03:27:07PM +0800, Haibo Chen wrote:
> Preparation of supportting DTR mode. In nor suspend, driver will disable
> DTR mode, and enable DTR mode back in nor resume. This require the flexspi
> driver has the ability to set back to dll override mode in STR mode when
> clock rate < 100MHz.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/spi/spi-nxp-fspi.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> index db4b92490de957580c6298baeb8b68a310c23615..a1c9ad03379682dc1fc2908fbd83e1ae8e91588f 100644
> --- a/drivers/spi/spi-nxp-fspi.c
> +++ b/drivers/spi/spi-nxp-fspi.c
> @@ -767,6 +767,8 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
> */
> if (rate > 100000000)
> nxp_fspi_dll_calibration(f);
> + else
> + nxp_fspi_dll_override(f);
>
> f->selected = spi_get_chipselect(spi, 0);
> }
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/5] spi: spi-nxp-fspi: Add the DDR LUT command support
2025-09-17 7:27 [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR mode support Haibo Chen
2025-09-17 7:27 ` [PATCH v2 1/5] spi: spi-nxp-fspi: extract function nxp_fspi_dll_override() Haibo Chen
2025-09-17 7:27 ` [PATCH v2 2/5] spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHz Haibo Chen
@ 2025-09-17 7:27 ` Haibo Chen
2025-09-17 7:27 ` [PATCH v2 4/5] spi: spi-nxp-fspi: add the support for sample data from DQS pad Haibo Chen
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Haibo Chen @ 2025-09-17 7:27 UTC (permalink / raw)
To: Han Xu, Yogesh Gaur, Mark Brown, Frank Li
Cc: linux-spi, imx, linux-kernel, Haibo Chen, Frank Li
For DTR mode, flexspi need to use DDR LUT command, flexspi will switch
to DDR mode when detect the DDR LUT command.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index a1c9ad03379682dc1fc2908fbd83e1ae8e91588f..bd61f951d6befdb78cdd84d4531aab378a47c56f 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -559,12 +559,21 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
u32 target_lut_reg;
/* cmd */
- lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
- op->cmd.opcode);
+ if (op->cmd.dtr) {
+ lutval[0] |= LUT_DEF(0, LUT_CMD_DDR, LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode >> 8);
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_CMD_DDR,
+ LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode & 0xFF);
+ lutidx++;
+ } else {
+ lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+ op->cmd.opcode);
+ }
/* addr bytes */
if (op->addr.nbytes) {
- lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? LUT_ADDR_DDR : LUT_ADDR,
LUT_PAD(op->addr.buswidth),
op->addr.nbytes * 8);
lutidx++;
@@ -572,7 +581,7 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
/* dummy bytes, if needed */
if (op->dummy.nbytes) {
- lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+ lutval[lutidx / 2] |= LUT_DEF(lutidx, op->dummy.dtr ? LUT_DUMMY_DDR : LUT_DUMMY,
/*
* Due to FlexSPI controller limitation number of PAD for dummy
* buswidth needs to be programmed as equal to data buswidth.
@@ -587,7 +596,8 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
if (op->data.nbytes) {
lutval[lutidx / 2] |= LUT_DEF(lutidx,
op->data.dir == SPI_MEM_DATA_IN ?
- LUT_NXP_READ : LUT_NXP_WRITE,
+ (op->data.dtr ? LUT_READ_DDR : LUT_NXP_READ) :
+ (op->data.dtr ? LUT_WRITE_DDR : LUT_NXP_WRITE),
LUT_PAD(op->data.buswidth),
0);
lutidx++;
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 4/5] spi: spi-nxp-fspi: add the support for sample data from DQS pad
2025-09-17 7:27 [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR mode support Haibo Chen
` (2 preceding siblings ...)
2025-09-17 7:27 ` [PATCH v2 3/5] spi: spi-nxp-fspi: Add the DDR LUT command support Haibo Chen
@ 2025-09-17 7:27 ` Haibo Chen
2025-09-17 16:28 ` Frank Li
2025-09-17 7:27 ` [PATCH v2 5/5] spi: spi-nxp-fspi: Add OCT-DTR mode support Haibo Chen
2025-09-19 16:03 ` [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR " Mark Brown
5 siblings, 1 reply; 12+ messages in thread
From: Haibo Chen @ 2025-09-17 7:27 UTC (permalink / raw)
To: Han Xu, Yogesh Gaur, Mark Brown, Frank Li
Cc: linux-spi, imx, linux-kernel, Haibo Chen
flexspi define four mode for sample clock source selection.
Here is the list of modes:
mode 0: Dummy Read strobe generated by FlexSPI Controller and loopback
internally
mode 1: Dummy Read strobe generated by FlexSPI Controller and loopback
from DQS pad
mode 2: Reserved
mode 3: Flash provided Read strobe and input from DQS pad
In default, flexspi use mode 0 after reset. And for DTR mode, flexspi
only support 8D-8D-8D mode. For 8D-8D-8D mode, IC suggest to use mode 3,
otherwise read always get incorrect data.
For DTR mode, flexspi will automatically div 2 of the root clock
and output to device. the formula is:
device_clock = root_clock / (is_dtr ? 2 : 1)
So correct the clock rate setting for DTR mode to get the max
performance.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 56 +++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 53 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index bd61f951d6befdb78cdd84d4531aab378a47c56f..d25679fafad7a94a7ea2a79d7e3da53f4939c9fa 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -399,7 +399,8 @@ struct nxp_fspi {
struct mutex lock;
struct pm_qos_request pm_qos_req;
int selected;
-#define FSPI_NEED_INIT (1 << 0)
+#define FSPI_NEED_INIT BIT(0)
+#define FSPI_DTR_MODE BIT(1)
int flags;
};
@@ -655,6 +656,40 @@ static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
return;
}
+/*
+ * Sample Clock source selection for Flash Reading
+ * Four modes defined by fspi:
+ * mode 0: Dummy Read strobe generated by FlexSPI Controller
+ * and loopback internally
+ * mode 1: Dummy Read strobe generated by FlexSPI Controller
+ * and loopback from DQS pad
+ * mode 2: Reserved
+ * mode 3: Flash provided Read strobe and input from DQS pad
+ *
+ * fspi default use mode 0 after reset
+ */
+static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f,
+ bool op_is_dtr)
+{
+ u32 reg;
+
+ /*
+ * For 8D-8D-8D mode, need to use mode 3 (Flash provided Read
+ * strobe and input from DQS pad), otherwise read operaton may
+ * meet issue.
+ * This mode require flash device connect the DQS pad on board.
+ * For other modes, still use mode 0, keep align with before.
+ * spi_nor_suspend will disable 8D-8D-8D mode, also need to
+ * change the mode back to mode 0.
+ */
+ reg = fspi_readl(f, f->iobase + FSPI_MCR0);
+ if (op_is_dtr)
+ reg |= FSPI_MCR0_RXCLKSRC(3);
+ else /*select mode 0 */
+ reg &= ~FSPI_MCR0_RXCLKSRC(3);
+ fspi_writel(f, reg, f->iobase + FSPI_MCR0);
+}
+
static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
{
int ret;
@@ -736,15 +771,18 @@ static void nxp_fspi_dll_override(struct nxp_fspi *f)
static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
const struct spi_mem_op *op)
{
+ /* flexspi only support one DTR mode: 8D-8D-8D */
+ bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr;
unsigned long rate = op->max_freq;
int ret;
uint64_t size_kb;
/*
* Return, if previously selected target device is same as current
- * requested target device.
+ * requested target device. Also the DTR or STR mode do not change.
*/
- if (f->selected == spi_get_chipselect(spi, 0))
+ if ((f->selected == spi_get_chipselect(spi, 0)) &&
+ (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr))
return;
/* Reset FLSHxxCR0 registers */
@@ -761,6 +799,18 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
+ nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr);
+
+ if (op_is_dtr) {
+ f->flags |= FSPI_DTR_MODE;
+ /* For DTR mode, flexspi will default div 2 and output to device.
+ * so here to config the root clock to 2 * device rate.
+ */
+ rate = rate * 2;
+ } else {
+ f->flags &= ~FSPI_DTR_MODE;
+ }
+
nxp_fspi_clk_disable_unprep(f);
ret = clk_set_rate(f->clk, rate);
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 4/5] spi: spi-nxp-fspi: add the support for sample data from DQS pad
2025-09-17 7:27 ` [PATCH v2 4/5] spi: spi-nxp-fspi: add the support for sample data from DQS pad Haibo Chen
@ 2025-09-17 16:28 ` Frank Li
0 siblings, 0 replies; 12+ messages in thread
From: Frank Li @ 2025-09-17 16:28 UTC (permalink / raw)
To: Haibo Chen; +Cc: Han Xu, Yogesh Gaur, Mark Brown, linux-spi, imx, linux-kernel
On Wed, Sep 17, 2025 at 03:27:09PM +0800, Haibo Chen wrote:
> flexspi define four mode for sample clock source selection.
> Here is the list of modes:
> mode 0: Dummy Read strobe generated by FlexSPI Controller and loopback
> internally
> mode 1: Dummy Read strobe generated by FlexSPI Controller and loopback
> from DQS pad
> mode 2: Reserved
> mode 3: Flash provided Read strobe and input from DQS pad
>
> In default, flexspi use mode 0 after reset. And for DTR mode, flexspi
> only support 8D-8D-8D mode. For 8D-8D-8D mode, IC suggest to use mode 3,
> otherwise read always get incorrect data.
>
> For DTR mode, flexspi will automatically div 2 of the root clock
> and output to device. the formula is:
> device_clock = root_clock / (is_dtr ? 2 : 1)
> So correct the clock rate setting for DTR mode to get the max
> performance.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
> drivers/spi/spi-nxp-fspi.c | 56 +++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 53 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> index bd61f951d6befdb78cdd84d4531aab378a47c56f..d25679fafad7a94a7ea2a79d7e3da53f4939c9fa 100644
> --- a/drivers/spi/spi-nxp-fspi.c
> +++ b/drivers/spi/spi-nxp-fspi.c
> @@ -399,7 +399,8 @@ struct nxp_fspi {
> struct mutex lock;
> struct pm_qos_request pm_qos_req;
> int selected;
> -#define FSPI_NEED_INIT (1 << 0)
> +#define FSPI_NEED_INIT BIT(0)
> +#define FSPI_DTR_MODE BIT(1)
> int flags;
> };
>
> @@ -655,6 +656,40 @@ static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
> return;
> }
>
> +/*
> + * Sample Clock source selection for Flash Reading
> + * Four modes defined by fspi:
> + * mode 0: Dummy Read strobe generated by FlexSPI Controller
> + * and loopback internally
> + * mode 1: Dummy Read strobe generated by FlexSPI Controller
> + * and loopback from DQS pad
> + * mode 2: Reserved
> + * mode 3: Flash provided Read strobe and input from DQS pad
> + *
> + * fspi default use mode 0 after reset
> + */
> +static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f,
> + bool op_is_dtr)
> +{
> + u32 reg;
> +
> + /*
> + * For 8D-8D-8D mode, need to use mode 3 (Flash provided Read
> + * strobe and input from DQS pad), otherwise read operaton may
> + * meet issue.
> + * This mode require flash device connect the DQS pad on board.
> + * For other modes, still use mode 0, keep align with before.
> + * spi_nor_suspend will disable 8D-8D-8D mode, also need to
> + * change the mode back to mode 0.
> + */
> + reg = fspi_readl(f, f->iobase + FSPI_MCR0);
> + if (op_is_dtr)
> + reg |= FSPI_MCR0_RXCLKSRC(3);
> + else /*select mode 0 */
> + reg &= ~FSPI_MCR0_RXCLKSRC(3);
> + fspi_writel(f, reg, f->iobase + FSPI_MCR0);
> +}
> +
> static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
> {
> int ret;
> @@ -736,15 +771,18 @@ static void nxp_fspi_dll_override(struct nxp_fspi *f)
> static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
> const struct spi_mem_op *op)
> {
> + /* flexspi only support one DTR mode: 8D-8D-8D */
> + bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr;
> unsigned long rate = op->max_freq;
> int ret;
> uint64_t size_kb;
>
> /*
> * Return, if previously selected target device is same as current
> - * requested target device.
> + * requested target device. Also the DTR or STR mode do not change.
> */
> - if (f->selected == spi_get_chipselect(spi, 0))
> + if ((f->selected == spi_get_chipselect(spi, 0)) &&
> + (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr))
> return;
>
> /* Reset FLSHxxCR0 registers */
> @@ -761,6 +799,18 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
>
> dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
>
> + nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr);
> +
> + if (op_is_dtr) {
> + f->flags |= FSPI_DTR_MODE;
> + /* For DTR mode, flexspi will default div 2 and output to device.
> + * so here to config the root clock to 2 * device rate.
> + */
Does it pass check patch? suppose multi-line comments is
/*
* For DTR ...
*/
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> + rate = rate * 2;
> + } else {
> + f->flags &= ~FSPI_DTR_MODE;
> + }
> +
> nxp_fspi_clk_disable_unprep(f);
>
> ret = clk_set_rate(f->clk, rate);
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 5/5] spi: spi-nxp-fspi: Add OCT-DTR mode support
2025-09-17 7:27 [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR mode support Haibo Chen
` (3 preceding siblings ...)
2025-09-17 7:27 ` [PATCH v2 4/5] spi: spi-nxp-fspi: add the support for sample data from DQS pad Haibo Chen
@ 2025-09-17 7:27 ` Haibo Chen
2025-09-17 16:30 ` Frank Li
2025-09-19 16:03 ` [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR " Mark Brown
5 siblings, 1 reply; 12+ messages in thread
From: Haibo Chen @ 2025-09-17 7:27 UTC (permalink / raw)
To: Han Xu, Yogesh Gaur, Mark Brown, Frank Li
Cc: linux-spi, imx, linux-kernel, Haibo Chen
Add OCT-DTR mode support in default, since flexspi do not supports
swapping bytes on a 16 bit boundary in OCT-DTR mode, so mark swap16
as false.
lx2160a do not support DQS, so add a quirk to disable DTR mode for this
platform.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index d25679fafad7a94a7ea2a79d7e3da53f4939c9fa..f9371f98a65bdc7e5eaa612c0770a6228bdda364 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -330,6 +330,8 @@
/* Access flash memory using IP bus only */
#define FSPI_QUIRK_USE_IP_ONLY BIT(0)
+/* Disable DTR */
+#define FSPI_QUIRK_DISABLE_DTR BIT(1)
struct nxp_fspi_devtype_data {
unsigned int rxfifo;
@@ -344,7 +346,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = {
.rxfifo = SZ_512, /* (64 * 64 bits) */
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
- .quirks = 0,
+ .quirks = FSPI_QUIRK_DISABLE_DTR,
.lut_num = 32,
.little_endian = true, /* little-endian */
};
@@ -1231,6 +1233,13 @@ static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
};
static const struct spi_controller_mem_caps nxp_fspi_mem_caps = {
+ .dtr = true,
+ .swap16 = false,
+ .per_op_freq = true,
+};
+
+static const struct spi_controller_mem_caps nxp_fspi_mem_caps_disable_dtr = {
+ .dtr = false,
.per_op_freq = true,
};
@@ -1346,7 +1355,12 @@ static int nxp_fspi_probe(struct platform_device *pdev)
ctlr->bus_num = -1;
ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
ctlr->mem_ops = &nxp_fspi_mem_ops;
- ctlr->mem_caps = &nxp_fspi_mem_caps;
+
+ if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR)
+ ctlr->mem_caps = &nxp_fspi_mem_caps_disable_dtr;
+ else
+ ctlr->mem_caps = &nxp_fspi_mem_caps;
+
ctlr->dev.of_node = np;
ret = devm_add_action_or_reset(dev, nxp_fspi_cleanup, f);
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 5/5] spi: spi-nxp-fspi: Add OCT-DTR mode support
2025-09-17 7:27 ` [PATCH v2 5/5] spi: spi-nxp-fspi: Add OCT-DTR mode support Haibo Chen
@ 2025-09-17 16:30 ` Frank Li
2025-09-17 18:09 ` Mark Brown
0 siblings, 1 reply; 12+ messages in thread
From: Frank Li @ 2025-09-17 16:30 UTC (permalink / raw)
To: Haibo Chen; +Cc: Han Xu, Yogesh Gaur, Mark Brown, linux-spi, imx, linux-kernel
On Wed, Sep 17, 2025 at 03:27:10PM +0800, Haibo Chen wrote:
> Add OCT-DTR mode support in default, since flexspi do not supports
> swapping bytes on a 16 bit boundary in OCT-DTR mode, so mark swap16
> as false.
>
> lx2160a do not support DQS, so add a quirk to disable DTR mode for this
does?
> platform.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/spi/spi-nxp-fspi.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> index d25679fafad7a94a7ea2a79d7e3da53f4939c9fa..f9371f98a65bdc7e5eaa612c0770a6228bdda364 100644
> --- a/drivers/spi/spi-nxp-fspi.c
> +++ b/drivers/spi/spi-nxp-fspi.c
> @@ -330,6 +330,8 @@
>
> /* Access flash memory using IP bus only */
> #define FSPI_QUIRK_USE_IP_ONLY BIT(0)
> +/* Disable DTR */
> +#define FSPI_QUIRK_DISABLE_DTR BIT(1)
>
> struct nxp_fspi_devtype_data {
> unsigned int rxfifo;
> @@ -344,7 +346,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = {
> .rxfifo = SZ_512, /* (64 * 64 bits) */
> .txfifo = SZ_1K, /* (128 * 64 bits) */
> .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
> - .quirks = 0,
> + .quirks = FSPI_QUIRK_DISABLE_DTR,
> .lut_num = 32,
> .little_endian = true, /* little-endian */
> };
> @@ -1231,6 +1233,13 @@ static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
> };
>
> static const struct spi_controller_mem_caps nxp_fspi_mem_caps = {
> + .dtr = true,
> + .swap16 = false,
> + .per_op_freq = true,
> +};
> +
> +static const struct spi_controller_mem_caps nxp_fspi_mem_caps_disable_dtr = {
> + .dtr = false,
> .per_op_freq = true,
> };
>
> @@ -1346,7 +1355,12 @@ static int nxp_fspi_probe(struct platform_device *pdev)
> ctlr->bus_num = -1;
> ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
> ctlr->mem_ops = &nxp_fspi_mem_ops;
> - ctlr->mem_caps = &nxp_fspi_mem_caps;
> +
> + if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR)
> + ctlr->mem_caps = &nxp_fspi_mem_caps_disable_dtr;
> + else
> + ctlr->mem_caps = &nxp_fspi_mem_caps;
> +
> ctlr->dev.of_node = np;
>
> ret = devm_add_action_or_reset(dev, nxp_fspi_cleanup, f);
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 5/5] spi: spi-nxp-fspi: Add OCT-DTR mode support
2025-09-17 16:30 ` Frank Li
@ 2025-09-17 18:09 ` Mark Brown
0 siblings, 0 replies; 12+ messages in thread
From: Mark Brown @ 2025-09-17 18:09 UTC (permalink / raw)
To: Frank Li; +Cc: Haibo Chen, Han Xu, Yogesh Gaur, linux-spi, imx, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 453 bytes --]
On Wed, Sep 17, 2025 at 12:30:19PM -0400, Frank Li wrote:
> On Wed, Sep 17, 2025 at 03:27:10PM +0800, Haibo Chen wrote:
> > Add OCT-DTR mode support in default, since flexspi do not supports
> > swapping bytes on a 16 bit boundary in OCT-DTR mode, so mark swap16
> > as false.
> >
> > lx2160a do not support DQS, so add a quirk to disable DTR mode for this
>
> does?
Yes, that's more correct (though the above is perfectly comprehensible).
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR mode support
2025-09-17 7:27 [PATCH v2 0/5] spi: spi-nxp-fspi: add DTR mode support Haibo Chen
` (4 preceding siblings ...)
2025-09-17 7:27 ` [PATCH v2 5/5] spi: spi-nxp-fspi: Add OCT-DTR mode support Haibo Chen
@ 2025-09-19 16:03 ` Mark Brown
5 siblings, 0 replies; 12+ messages in thread
From: Mark Brown @ 2025-09-19 16:03 UTC (permalink / raw)
To: Han Xu, Yogesh Gaur, Frank Li, Haibo Chen
Cc: linux-spi, imx, linux-kernel, Frank Li
On Wed, 17 Sep 2025 15:27:05 +0800, Haibo Chen wrote:
> this patch set add DTR mode support for flexspi.
> For DTR mode, flexspi only support 8D-8D-8D mode.
>
> Patch 1~2 extract nxp_fspi_dll_override(), prepare for adding the DTR mode.
> in nor suspend, it will disable DTR mode, and enable DTR mode back
> in nor resume. this require the flexspi driver has the ability to
> set back to dll override mode in STR mode when clock rate < 100MHz.
> Patch 3 Add the DDR LUT command support. flexspi use LUT command to handle
> the dtr/str mode.
> Patch 4 add the logic of sample clock source selection for STR/DTR mode
> STR use the default mode 0, sample based on the internal dummy pad.
> DTR use the mode 3, sample based on the external DQS pad, so this
> board and device connect the DQS pad.
> adjust the clock rate for DTR mode, when detect the DDR LUT command,
> flexspi will automatically div 2 of the root clock and output to device.
> Patch 5 finally add the DTR support in default after the upper 4 patches's
> prepareation. Since lx2160a do not implement DQS pad, so can't support
> this DTR mode.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/5] spi: spi-nxp-fspi: extract function nxp_fspi_dll_override()
commit: 614180a54d5f21ccb4f60042d19744694d31d3f8
[2/5] spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHz
commit: a9888b3222ec73d055447a39cf9a0118f67497f4
[3/5] spi: spi-nxp-fspi: Add the DDR LUT command support
commit: 3c1000e15fd0eb387fcca420c9fb36ae07887782
[4/5] spi: spi-nxp-fspi: add the support for sample data from DQS pad
commit: c07f270323175b83779c2c2b80b360ed476baec5
[5/5] spi: spi-nxp-fspi: Add OCT-DTR mode support
commit: 0f67557763accbdd56681f17ed5350735198c57b
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply [flat|nested] 12+ messages in thread