[PATCH 0/8] riscv: Add cpufeature parsing and hwprobe export for RVA23 extensions

[PATCH 0/8] riscv: Add cpufeature parsing and hwprobe export for RVA23 extensions

[Guodong Xu]

Complete the previous series [1] (Patch 6-9), which added DT bindings for
extensions mandatory in the RVA23 Profile, by adding cpufeature parsing
and hwprobe exports.

This patchset is organized so that cpufeature parsing and hwprobe export
(when needed) are grouped together.

Patches 1-2: B extension
Patches   3: Enforce dependency checking for Ziccrse.
Patches 4-6: Handle the RVA23U64 extensions, namely Za64rs,
               Ziccamoa, Ziccif, Zicclsm.
Patches 7-8: Handle the RVA23S64 extensions, namely 1) Ssccptr,
               Sscounterenw, Sstvala, Sstvecd, Ssu64xl, 2) Sha and
               its comprised sub-extensions.

Noted that among all these extensions, I chose to hwprobe only three:
B, Ziccif and Zicclsm. My observation is all recently merged hwprobe
extensions (such as Zaamo, Zicntr, Zicbom) expose instructions or CSR
that userspace directly executes, or hints for userspace prefetch.

Whereas Za64rs and Ziccamoa are named features, currently I don't see
a need for userspace to hwprobe them. They can be added later if a
concrete userspace use case emerges.

Zicclsm is hwprobe exported, previous LKML discussion can be found here:
Conor Dooley noted the need for "bindings, detection and hwprobe key
for Zicclsm" [2] after Palmer's misaligned access clarification [3].

Ziccif guarantees atomic instruction fetches for naturally aligned
instructions. Exposing it through hwprobe allows userspace performing
concurrent code modification (CMODX) to confirm the underlying
hardware guarantee at runtime. See Documentation/arch/riscv/cmodx.rst
[4] for background.

The B extension hwprobe bit uses a system-wide check against the global
ISA bitmap, following the same pattern as C in hwprobe_isa_ext0().

Zicclsm and Ziccif use the per-CPU EXT_KEY() mechanism, consistent with
individual extension exports.

This series is based on next-20260123, plus the sump patchset. Tested on
SpacemiT K3 PICO ITX board, checked both cat /proc/cpuinfo and a hwprobe
userspace testing stub.

Link: https://lore.kernel.org/all/20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com/ [1]
Link: https://lore.kernel.org/all/20240524-ruckus-trickily-1cda26c1a455@spud/ [2]
Link: https://lore.kernel.org/all/20240524185600.5919-1-palmer@rivosinc.com/ [3]
Link: https://lore.kernel.org/all/20250407180838.42877-12-andybnac@gmail.com/ [4]

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
Guodong Xu (8):
      riscv: cpufeature: Add parsing for B
      riscv: hwprobe: Add support for probing B
      riscv: cpufeature: Enforce Ziccrse dependency on Zalrsc
      riscv: cpufeature: Add parsing for Za64rs, Ziccamoa, Ziccif, and Zicclsm
      riscv: hwprobe: Add support for probing Zicclsm
      riscv: hwprobe: Add support for probing Ziccif
      riscv: cpufeature: Add parsing for Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl
      riscv: cpufeature: Add parsing for Sha and its comprised extensions

 Documentation/arch/riscv/hwprobe.rst  | 11 ++++++
 arch/riscv/include/asm/hwcap.h        | 18 ++++++++++
 arch/riscv/include/uapi/asm/hwprobe.h |  3 ++
 arch/riscv/kernel/cpufeature.c        | 63 ++++++++++++++++++++++++++++++++++-
 arch/riscv/kernel/sys_hwprobe.c       |  5 +++
 5 files changed, 99 insertions(+), 1 deletion(-)
---
base-commit: 4af4e95edc37ae54f64cbd75b46f16ce15f3a6b8
change-id: 20260116-isa-ext-parse-export-047c0003e12c
prerequisite-message-id: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com>
prerequisite-patch-id: f10e134f9f9291ace47876fa4b2171094838a40b
prerequisite-patch-id: 59a67878b96d6de42a9bad35fc610ef10dabff55
prerequisite-patch-id: 30a3e1b50fc95ab5a521f4dab693d914713992f2

Best regards,
-- 
Guodong Xu <guodong@riscstar.com>

[PATCH 1/8] riscv: cpufeature: Add parsing for B

[Guodong Xu]

The B extension comprises the Zba, Zbb, and Zbs extensions, as defined
by version 20240411 of the RISC-V Instruction Set Manual Volume I
Unprivileged Architecture.

Add B as a superset extension so that when "b" is encountered in the ISA
string or devicetree, its sub-extensions are automatically enabled.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/include/asm/hwcap.h |  1 +
 arch/riscv/kernel/cpufeature.c | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index aa2af21f3bd32573558e964f94b32f9739f4c89f..35e87e4a8475a9201e84e7f9f8a4d10dfd9e4759 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -11,6 +11,7 @@
 #include <uapi/asm/hwcap.h>
 
 #define RISCV_ISA_EXT_a		('a' - 'a')
+#define RISCV_ISA_EXT_b		('b' - 'a')
 #define RISCV_ISA_EXT_c		('c' - 'a')
 #define RISCV_ISA_EXT_d		('d' - 'a')
 #define RISCV_ISA_EXT_f		('f' - 'a')
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 63ad6393b2c6dcbfd6e7e247cf4bacb6c11fe58e..3d3af82a53250f29204a3fb138feaf520a878d0e 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -480,6 +480,15 @@ static const unsigned int riscv_supm_exts[] = {
 	RISCV_ISA_EXT_SUPM
 };
 
+/*
+ * The B extension comprises Zba, Zbb, and Zbs.
+ */
+static const unsigned int riscv_b_exts[] = {
+	RISCV_ISA_EXT_ZBA,
+	RISCV_ISA_EXT_ZBB,
+	RISCV_ISA_EXT_ZBS,
+};
+
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
  * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA
@@ -528,6 +537,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate),
 	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
 	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
+	__RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_b, riscv_b_exts),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
 	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),

-- 
2.43.0

[PATCH 2/8] riscv: hwprobe: Add support for probing B

[Guodong Xu]

The B extension is a shorthand for the Zba, Zbb, and Zbs extensions
combined, as defined by version 20240411 of the RISC-V Instruction Set
Manual Volume I Unprivileged Architecture.

The B bit is added as a system-wide check in RISCV_HWPROBE_KEY_IMA_EXT_1
using the global ISA bitmap.

It should be noted that the kernel already exports Zba, Zbb, and Zbs
individually in RISCV_HWPROBE_KEY_IMA_EXT_0 with per-CPU granularity.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 4 ++++
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_hwprobe.c       | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index c420a8349bc6811573051154bc9c64617f3d7464..8430bc94fdba073e1e3ded973322c773c598a0b5 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -391,3 +391,7 @@ The following keys are defined:
 * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
   extensions that are compatible with the
   :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
+
+  * :c:macro:`RISCV_HWPROBE_IMA_B`: The B extension is supported, as defined
+    by version 20240411 of the RISC-V Instruction Set Manual, Volume I
+    Unprivileged Architecture.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 9139edba0aecbf466098ace486658aaeeb6667e3..e7bd2e9ea33459572d01495f4063e32e3207e48f 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -116,6 +116,7 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE	15
 #define RISCV_HWPROBE_KEY_IMA_EXT_1		16
 #define		RISCV_HWPROBE_EXT_ZICFISS	(1ULL << 0)
+#define		RISCV_HWPROBE_IMA_B		(1ULL << 1)
 
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 1659d31fd288fc296d711c111e8d1a2e2fc8026a..491af3c5b66a0cb30471dafc8b31c70df2f9bed1 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -191,6 +191,9 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 
 	pair->value = 0;
 
+	if (riscv_isa_extension_available(NULL, b))
+		pair->value |= RISCV_HWPROBE_IMA_B;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.

-- 
2.43.0

[PATCH 3/8] riscv: cpufeature: Enforce Ziccrse dependency on Zalrsc

[Guodong Xu]

Ziccrse guarantees RsrvEventual for cacheable coherent main memory,
a property that is only meaningful when LR/SC instructions are present.
Since Zalrsc is the extension that provides LR/SC (also implied by A),
add a validation callback to enforce this dependency.

Introduce riscv_ext_zalrsc_depends() following the naming convention
used by other pure dependency checks like riscv_ext_f_depends().

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/kernel/cpufeature.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3d3af82a53250f29204a3fb138feaf520a878d0e..68c94fe29cd1b26925fa38a5c877d699bbc88e25 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -338,6 +338,15 @@ static int riscv_ext_supm_validate(const struct riscv_isa_ext_data *data,
 	return -EPROBE_DEFER;
 }
 
+static int riscv_ext_zalrsc_depends(const struct riscv_isa_ext_data *data,
+				    const unsigned long *isa_bitmap)
+{
+	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZALRSC))
+		return 0;
+
+	return -EPROBE_DEFER;
+}
+
 static const unsigned int riscv_a_exts[] = {
 	RISCV_ISA_EXT_ZAAMO,
 	RISCV_ISA_EXT_ZALRSC,
@@ -543,7 +552,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
-	__RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
+	__RISCV_ISA_EXT_DATA_VALIDATE(ziccrse, RISCV_ISA_EXT_ZICCRSE, riscv_ext_zalrsc_depends),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts,
 					  riscv_cfilp_validate),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts,

-- 
2.43.0

[PATCH 4/8] riscv: cpufeature: Add parsing for Za64rs, Ziccamoa, Ziccif, and Zicclsm

[Guodong Xu]

Add ISA extension parsing for four memory system related extensions:

 - Za64rs: reservation set size of at most 64 bytes
 - Ziccamoa: main memory must support all atomics in A
 - Ziccif: main memory instruction fetch atomicity
 - Zicclsm: main memory must support misaligned loads and stores

Za64rs depends on Zalrsc (or the A extension, which implies Zalrsc).
Ziccamoa depends on Zaamo (or the A extension, which implies Zaamo).
Both use dependency callbacks to enforce these requirements.

All of them are labeled as mandatory in RVA23 Profile 1.0.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/include/asm/hwcap.h |  4 ++++
 arch/riscv/kernel/cpufeature.c | 13 +++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 35e87e4a8475a9201e84e7f9f8a4d10dfd9e4759..5a050fae5302c7717596799967d8d514e7dfc536 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -114,6 +114,10 @@
 #define RISCV_ISA_EXT_ZICFILP		104
 #define RISCV_ISA_EXT_ZICFISS		105
 #define RISCV_ISA_EXT_SUPM		106
+#define RISCV_ISA_EXT_ZA64RS		107
+#define RISCV_ISA_EXT_ZICCAMOA		108
+#define RISCV_ISA_EXT_ZICCIF		109
+#define RISCV_ISA_EXT_ZICCLSM		110
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 68c94fe29cd1b26925fa38a5c877d699bbc88e25..fee5b20bb171334e8ca60af25485f43a9acef619 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -347,6 +347,15 @@ static int riscv_ext_zalrsc_depends(const struct riscv_isa_ext_data *data,
 	return -EPROBE_DEFER;
 }
 
+static int riscv_ext_zaamo_depends(const struct riscv_isa_ext_data *data,
+				   const unsigned long *isa_bitmap)
+{
+	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZAAMO))
+		return 0;
+
+	return -EPROBE_DEFER;
+}
+
 static const unsigned int riscv_a_exts[] = {
 	RISCV_ISA_EXT_ZAAMO,
 	RISCV_ISA_EXT_ZALRSC,
@@ -552,6 +561,9 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
+	__RISCV_ISA_EXT_DATA_VALIDATE(ziccamoa, RISCV_ISA_EXT_ZICCAMOA, riscv_ext_zaamo_depends),
+	__RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF),
+	__RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM),
 	__RISCV_ISA_EXT_DATA_VALIDATE(ziccrse, RISCV_ISA_EXT_ZICCRSE, riscv_ext_zalrsc_depends),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts,
 					  riscv_cfilp_validate),
@@ -565,6 +577,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
 	__RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
+	__RISCV_ISA_EXT_DATA_VALIDATE(za64rs, RISCV_ISA_EXT_ZA64RS, riscv_ext_zalrsc_depends),
 	__RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
 	__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
 	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),

-- 
2.43.0

[PATCH 5/8] riscv: hwprobe: Add support for probing Zicclsm

[Guodong Xu]

Zicclsm guarantees that misaligned loads and stores to main memory
regions are supported. This is a mandatory extension in the RVA23U64
user-mode profile.

Export Zicclsm through hwprobe to help userspace check the existence of
this capability.

"Misaligned vector accesses are only supported if Zicclsm extension
is supported", as clarified in:

commit 982a7eb97be6 ("Documentation: RISC-V: uabi: Only scalar
misaligned loads are supported")

Link: https://lore.kernel.org/all/20240524185600.5919-1-palmer@rivosinc.com/
Link: https://lore.kernel.org/all/20240524-ruckus-trickily-1cda26c1a455@spud/
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 4 ++++
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_hwprobe.c       | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 8430bc94fdba073e1e3ded973322c773c598a0b5..198b31bc9a20c2739988849cf7d2948a4fe1bdc4 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -395,3 +395,7 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_IMA_B`: The B extension is supported, as defined
     by version 20240411 of the RISC-V Instruction Set Manual, Volume I
     Unprivileged Architecture.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension for main
+    memory that must support misaligned loads and stores, as ratified in
+    RISC-V Profiles Version 1.0.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index e7bd2e9ea33459572d01495f4063e32e3207e48f..323c488de5548883ddceac256bf312ec854ee899 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -117,6 +117,7 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_IMA_EXT_1		16
 #define		RISCV_HWPROBE_EXT_ZICFISS	(1ULL << 0)
 #define		RISCV_HWPROBE_IMA_B		(1ULL << 1)
+#define		RISCV_HWPROBE_EXT_ZICCLSM	(1ULL << 2)
 
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 491af3c5b66a0cb30471dafc8b31c70df2f9bed1..6997c6007a8e86dff85b5b83d14924e7c2466eb2 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -208,6 +208,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 		 * in the hart_isa bitmap, are made.
 		 */
 		EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing);
 	}
 
 	/* Now turn off reporting features if any CPU is missing it. */

-- 
2.43.0

[PATCH 6/8] riscv: hwprobe: Add support for probing Ziccif

[Guodong Xu]

Ziccif guarantees that instruction fetches from main memory regions with
cacheability and coherence PMAs are atomic for naturally aligned
power-of-2 sizes up to min(ILEN,XLEN). This is a mandatory extension
in the RVA23U64 user-mode profile (and has been since RVA20U64).

Exposing Ziccif through hwprobe allows userspace performing concurrent
code modification (CMODX) to confirm the underlying hardware guarantees
atomic instruction fetches for naturally aligned instructions.

Previous communitiy discussion exists [1].

Link: https://lore.kernel.org/all/20250407180838.42877-12-andybnac@gmail.com/ [1]
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 3 +++
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_hwprobe.c       | 1 +
 3 files changed, 5 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 198b31bc9a20c2739988849cf7d2948a4fe1bdc4..89ff3d4e9f299de2b7d14b7ed77a04409f821621 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -399,3 +399,6 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension for main
     memory that must support misaligned loads and stores, as ratified in
     RISC-V Profiles Version 1.0.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension for main memory
+    instruction fetch atomicity, as ratified in RISC-V Profiles Version 1.0.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 323c488de5548883ddceac256bf312ec854ee899..ebf1434f54e6dc640b3414e8a23ab8e29ab243e4 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -118,6 +118,7 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZICFISS	(1ULL << 0)
 #define		RISCV_HWPROBE_IMA_B		(1ULL << 1)
 #define		RISCV_HWPROBE_EXT_ZICCLSM	(1ULL << 2)
+#define		RISCV_HWPROBE_EXT_ZICCIF	(1ULL << 3)
 
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 6997c6007a8e86dff85b5b83d14924e7c2466eb2..8d774a0be9110c997a200c4eeeb434e8afd5c7f9 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -209,6 +209,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 		 */
 		EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing);
 	}
 
 	/* Now turn off reporting features if any CPU is missing it. */

-- 
2.43.0

[PATCH 7/8] riscv: cpufeature: Add parsing for Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl

[Guodong Xu]

Add ISA extension parsing for five supervisor-level extensions ratified
in RISC-V Profiles Version 1.0:

 - Ssccptr: main memory hardware page-table reads
 - Sscounterenw: writable enables in scounteren for any supported counter
 - Sstvala: stval provides all needed values
 - Sstvecd: stvec supports Direct mode
 - Ssu64xl: UXLEN=64 must be supported

These are simple extensions with no dependencies.

All of them are labeled as mandatory in RVA23 Profile 1.0.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/include/asm/hwcap.h | 5 +++++
 arch/riscv/kernel/cpufeature.c | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 5a050fae5302c7717596799967d8d514e7dfc536..75f64f5b7355db6ea5218f544ceda3be9619a58a 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -118,6 +118,11 @@
 #define RISCV_ISA_EXT_ZICCAMOA		108
 #define RISCV_ISA_EXT_ZICCIF		109
 #define RISCV_ISA_EXT_ZICCLSM		110
+#define RISCV_ISA_EXT_SSCCPTR		111
+#define RISCV_ISA_EXT_SSCOUNTERENW	112
+#define RISCV_ISA_EXT_SSTVALA		113
+#define RISCV_ISA_EXT_SSTVECD		114
+#define RISCV_ISA_EXT_SSU64XL		115
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fee5b20bb171334e8ca60af25485f43a9acef619..fff35a3e85db70f5610df2667f2b4f45f091cb2b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -643,9 +643,14 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_supm_exts),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
+	__RISCV_ISA_EXT_DATA(ssccptr, RISCV_ISA_EXT_SSCCPTR),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+	__RISCV_ISA_EXT_DATA(sscounterenw, RISCV_ISA_EXT_SSCOUNTERENW),
 	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_supm_exts),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
+	__RISCV_ISA_EXT_DATA(sstvala, RISCV_ISA_EXT_SSTVALA),
+	__RISCV_ISA_EXT_DATA(sstvecd, RISCV_ISA_EXT_SSTVECD),
+	__RISCV_ISA_EXT_DATA(ssu64xl, RISCV_ISA_EXT_SSU64XL),
 	__RISCV_ISA_EXT_DATA_VALIDATE(supm, RISCV_ISA_EXT_SUPM, riscv_ext_supm_validate),
 	__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
 	__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),

-- 
2.43.0

[PATCH 8/8] riscv: cpufeature: Add parsing for Sha and its comprised extensions

[Guodong Xu]

Sha is a profile-defined extension introduced in RVA23 Profiles
Version 1.0 that captures the full set of features mandated to be
supported along with the H extension. The augmented hypervisor
extension was optional in RVA22 and mandatory in RVA23.

Sha comprises: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala,
Shvstvecd, and Ssstateen.

Add Sha as a superset extension so that when "sha" is encountered in
the ISA string, its sub-extensions are automatically enabled. Also add
individual parsing for each of the comprised extensions.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/include/asm/hwcap.h |  8 ++++++++
 arch/riscv/kernel/cpufeature.c | 24 ++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 75f64f5b7355db6ea5218f544ceda3be9619a58a..8cc1d47b1068637fabb94a3f8defb1d6fe3bc180 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -123,6 +123,14 @@
 #define RISCV_ISA_EXT_SSTVALA		113
 #define RISCV_ISA_EXT_SSTVECD		114
 #define RISCV_ISA_EXT_SSU64XL		115
+#define RISCV_ISA_EXT_SHA		116
+#define RISCV_ISA_EXT_SHCOUNTERENW	117
+#define RISCV_ISA_EXT_SHGATPA		118
+#define RISCV_ISA_EXT_SHTVALA		119
+#define RISCV_ISA_EXT_SHVSATPA		120
+#define RISCV_ISA_EXT_SHVSTVALA		121
+#define RISCV_ISA_EXT_SHVSTVECD		122
+#define RISCV_ISA_EXT_SSSTATEEN		123
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fff35a3e85db70f5610df2667f2b4f45f091cb2b..13fa5dd555c4cb40831f75c3a0e0c4c5b518864b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -498,6 +498,22 @@ static const unsigned int riscv_supm_exts[] = {
 	RISCV_ISA_EXT_SUPM
 };
 
+/*
+ * The Sha extension captures the full set of features mandated along with the
+ * H extension. Sha comprises: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa,
+ * Shvstvala, Shvstvecd, and Ssstateen.
+ */
+static const unsigned int riscv_sha_exts[] = {
+	RISCV_ISA_EXT_h,
+	RISCV_ISA_EXT_SHCOUNTERENW,
+	RISCV_ISA_EXT_SHGATPA,
+	RISCV_ISA_EXT_SHTVALA,
+	RISCV_ISA_EXT_SHVSATPA,
+	RISCV_ISA_EXT_SHVSTVALA,
+	RISCV_ISA_EXT_SHVSTVECD,
+	RISCV_ISA_EXT_SSSTATEEN,
+};
+
 /*
  * The B extension comprises Zba, Zbb, and Zbs.
  */
@@ -638,6 +654,13 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA_VALIDATE(zvksh, RISCV_ISA_EXT_ZVKSH, riscv_ext_vector_crypto_validate),
 	__RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ext_vector_crypto_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_crypto_validate),
+	__RISCV_ISA_EXT_SUPERSET(sha, RISCV_ISA_EXT_SHA, riscv_sha_exts),
+	__RISCV_ISA_EXT_DATA(shcounterenw, RISCV_ISA_EXT_SHCOUNTERENW),
+	__RISCV_ISA_EXT_DATA(shgatpa, RISCV_ISA_EXT_SHGATPA),
+	__RISCV_ISA_EXT_DATA(shtvala, RISCV_ISA_EXT_SHTVALA),
+	__RISCV_ISA_EXT_DATA(shvsatpa, RISCV_ISA_EXT_SHVSATPA),
+	__RISCV_ISA_EXT_DATA(shvstvala, RISCV_ISA_EXT_SHVSTVALA),
+	__RISCV_ISA_EXT_DATA(shvstvecd, RISCV_ISA_EXT_SHVSTVECD),
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
 	__RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_supm_exts),
@@ -647,6 +670,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
 	__RISCV_ISA_EXT_DATA(sscounterenw, RISCV_ISA_EXT_SSCOUNTERENW),
 	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_supm_exts),
+	__RISCV_ISA_EXT_DATA(ssstateen, RISCV_ISA_EXT_SSSTATEEN),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
 	__RISCV_ISA_EXT_DATA(sstvala, RISCV_ISA_EXT_SSTVALA),
 	__RISCV_ISA_EXT_DATA(sstvecd, RISCV_ISA_EXT_SSTVECD),

-- 
2.43.0

Re: [PATCH 1/8] riscv: cpufeature: Add parsing for B

[Andrew Jones]

On Sat, Feb 07, 2026 at 06:27:55PM +0800, Guodong Xu wrote:
> The B extension comprises the Zba, Zbb, and Zbs extensions, as defined
> by version 20240411 of the RISC-V Instruction Set Manual Volume I
> Unprivileged Architecture.
> 
> Add B as a superset extension so that when "b" is encountered in the ISA
> string or devicetree, its sub-extensions are automatically enabled.
> 
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
>  arch/riscv/include/asm/hwcap.h |  1 +
>  arch/riscv/kernel/cpufeature.c | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index aa2af21f3bd32573558e964f94b32f9739f4c89f..35e87e4a8475a9201e84e7f9f8a4d10dfd9e4759 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -11,6 +11,7 @@
>  #include <uapi/asm/hwcap.h>
>  
>  #define RISCV_ISA_EXT_a		('a' - 'a')
> +#define RISCV_ISA_EXT_b		('b' - 'a')
>  #define RISCV_ISA_EXT_c		('c' - 'a')
>  #define RISCV_ISA_EXT_d		('d' - 'a')
>  #define RISCV_ISA_EXT_f		('f' - 'a')
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 63ad6393b2c6dcbfd6e7e247cf4bacb6c11fe58e..3d3af82a53250f29204a3fb138feaf520a878d0e 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -480,6 +480,15 @@ static const unsigned int riscv_supm_exts[] = {
>  	RISCV_ISA_EXT_SUPM
>  };
>  
> +/*
> + * The B extension comprises Zba, Zbb, and Zbs.
> + */
> +static const unsigned int riscv_b_exts[] = {
> +	RISCV_ISA_EXT_ZBA,
> +	RISCV_ISA_EXT_ZBB,
> +	RISCV_ISA_EXT_ZBS,
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA
> @@ -528,6 +537,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate),
>  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
>  	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
> +	__RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_b, riscv_b_exts),
>  	__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
>  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
>  	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
> 
> -- 
> 2.43.0

Hi Guodong Xu,

As part of the "hwprobe: Introduce rva23u64 base behavior" RFC [1] I
posted a similar patch where I also added B to hwcap. Can you take a
look at that?

[1] https://lore.kernel.org/all/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/

Thanks,
drew

Re: [PATCH 2/8] riscv: hwprobe: Add support for probing B

[Andrew Jones]

On Sat, Feb 07, 2026 at 06:27:56PM +0800, Guodong Xu wrote:
> The B extension is a shorthand for the Zba, Zbb, and Zbs extensions
> combined, as defined by version 20240411 of the RISC-V Instruction Set
> Manual Volume I Unprivileged Architecture.
> 
> The B bit is added as a system-wide check in RISCV_HWPROBE_KEY_IMA_EXT_1
> using the global ISA bitmap.
> 
> It should be noted that the kernel already exports Zba, Zbb, and Zbs
> individually in RISCV_HWPROBE_KEY_IMA_EXT_0 with per-CPU granularity.

For the rva23u64 base behavior rfc I opted to not add a B hwprobe
extension bit because Zba, Zbb, and Zbs were already in hwprobe and
because I added B to hwcap. I realize we have 'FD', C, and V in hwprobe as
well as the 'IMA' base, so I'm open to adding 'B' as well if that's what
users expect, I'm just not sure if we need it, especially with adding the
rva23u64 base as a quick way to determine B is present along with all
other rva23 extensions.

Thanks,
drew

Re: [PATCH 1/8] riscv: cpufeature: Add parsing for B

[Guodong Xu]

Hi Drew,

On Mon, Feb 9, 2026 at 12:43 AM Andrew Jones
<andrew.jones@oss.qualcomm.com> wrote:
>
> On Sat, Feb 07, 2026 at 06:27:55PM +0800, Guodong Xu wrote:
> > The B extension comprises the Zba, Zbb, and Zbs extensions, as defined
> > by version 20240411 of the RISC-V Instruction Set Manual Volume I
> > Unprivileged Architecture.
> >
> > Add B as a superset extension so that when "b" is encountered in the ISA
> > string or devicetree, its sub-extensions are automatically enabled.
> >
> > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > ---
> >  arch/riscv/include/asm/hwcap.h |  1 +
> >  arch/riscv/kernel/cpufeature.c | 10 ++++++++++
> >  2 files changed, 11 insertions(+)
> >

>
> Hi Guodong Xu,
>
> As part of the "hwprobe: Introduce rva23u64 base behavior" RFC [1] I

Thanks for pointing me to your link. I'm happy to look
at your RFC series. I like your part of adding rva23u64
and rva23s64, I've been thinking the same, but you
offered the solution!

> posted a similar patch where I also added B to hwcap. Can you take a
> look at that?

Sure, I'll comment in your series.

>
> [1] https://lore.kernel.org/all/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/

With the patches in [1], I would drop the duplicated
ones from my series (5 of them if I counted correctly),
and keep only the 3 patches which add SHA and other
S extensions.

Would you prefer I send a v2 based on your series, or
would it be easier for you to pick them up directly?
Either way works for me.

Best regards,
Guodong Xu

>
> Thanks,
> drew

Re: [PATCH 1/8] riscv: cpufeature: Add parsing for B

[Andrew Jones]

On Tue, Feb 10, 2026 at 04:15:52PM +0800, Guodong Xu wrote:
...
> > [1] https://lore.kernel.org/all/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/
> 
> With the patches in [1], I would drop the duplicated
> ones from my series (5 of them if I counted correctly),
> and keep only the 3 patches which add SHA and other
> S extensions.
> 
> Would you prefer I send a v2 based on your series, or
> would it be easier for you to pick them up directly?
> Either way works for me.

I can pick yours up, which would allow me to get rid of some
TODOs I have in my patch10.

Thanks,
drew