[PATCH v3 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64

[PATCH v3 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64

[Richard Cheng]

This series fixes numerous issues in the resctrl selftests on aarch64,
where they currently misreport failures.

Patch 1 skips L3_CAT at feature-check time when MPAM legitimately
reports every CBM bit as shareable, instead of failing the test.

Patch 2 adds aarch64 implementations of cl_flush() and sb() in
fill_buf.c so cache flushes are no longer silent no-ops.

Patch 3 teaches detect_vendor() about aarch64 (which exposes no
vendor_id in /proc/cpuinfo) and lets arch_supports_noncont_cat()
return true for ARM, fixing spurious L3_NONCONT_CAT failures.

Changes since v2:
    - Patch 1: add Ilpo's Reviewed-by.
    - Patch 3: factor the aarch64 check into a detect_aarch64() helper
      instead of an inline #ifdef in detect_vendor().
    - Fix the patch ordering in this cover letter to match the series.

Richard Cheng (3):
  selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists
  selftests/resctrl: Implement cl_flush() and sb() for aarch64
  selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT

 tools/testing/selftests/resctrl/cat_test.c    | 32 +++++++++++++++++--
 tools/testing/selftests/resctrl/fill_buf.c    |  6 ++++
 tools/testing/selftests/resctrl/resctrl.h     |  1 +
 .../testing/selftests/resctrl/resctrl_tests.c | 21 ++++++++++++
 4 files changed, 57 insertions(+), 3 deletions(-)

-- 
2.43.0

[PATCH v3 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists

[Richard Cheng]

L3_CAT measures cache isolation, which requires at least one cache bit
that is not shared with non-CPU agents, i.e. cbm_mask & ~shareable_bits
must be non-zero. On MPAM, shareable_bits == cbm_mask is a legitimate
state, so there are situations in which no bit can be reported as
exclusive.

Previously get_mask_no_shareable() was invoked inside cat_run_test()
and silently returned -1, which surfaced as a test failure on arm64
MPAM systems.

Implement cat_feature_check() to perform the same check at feature-check
time. It prints a diagnostic and returns false so the test case is
skipped instead of failing.

Tested-by: Chen Yu <yu.c.chen@intel.com>
Signed-off-by: Richard Cheng <icheng@nvidia.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
 tools/testing/selftests/resctrl/cat_test.c | 23 +++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
index f00b622c1460..dc414e55ae94 100644
--- a/tools/testing/selftests/resctrl/cat_test.c
+++ b/tools/testing/selftests/resctrl/cat_test.c
@@ -378,11 +378,32 @@ static bool noncont_cat_feature_check(const struct resctrl_test *test)
 	return resource_info_file_exists(test->resource, "sparse_masks");
 }
 
+static bool cat_feature_check(const struct resctrl_test *test)
+{
+	unsigned long mask;
+
+	if (!test_resource_feature_check(test))
+		return false;
+
+	/*
+	 * The CAT isolation measurement needs a cache portion that no
+	 * other agent shares. On MPAM the kernel may legitimately report
+	 * all bits as shareable; skip the test if that is the case.
+	 */
+	if (get_mask_no_shareable(test->resource, &mask)) {
+		ksft_print_msg("All %s bits are shareable; cannot measure CAT isolation\n",
+			       test->resource);
+		return false;
+	}
+
+	return true;
+}
+
 struct resctrl_test l3_cat_test = {
 	.name = "L3_CAT",
 	.group = "CAT",
 	.resource = "L3",
-	.feature_check = test_resource_feature_check,
+	.feature_check = cat_feature_check,
 	.run_test = cat_run_test,
 	.cleanup = cat_test_cleanup,
 };
-- 
2.43.0

Re: [PATCH v3 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists

[Reinette Chatre]

Hi Richard,

On 5/28/26 7:23 PM, Richard Cheng wrote:
> L3_CAT measures cache isolation, which requires at least one cache bit
> that is not shared with non-CPU agents, i.e. cbm_mask & ~shareable_bits
> must be non-zero. On MPAM, shareable_bits == cbm_mask is a legitimate
> state, so there are situations in which no bit can be reported as
> exclusive.

To make problem clear, please append "... causing the L3_CAT test to fail."

> 
> Previously get_mask_no_shareable() was invoked inside cat_run_test()

Written in past tense is confusing since it describes current behavior.

> and silently returned -1, which surfaced as a test failure on arm64
> MPAM systems.
> 
> Implement cat_feature_check() to perform the same check at feature-check
> time. It prints a diagnostic and returns false so the test case is
> skipped instead of failing.

The second and third paragraph describes a lot of detail that is clear from
the patch. I think these two paragraphs can just be replaced with something
brief like:
	Skip, don't fail, the L3_CAT test when the platform does not have any
	cache portions that the test can use.
	

> 
> Tested-by: Chen Yu <yu.c.chen@intel.com>
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> ---
>  tools/testing/selftests/resctrl/cat_test.c | 23 +++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
> index f00b622c1460..dc414e55ae94 100644
> --- a/tools/testing/selftests/resctrl/cat_test.c
> +++ b/tools/testing/selftests/resctrl/cat_test.c
> @@ -378,11 +378,32 @@ static bool noncont_cat_feature_check(const struct resctrl_test *test)
>  	return resource_info_file_exists(test->resource, "sparse_masks");
>  }
>  
> +static bool cat_feature_check(const struct resctrl_test *test)
> +{
> +	unsigned long mask;
> +
> +	if (!test_resource_feature_check(test))
> +		return false;
> +
> +	/*
> +	 * The CAT isolation measurement needs a cache portion that no
> +	 * other agent shares. On MPAM the kernel may legitimately report

This does not seem to be unique to MPAM (https://lore.kernel.org/lkml/c9bee1ad-10f8-4e69-8d90-609cdd72580e@intel.com/)
Perhaps "On MPAM the kernel may" -> "Some platforms may"?

> +	 * all bits as shareable; skip the test if that is the case.
> +	 */
> +	if (get_mask_no_shareable(test->resource, &mask)) {
> +		ksft_print_msg("All %s bits are shareable; cannot measure CAT isolation\n",
> +			       test->resource);
> +		return false;
> +	}
> +
> +	return true;
> +}
> +
>  struct resctrl_test l3_cat_test = {
>  	.name = "L3_CAT",
>  	.group = "CAT",
>  	.resource = "L3",
> -	.feature_check = test_resource_feature_check,
> +	.feature_check = cat_feature_check,
>  	.run_test = cat_run_test,
>  	.cleanup = cat_test_cleanup,
>  };

Patch looks good to me, thank you.

Reinette

[PATCH v3 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64

[Richard Cheng]

cl_flush() and sb() in fill_buf.c only have implementations for i386
and x86_64, so on aarch64 both compile to empty functions. mem_flush()
then walks the buffer calling a no-op cl_flush() per cache line and
finishes with a no-op sb(), leaving any caller that expects a flushed
buffer (e.g. CMT, L3_CAT) operating on unflushed state with no warning.

Add an aarch64 code block using the ARM equivalents:
* "dc civac, %0" for cl_flush()
* "dsb sy"       for sb()

Both instructions are EL0-accessible on Linux aarch64.

Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
 tools/testing/selftests/resctrl/fill_buf.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c
index 19a01a52dc1a..a41d21e5a64e 100644
--- a/tools/testing/selftests/resctrl/fill_buf.c
+++ b/tools/testing/selftests/resctrl/fill_buf.c
@@ -27,6 +27,9 @@ static void sb(void)
 #if defined(__i386) || defined(__x86_64)
 	asm volatile("sfence\n\t"
 		     : : : "memory");
+#elif defined(__aarch64__)
+	asm volatile("dsb sy\n\t"
+		     : : : "memory");
 #endif
 }
 
@@ -35,6 +38,9 @@ static void cl_flush(void *p)
 #if defined(__i386) || defined(__x86_64)
 	asm volatile("clflush (%0)\n\t"
 		     : : "r"(p) : "memory");
+#elif defined(__aarch64__)
+	asm volatile("dc civac, %0\n\t"
+		     : : "r"(p) : "memory");
 #endif
 }
 
-- 
2.43.0

Re: [PATCH v3 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64

[Reinette Chatre]

+Ben

Hi Richard,

On 5/28/26 7:23 PM, Richard Cheng wrote:
> cl_flush() and sb() in fill_buf.c only have implementations for i386
> and x86_64, so on aarch64 both compile to empty functions. mem_flush()
> then walks the buffer calling a no-op cl_flush() per cache line and
> finishes with a no-op sb(), leaving any caller that expects a flushed
> buffer (e.g. CMT, L3_CAT) operating on unflushed state with no warning.
> 
> Add an aarch64 code block using the ARM equivalents:
> * "dc civac, %0" for cl_flush()
> * "dsb sy"       for sb()

Calling on Arm experts here since my superficial check found sfence to
be used for __wmb() on x86 and the Arm equivalent per
arch/arm64/include/asm/barrier.h appears to be "dsb st"?

Even so, it looks like the changes below were considered by Ben during
a previous submission but I am not able to tell if his feedback was taken
into account here.
Please see:
https://lore.kernel.org/lkml/4449219d-186f-4b5e-9f72-958d1af80f58@arm.com/
https://lore.kernel.org/lkml/5aea412c-9c7f-4692-af3e-79937956ef8c@arm.com/

> 
> Both instructions are EL0-accessible on Linux aarch64.
> 
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> ---
>  tools/testing/selftests/resctrl/fill_buf.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c
> index 19a01a52dc1a..a41d21e5a64e 100644
> --- a/tools/testing/selftests/resctrl/fill_buf.c
> +++ b/tools/testing/selftests/resctrl/fill_buf.c
> @@ -27,6 +27,9 @@ static void sb(void)
>  #if defined(__i386) || defined(__x86_64)
>  	asm volatile("sfence\n\t"
>  		     : : : "memory");
> +#elif defined(__aarch64__)
> +	asm volatile("dsb sy\n\t"
> +		     : : : "memory");
>  #endif
>  }
>  
> @@ -35,6 +38,9 @@ static void cl_flush(void *p)
>  #if defined(__i386) || defined(__x86_64)
>  	asm volatile("clflush (%0)\n\t"
>  		     : : "r"(p) : "memory");
> +#elif defined(__aarch64__)
> +	asm volatile("dc civac, %0\n\t"
> +		     : : "r"(p) : "memory");
>  #endif
>  }
>  

Reinette

Re: [PATCH v3 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64

[Ben Horgan]

Hi Reinette, Richard,

On 6/26/26 04:26, Reinette Chatre wrote:
> +Ben
> 
> Hi Richard,
> 
> On 5/28/26 7:23 PM, Richard Cheng wrote:
>> cl_flush() and sb() in fill_buf.c only have implementations for i386
>> and x86_64, so on aarch64 both compile to empty functions. mem_flush()
>> then walks the buffer calling a no-op cl_flush() per cache line and
>> finishes with a no-op sb(), leaving any caller that expects a flushed
>> buffer (e.g. CMT, L3_CAT) operating on unflushed state with no warning.
>>
>> Add an aarch64 code block using the ARM equivalents:
>> * "dc civac, %0" for cl_flush()
>> * "dsb sy"       for sb()
> 
> Calling on Arm experts here since my superficial check found sfence to
> be used for __wmb() on x86 and the Arm equivalent per
> arch/arm64/include/asm/barrier.h appears to be "dsb st"?

Referring to the arm reference manual (DDI0487 version M.a.a):
D7.5.9.15 Ordering and completion of data and instruction cache
instructions
This talks about using dsb for the synchronization and also states:
"In all cases, where the text in this section refers to a DMB or a DSB,
this means a DMB or DSB whose required access type is both loads and
stores."

Hence, in this case a "dsb st" is insufficient as the required access
type is loads but not stores. A full "dsb sy" would work to synchronize
the "dc civac".

However, I don't think "dc civac" fulfills the role of what is expected
of cl_flush().

> 
> Even so, it looks like the changes below were considered by Ben during
> a previous submission but I am not able to tell if his feedback was taken
> into account here.
> Please see:
> https://lore.kernel.org/lkml/4449219d-186f-4b5e-9f72-958d1af80f58@arm.com/
> https://lore.kernel.org/lkml/5aea412c-9c7f-4692-af3e-79937956ef8c@arm.com/

My understanding is that the resctrl selftests want to use cl_flush(),
to invalidate entries in a system level cache for testing the cache
portion bitmaps. However, the mechanism to invalidate the system level
cache is generally implementation defined.

> 
>>
>> Both instructions are EL0-accessible on Linux aarch64.
>>
>> Signed-off-by: Richard Cheng <icheng@nvidia.com>
>> ---
>>  tools/testing/selftests/resctrl/fill_buf.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c
>> index 19a01a52dc1a..a41d21e5a64e 100644
>> --- a/tools/testing/selftests/resctrl/fill_buf.c
>> +++ b/tools/testing/selftests/resctrl/fill_buf.c
>> @@ -27,6 +27,9 @@ static void sb(void)
>>  #if defined(__i386) || defined(__x86_64)
>>  	asm volatile("sfence\n\t"
>>  		     : : : "memory");
>> +#elif defined(__aarch64__)
>> +	asm volatile("dsb sy\n\t"
>> +		     : : : "memory");
>>  #endif
>>  }
>>  
>> @@ -35,6 +38,9 @@ static void cl_flush(void *p)
>>  #if defined(__i386) || defined(__x86_64)
>>  	asm volatile("clflush (%0)\n\t"
>>  		     : : "r"(p) : "memory");
>> +#elif defined(__aarch64__)
>> +	asm volatile("dc civac, %0\n\t"
>> +		     : : "r"(p) : "memory");


This will only clean to the Point of Coherency (PoC).

To quote the arm reference manual (DDI0487 version M.a.a):
D7.5.9.2 The data cache maintenance instruction (DC)

If there are caches after the Point of Coherency and FEAT_PoPS is not
implemented, then the DC CIVAC and DC CIGDVAC instructions are not
sufficient to remove all copies of a poisoned Location and it is
IMPLEMENTATION DEFINED whether any IMPLEMENTATION DEFINED mechanism
exists to remove poison from a Location.

In most systems the slc, where your MPAM cache portions are likely to
be, will be past the PoC and I'd not expect FEAT_PoPS to be implemented.

Thanks,

Ben


>>  #endif
>>  }
>>  
> 
> Reinette

Re: [PATCH v3 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64

[Ben Horgan]

Hi Reinette, Richard,

On 6/26/26 14:58, Ben Horgan wrote:
> Hi Reinette, Richard,
> 
> On 6/26/26 04:26, Reinette Chatre wrote:
>> +Ben
>>
>> Hi Richard,
>>
>> On 5/28/26 7:23 PM, Richard Cheng wrote:
>>> cl_flush() and sb() in fill_buf.c only have implementations for i386
>>> and x86_64, so on aarch64 both compile to empty functions. mem_flush()
>>> then walks the buffer calling a no-op cl_flush() per cache line and
>>> finishes with a no-op sb(), leaving any caller that expects a flushed
>>> buffer (e.g. CMT, L3_CAT) operating on unflushed state with no warning.
>>>
>>> Add an aarch64 code block using the ARM equivalents:
>>> * "dc civac, %0" for cl_flush()
>>> * "dsb sy"       for sb()
>>
>> Calling on Arm experts here since my superficial check found sfence to
>> be used for __wmb() on x86 and the Arm equivalent per
>> arch/arm64/include/asm/barrier.h appears to be "dsb st"?
> 
> Referring to the arm reference manual (DDI0487 version M.a.a):
> D7.5.9.15 Ordering and completion of data and instruction cache
> instructions
> This talks about using dsb for the synchronization and also states:
> "In all cases, where the text in this section refers to a DMB or a DSB,
> this means a DMB or DSB whose required access type is both loads and
> stores."
> 
> Hence, in this case a "dsb st" is insufficient as the required access
> type is loads but not stores. A full "dsb sy" would work to synchronize
> the "dc civac".
> 
> However, I don't think "dc civac" fulfills the role of what is expected
> of cl_flush().
> 
>>
>> Even so, it looks like the changes below were considered by Ben during
>> a previous submission but I am not able to tell if his feedback was taken
>> into account here.
>> Please see:
>> https://lore.kernel.org/lkml/4449219d-186f-4b5e-9f72-958d1af80f58@arm.com/
>> https://lore.kernel.org/lkml/5aea412c-9c7f-4692-af3e-79937956ef8c@arm.com/
> 
> My understanding is that the resctrl selftests want to use cl_flush(),
> to invalidate entries in a system level cache for testing the cache
> portion bitmaps. However, the mechanism to invalidate the system level
> cache is generally implementation defined.
> 


I have also found out that cache maintenance operations on arm64 need
only do the necessary work to maintain coherency and no performance
effects can be implied. On platforms that are known to be coherent then
they may be a NOP. Perhaps you can just do some stores to fill the cache
with junk data.

Thanks,

Ben

[PATCH v3 3/3] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT

[Richard Cheng]

aarch64 has no vendor_id in /proc/cpuinfo, so detect_vendor() returns 0
and arch_supports_noncont_cat() falls through to "return false".
L3_NONCONT_CAT therefore spuriously fails on every ARM MPAM platform.

Define ARCH_ARM, short-circuit detect_vendor() to it on aarch64, and
add it to the AMD/Hygon always-supports early-out in
arch_supports_noncont_cat().

aarch64 has many implementers (ARM 0x41, NVIDIA 0x43, etc.), but MPAM
mandates non-contiguous CPBM uniformly, so per-implementer handling is
not needed here.

Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
 tools/testing/selftests/resctrl/cat_test.c    |  9 ++++++--
 tools/testing/selftests/resctrl/resctrl.h     |  1 +
 .../testing/selftests/resctrl/resctrl_tests.c | 21 +++++++++++++++++++
 3 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
index dc414e55ae94..ce66016dbd88 100644
--- a/tools/testing/selftests/resctrl/cat_test.c
+++ b/tools/testing/selftests/resctrl/cat_test.c
@@ -292,8 +292,13 @@ static bool arch_supports_noncont_cat(const struct resctrl_test *test)
 {
 	unsigned int vendor_id = get_vendor();
 
-	/* AMD and Hygon always support non-contiguous CBM. */
-	if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON)
+	/*
+	 * AMD and Hygon always support non-contiguous CBM. ARM/MPAM defines
+	 * MPAMCFG_CPBM as a bitmap with no contiguity constraint per ARM
+	 * DDI 0598.
+	 */
+	if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON ||
+	    vendor_id == ARCH_ARM)
 		return true;
 
 #if defined(__i386__) || defined(__x86_64__) /* arch */
diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h
index afe635b6e48d..670e5b128b4d 100644
--- a/tools/testing/selftests/resctrl/resctrl.h
+++ b/tools/testing/selftests/resctrl/resctrl.h
@@ -40,6 +40,7 @@
 #define ARCH_INTEL	BIT(0)
 #define ARCH_AMD	BIT(1)
 #define ARCH_HYGON	BIT(2)
+#define ARCH_ARM	BIT(3)
 
 #define END_OF_TESTS	1
 
diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c
index dbcd5eea9fbc..cfece594a8c6 100644
--- a/tools/testing/selftests/resctrl/resctrl_tests.c
+++ b/tools/testing/selftests/resctrl/resctrl_tests.c
@@ -23,6 +23,15 @@ static struct resctrl_test *resctrl_tests[] = {
 	&l2_noncont_cat_test,
 };
 
+static bool detect_aarch64(void)
+{
+#if defined(__aarch64__)
+	return true;
+#else
+	return false;
+#endif
+}
+
 static unsigned int detect_vendor(void)
 {
 	static unsigned int vendor_id;
@@ -34,6 +43,18 @@ static unsigned int detect_vendor(void)
 	if (initialized)
 		return vendor_id;
 
+	if (detect_aarch64()) {
+		/*
+		 * aarch64 has no userspace vendor_id in /proc/cpuinfo.
+		 * MPAM-capable ARM implementations follow ARM DDI 0598;
+		 * treat all aarch64 builds as a single vendor for the
+		 * purposes of resctrl selftests.
+		 */
+		vendor_id = ARCH_ARM;
+		initialized = true;
+		return vendor_id;
+	}
+
 	inf = fopen("/proc/cpuinfo", "r");
 	if (!inf) {
 		vendor_id = 0;
-- 
2.43.0

Re: [PATCH v3 3/3] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 3451 bytes --]

On Fri, 29 May 2026, Richard Cheng wrote:

> aarch64 has no vendor_id in /proc/cpuinfo, so detect_vendor() returns 0
> and arch_supports_noncont_cat() falls through to "return false".
> L3_NONCONT_CAT therefore spuriously fails on every ARM MPAM platform.
> 
> Define ARCH_ARM, short-circuit detect_vendor() to it on aarch64, and
> add it to the AMD/Hygon always-supports early-out in
> arch_supports_noncont_cat().
> 
> aarch64 has many implementers (ARM 0x41, NVIDIA 0x43, etc.), but MPAM
> mandates non-contiguous CPBM uniformly, so per-implementer handling is
> not needed here.
> 
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> ---
>  tools/testing/selftests/resctrl/cat_test.c    |  9 ++++++--
>  tools/testing/selftests/resctrl/resctrl.h     |  1 +
>  .../testing/selftests/resctrl/resctrl_tests.c | 21 +++++++++++++++++++
>  3 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
> index dc414e55ae94..ce66016dbd88 100644
> --- a/tools/testing/selftests/resctrl/cat_test.c
> +++ b/tools/testing/selftests/resctrl/cat_test.c
> @@ -292,8 +292,13 @@ static bool arch_supports_noncont_cat(const struct resctrl_test *test)
>  {
>  	unsigned int vendor_id = get_vendor();
>  
> -	/* AMD and Hygon always support non-contiguous CBM. */
> -	if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON)
> +	/*
> +	 * AMD and Hygon always support non-contiguous CBM. ARM/MPAM defines
> +	 * MPAMCFG_CPBM as a bitmap with no contiguity constraint per ARM
> +	 * DDI 0598.
> +	 */
> +	if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON ||
> +	    vendor_id == ARCH_ARM)
>  		return true;
>  
>  #if defined(__i386__) || defined(__x86_64__) /* arch */
> diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h
> index afe635b6e48d..670e5b128b4d 100644
> --- a/tools/testing/selftests/resctrl/resctrl.h
> +++ b/tools/testing/selftests/resctrl/resctrl.h
> @@ -40,6 +40,7 @@
>  #define ARCH_INTEL	BIT(0)
>  #define ARCH_AMD	BIT(1)
>  #define ARCH_HYGON	BIT(2)
> +#define ARCH_ARM	BIT(3)
>  
>  #define END_OF_TESTS	1
>  
> diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c
> index dbcd5eea9fbc..cfece594a8c6 100644
> --- a/tools/testing/selftests/resctrl/resctrl_tests.c
> +++ b/tools/testing/selftests/resctrl/resctrl_tests.c
> @@ -23,6 +23,15 @@ static struct resctrl_test *resctrl_tests[] = {
>  	&l2_noncont_cat_test,
>  };
>  
> +static bool detect_aarch64(void)
> +{
> +#if defined(__aarch64__)
> +	return true;
> +#else
> +	return false;
> +#endif
> +}
> +
>  static unsigned int detect_vendor(void)
>  {
>  	static unsigned int vendor_id;
> @@ -34,6 +43,18 @@ static unsigned int detect_vendor(void)
>  	if (initialized)
>  		return vendor_id;
>  
> +	if (detect_aarch64()) {
> +		/*
> +		 * aarch64 has no userspace vendor_id in /proc/cpuinfo.
> +		 * MPAM-capable ARM implementations follow ARM DDI 0598;
> +		 * treat all aarch64 builds as a single vendor for the
> +		 * purposes of resctrl selftests.
> +		 */
> +		vendor_id = ARCH_ARM;
> +		initialized = true;
> +		return vendor_id;
> +	}
> +
>  	inf = fopen("/proc/cpuinfo", "r");
>  	if (!inf) {
>  		vendor_id = 0;
> 

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

-- 
 i.

Re: [PATCH v3 3/3] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT

[Reinette Chatre]

Hi Richard,

On 5/28/26 7:23 PM, Richard Cheng wrote:
> aarch64 has no vendor_id in /proc/cpuinfo, so detect_vendor() returns 0
> and arch_supports_noncont_cat() falls through to "return false".
> L3_NONCONT_CAT therefore spuriously fails on every ARM MPAM platform.
> 
> Define ARCH_ARM, short-circuit detect_vendor() to it on aarch64, and
> add it to the AMD/Hygon always-supports early-out in
> arch_supports_noncont_cat().
> 
> aarch64 has many implementers (ARM 0x41, NVIDIA 0x43, etc.), but MPAM
> mandates non-contiguous CPBM uniformly, so per-implementer handling is
> not needed here.
> 
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> ---

Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>

Reinette

Re: [PATCH v3 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64

[Richard Cheng]

On Fri, May 29, 2026 at 10:23:48AM +0800, Richard Cheng wrote:
> This series fixes numerous issues in the resctrl selftests on aarch64,
> where they currently misreport failures.
> 
> Patch 1 skips L3_CAT at feature-check time when MPAM legitimately
> reports every CBM bit as shareable, instead of failing the test.
> 
> Patch 2 adds aarch64 implementations of cl_flush() and sb() in
> fill_buf.c so cache flushes are no longer silent no-ops.
> 
> Patch 3 teaches detect_vendor() about aarch64 (which exposes no
> vendor_id in /proc/cpuinfo) and lets arch_supports_noncont_cat()
> return true for ARM, fixing spurious L3_NONCONT_CAT failures.
> 
> Changes since v2:
>     - Patch 1: add Ilpo's Reviewed-by.
>     - Patch 3: factor the aarch64 check into a detect_aarch64() helper
>       instead of an inline #ifdef in detect_vendor().
>     - Fix the patch ordering in this cover letter to match the series.
> 
> Richard Cheng (3):
>   selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists
>   selftests/resctrl: Implement cl_flush() and sb() for aarch64
>   selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT
> 
>  tools/testing/selftests/resctrl/cat_test.c    | 32 +++++++++++++++++--
>  tools/testing/selftests/resctrl/fill_buf.c    |  6 ++++
>  tools/testing/selftests/resctrl/resctrl.h     |  1 +
>  .../testing/selftests/resctrl/resctrl_tests.c | 21 ++++++++++++
>  4 files changed, 57 insertions(+), 3 deletions(-)
> 
> -- 
> 2.43.0
>

Sorry forgot to cc Ilpo.

+Cc. Ilpo Järvinen

Best regards,
Richard Cheng.