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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Daniel Lezcano <daniel.lezcano@kernel.org>,
	Zhang Rui <rui.zhang@intel.com>,
	Lukasz Luba <lukasz.luba@arm.com>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	Amit Kucheria <amitk@kernel.org>,
	Thara Gopinath <thara.gopinath@gmail.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Abel Vesa <abelvesa@kernel.org>
Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-arm-msm@vger.kernel.org,
	Amit Kucheria <amit.kucheria@oss.qualcomm.com>
Subject: Re: [PATCH 4/6] thermal: qcom: tsens: add hardware-bin trip-point filtering
Date: Fri, 30 Oct 2026 13:38:00 +0100	[thread overview]
Message-ID: <310594f7-fd4f-480c-a2f9-844e3da73b0a@oss.qualcomm.com> (raw)
In-Reply-To: <991e6b64-8741-4669-9bbf-e31eed788f42@oss.qualcomm.com>

[-- Attachment #1: Type: text/plain, Size: 2720 bytes --]

On 10/27/26 1:59 PM, Gaurav Kohli wrote:
> 
> 
> On 10/26/2026 5:21 PM, Konrad Dybcio wrote:
>> On 10/23/26 12:01 PM, Gaurav Kohli wrote:
>>>
>>>
>>> On 10/22/2026 2:39 PM, Konrad Dybcio wrote:
>>>> On 10/2/26 12:46 PM, Gaurav Kohli wrote:
>>>>> From: Amit Kucheria <amit.kucheria@oss.qualcomm.com>
>>>>>
>>>>> Some Qualcomm SoCs are binned at manufacturing time and expose the bin
>>>>> in qfprom fuses.  The thermal core's supported_hw_bin mechanism filters
>>>>> trip points by hardware version; wire tsens up to feed it.
>>>>
>>>> [...]
>>>>
>>>>> +    /* Hardware-bin values for thermal-hw-bin matching in DT. */
>>>>> +    const u32 hw_bin_std = 0x1;
>>>>> +    const u32 hw_bin_elevated = 0x2;
>>>>> +
>>>>> +    /* Higher thermal profile identification for qcm6490/sc7280 bins. */
>>>>> +    const u32 tsens_chip_id0 = 0x197;
>>>>> +    const u32 tsens_chip_id1 = 0x198;
>>>>> +    const u32 tsens_chip_id2 = 0x20e;
>>>>> +    const u32 tsens_chip_id3 = 0x20f;
>>>>> +    const u8 tsens_feat_id2 = 0x2;
>>>>> +    const u8 tsens_feat_id3 = 0x3;
>>>>> +    const u8 tsens_feat_id4 = 0x4;
>>>>
>>>> Isn't that (also) exposed over SMEM?
>>>
>>> Thanks Konrad, for review.
>>>
>>> SMEM has related socinfo data, but there is no exported helper for the
>>> exact fields needed here, such as feat-id, which is also used as the bin
>>> value.
>>
>> Is that different to qcom_smem_get_feature_code()?
> 
> Thanks for review.
> I am checking internally and will update with the exact difference from
> feat-id. My understanding is that qcom_smem_get_feature_code() returns
> the SMEM socinfo feature_code, while this code needs the QFPROM feat-id
> field from the JTAG ID fuse word.

I traced down some code, only managed to find the sources for newer
SoCs. The JTAG ID is present in socinfo->raw_id. I have a Kodiak
(QCM6490) phone on my desk - the JTAG_ID part of the fuse reads as
0x197 and the socinfo data reads the same. I attached a patch for you.

The feature ID is not exposed via SMEM to the best of my knowledge so
it needs to stay as a fuse.

Konrad

> For this series, would prefer to keep the fuse-based path. The same
> binding is also used by the generic i-temp fuse bit for Hamoa/future
> targets, while the jtag-id/feat-id decoding remains only the
> Kodiak/QCM6490-specific callback. Please let me know if you are fine with this approach.
>>
>>> This jtag-id/feat-id decoding is Kodiak/QCM6490-specific, and the
>>> thermal-bin mapping needs both values. Other/future targets are expected
>>> to use only the generic i-temp fuse bit, like Hamoa.
>>
>> So there are variants of kodiak that ""incorrectly"" set the feat_id?
> 
> No, Kodiak is not incorrectly setting it.

[-- Attachment #2: 0001-soc-qcom-socinfo-Export-JTAG-ID.patch --]
[-- Type: text/x-patch, Size: 2864 bytes --]

From be8bba1e58dc169079567a6d506ba0f4010b29e5 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Date: Fri, 30 Oct 2026 13:22:46 +0100
Subject: [PATCH] soc: qcom: socinfo: Export JTAG ID

The JTAG ("raw") ID of the SoC is different from the "socinfo ID". Some
consumers need to consume the former. Export it in debugfs and via a
getter.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 drivers/soc/qcom/smem.c       | 22 ++++++++++++++++++++++
 drivers/soc/qcom/socinfo.c    |  6 +++++-
 include/linux/soc/qcom/smem.h |  1 +
 3 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index b5e7bd8c1512..6659f1996b26 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drivers/soc/qcom/smem.c
@@ -870,6 +870,28 @@ int qcom_smem_get_feature_code(u32 *code)
 }
 EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code);
 
+/**
+ * qcom_smem_get_jtag_id() - return the JTAG/raw ID
+ * @id:	On success, we return the SoC JTAG here.
+ *
+ * Look up the JTAG ID from HW/SW build ID and return it.
+ *
+ * Return: 0 on success, negative errno on failure.
+ */
+int qcom_smem_get_jtag_id(u32 *id)
+{
+	struct socinfo *info;
+
+	info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL);
+	if (IS_ERR(info))
+		return PTR_ERR(info);
+
+	*id = __le32_to_cpu(info->raw_id);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(qcom_smem_get_jtag_id);
+
 static int qcom_smem_get_sbl_version(struct qcom_smem *smem)
 {
 	struct smem_header *header;
diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index 38efc5db7fa8..aeac716f639a 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -211,6 +211,7 @@ struct socinfo_params {
 	u32 chip_family;
 	u32 foundry_id;
 	u32 plat_ver;
+	u32 raw_id;
 	u32 raw_ver;
 	u32 hw_plat;
 	u32 fmt;
@@ -844,8 +845,11 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
 				   &qcom_socinfo->info.hw_plat);
 		fallthrough;
 	case SOCINFO_VERSION(0, 2):
-		qcom_socinfo->info.raw_ver  = __le32_to_cpu(info->raw_ver);
+		qcom_socinfo->info.raw_id  = __le32_to_cpu(info->raw_id);
+		qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver);
 
+		debugfs_create_u32("raw_id", 0444, qcom_socinfo->dbg_root,
+				   &qcom_socinfo->info.raw_id);
 		debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root,
 				   &qcom_socinfo->info.raw_ver);
 		fallthrough;
diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h
index 3249cbd2016b..5d7a3cfb2000 100644
--- a/include/linux/soc/qcom/smem.h
+++ b/include/linux/soc/qcom/smem.h
@@ -14,6 +14,7 @@ phys_addr_t qcom_smem_virt_to_phys(void *p);
 
 int qcom_smem_get_soc_id(u32 *id);
 int qcom_smem_get_feature_code(u32 *code);
+int qcom_smem_get_jtag_id(u32 *id);
 
 int qcom_smem_bust_hwspin_lock_by_host(unsigned int host);
 
-- 
2.56.0


  reply	other threads:[~2026-10-30 12:38 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-02 10:46 [PATCH 0/6] thermal: Add hardware-binned trip point support Gaurav Kohli
2026-10-02 10:46 ` [PATCH 1/6] dt-bindings: thermal: thermal-zones: add hardware-binning trip properties Gaurav Kohli
2026-10-13  6:24   ` Krzysztof Kozlowski
2026-10-19 14:09     ` Gaurav Kohli
2026-10-02 10:46 ` [PATCH 2/6] thermal: add hardware-binning trip-point filtering support Gaurav Kohli
2026-10-02 10:46 ` [PATCH 3/6] dt-bindings: thermal: qcom-tsens: document qcm6490 tsens Gaurav Kohli
2026-10-02 10:46 ` [PATCH 4/6] thermal: qcom: tsens: add hardware-bin trip-point filtering Gaurav Kohli
2026-10-22  9:09   ` Konrad Dybcio
2026-10-23 10:01     ` Gaurav Kohli
2026-10-26 11:51       ` Konrad Dybcio
2026-10-27 12:59         ` Gaurav Kohli
2026-10-30 12:38           ` Konrad Dybcio [this message]
2026-10-02 10:47 ` [PATCH 5/6] arm64: dts: qcom: kodiak: use thermal hw-bin trips Gaurav Kohli
2026-10-22  9:09   ` Konrad Dybcio
2026-10-22 13:39     ` Gaurav Kohli
2026-10-02 10:47 ` [PATCH 6/6] arm64: dts: qcom: hamoa: add thermal hw-bin support Gaurav Kohli

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