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From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Li Ming <ming.li@zohomail.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing
Date: Thu, 29 Oct 2026 18:33:05 -0700	[thread overview]
Message-ID: <34632b64-c86f-4853-8d1f-8e75ae674398@nvidia.com> (raw)
In-Reply-To: <37c6f2bc-53b3-4260-aa27-04f89c45e950@zohomail.com>

On 10/27/26 8:01 PM, Li Ming wrote:
>> +     if (PCI_POSSIBLE_ERROR(status2))
>> +             return -ENODEV;
>> +     if (status2 & PCI_DVSEC_CXL_CACHE_INV)
>> +             return 0;
> I think checking again after deadline is not needed, if it usually
> happens, it means we should adjust CXL_CACHE_WBI_TIMEOUT_US.
>> +
>> +     return -ETIMEDOUT;
> It is better to output a warning before returning -ETIMEDOUT.
>> +}
Ack. Fixes this in v16 and added warining.

>> +
>> +     idx = FIELD_GET(PCI_DVSEC_CXL_RST_TIMEOUT, cap);
>> +     if (idx >= ARRAY_SIZE(cxl_reset_timeout_ms)) {
>> +             pci_warn(pdev,
>> +                      "unknown CXL reset timeout encoding %d; using 
>> %u ms\n",
>> +                      idx, CXL_RESET_MAX_WAIT_MS);
>> +             idx = ARRAY_SIZE(cxl_reset_timeout_ms) - 1;
>> +     }
>> +
> I noticed that the worst situation is that we have to wait cxl reset
> done for 100s. If my understanding is correct, userspace would hang on
> "echo 1 > reset" until reset done. Is it better to add a pci_info() here
> to output the reset timeout value?

Done. Added a log print.

-- 
Regards,
Srirangan

  parent reply	other threads:[~2026-10-30  1:33 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-11  2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-27  4:13   ` Alison Schofield
2026-10-11  2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-26 22:20   ` Dave Jiang
2026-10-27  6:23   ` Li Ming
2026-10-11  2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-26 22:32   ` Dave Jiang
2026-10-27  6:24   ` Li Ming
2026-10-11  2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-26 22:41   ` Dave Jiang
2026-10-27  6:31   ` Li Ming
2026-10-11  2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-26 22:56   ` Dave Jiang
2026-10-27  6:50   ` Li Ming
2026-10-11  2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-27  8:07   ` Li Ming
2026-10-29  3:19   ` Alison Schofield
2026-10-30  1:11     ` Srirangan Madhavan
2026-10-29  7:02   ` Li Ming
2026-10-11  2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-28  3:01   ` Li Ming
2026-10-30  1:23     ` Srirangan Madhavan
2026-10-30  1:33     ` Srirangan Madhavan [this message]
2026-10-11  2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-27  3:25   ` Alison Schofield
2026-10-29 23:47     ` Srirangan Madhavan
2026-10-27  4:32   ` Alison Schofield
2026-10-30  1:43     ` Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-27  3:56   ` Alison Schofield
2026-10-30  0:46     ` Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-27  2:41   ` Alison Schofield
2026-10-30  0:48     ` Srirangan Madhavan

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