From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset
Date: Thu, 29 Oct 2026 18:43:13 -0700 [thread overview]
Message-ID: <370ae30d-8550-44d8-9191-e9638508b291@nvidia.com> (raw)
In-Reply-To: <auApYR-A3qihqLbP@aschofie-mobl2.lan>
On 10/26/26 9:32 PM, Alison Schofield wrote:
>> The range handling and region-quiesce structure follow Dave Jiang's
>> reference implementation on his cxl-type2-reset branch.
>>
>> Link:https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/
>> commit/?id=5944c6e61f14c0dd28d54537be15edb2cadb0e8b
>> Suggested-by: Dave Jiang<dave.jiang@intel.com>
>> Signed-off-by: Srirangan Madhavan<smadhavan@nvidia.com>
> Hi Srirangan,
>
> Please revisit the tags and the inclusion of a link to DaveJ's
> private branch.
>
> If DaveJ contributed code that you used, then the tags would be
> Co-developed-by: DaveJ followed by Signed-off-by: DaveJ.
> (Assuming it was non trivial which seems true based on branch)
>
> If DaveJ only suggested you create the patch, ie, you need this
> functionality, then it's Suggested-by.
>
> I'm not sure you should include the links in the commit log since
> they are to a private git tree. Maybe just include below the line.
> Those links are on more patches than just the ones you added
> DaveJ as Suggested-by, so very that is odd too.
>
> Anyway, that's for you and DaveJ to sort out 🙂
>
> -- Alison
Hi Alison!
Thanks for pointing it out. I put suggested-by and linked Dave's branch
as I wasn't sure what the right tags were.
I moved the reference-branch links below the patch separator (I can
remove them altogether if they are not useful) and removed Dave’s
Suggested-by tags in v16.
Checkpatch was complaining about Co-developed-by tag without his
accompanying Signed-off-by. I'll reinsert them once I get ack.
Dave, the refactor starts at v15 patch 6; after the split, the related
v16 patches are 6–13, 15, and 17. Would Co-developed-by be appropriate
for any of these, and can I add the Signed-off-by for the applicable
patches?
--
Regards,
Srirangan
next prev parent reply other threads:[~2026-10-30 1:43 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-11 2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-27 4:13 ` Alison Schofield
2026-10-11 2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-26 22:20 ` Dave Jiang
2026-10-27 6:23 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-26 22:32 ` Dave Jiang
2026-10-27 6:24 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-26 22:41 ` Dave Jiang
2026-10-27 6:31 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-26 22:56 ` Dave Jiang
2026-10-27 6:50 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-27 8:07 ` Li Ming
2026-10-29 3:19 ` Alison Schofield
2026-10-30 1:11 ` Srirangan Madhavan
2026-10-29 7:02 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-28 3:01 ` Li Ming
2026-10-30 1:23 ` Srirangan Madhavan
2026-10-30 1:33 ` Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-27 3:25 ` Alison Schofield
2026-10-29 23:47 ` Srirangan Madhavan
2026-10-27 4:32 ` Alison Schofield
2026-10-30 1:43 ` Srirangan Madhavan [this message]
2026-10-11 2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-27 3:56 ` Alison Schofield
2026-10-30 0:46 ` Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-27 2:41 ` Alison Schofield
2026-10-30 0:48 ` Srirangan Madhavan
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