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From: Li Ming <ming.li@zohomail.com>
To: Srirangan Madhavan <smadhavan@nvidia.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org,
	Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Subject: Re: [PATCH v14 02/16] cxl: Share CXL port upstream PCI device lookup
Date: Wed, 7 Oct 2026 20:22:12 +0800	[thread overview]
Message-ID: <4d2c765a-0d77-49f9-8e6e-4d80137df513@zohomail.com> (raw)
In-Reply-To: <20261001092227.3004747-3-smadhavan@nvidia.com>


在 2026/10/1 17:22, Srirangan Madhavan 写道:
> read_cdat_data() resolves a CXL port's upstream device to its backing PCI
> device. HDM cache updates need the same mapping.
>
> Factor the lookup into cxl_port_get_uport_pci_dev() and return a referenced
> PCI device to make caller ownership explicit.
>
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>

Reviewed-by: Li Ming <ming.li@zohomail.com>


pci.h provides a __free() based cleanup function for pci_dev_put().

I think you can use "struct pci_dev *pdev __free(pci_dev_put) = 
cxl_port_get_uport_pci_dev(port);" and drop all pci_dev_put() below.

> ---
>   drivers/cxl/core/core.h |  1 +
>   drivers/cxl/core/pci.c  | 19 +++++--------------
>   drivers/cxl/core/port.c | 26 ++++++++++++++++++++++++++
>   3 files changed, 32 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 35eaf636adc9..983d7690c3a5 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -157,6 +157,7 @@ long cxl_pci_get_latency(struct pci_dev *pdev);
>   int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c);
>   int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
>   					struct access_coordinate *c);
> +struct pci_dev *cxl_port_get_uport_pci_dev(struct cxl_port *port);
>   
>   static inline struct device *port_to_host(struct cxl_port *port)
>   {
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 9d807c1a002c..99c8b02d42e5 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -564,26 +564,13 @@ static unsigned char cdat_checksum(void *buf, size_t size)
>    */
>   void read_cdat_data(struct cxl_port *port)
>   {
> -	struct device *uport = port->uport_dev;
> +	struct pci_dev *pdev = cxl_port_get_uport_pci_dev(port);
>   	struct device *dev = &port->dev;
>   	struct pci_doe_mb *doe_mb;
> -	struct pci_dev *pdev = NULL;
> -	struct cxl_memdev *cxlmd;
>   	struct cdat_doe_rsp *buf;
>   	size_t table_length, length;
>   	int rc;
>   
> -	if (is_cxl_memdev(uport)) {
> -		struct device *host;
> -
> -		cxlmd = to_cxl_memdev(uport);
> -		host = cxlmd->dev.parent;
> -		if (dev_is_pci(host))
> -			pdev = to_pci_dev(host);
> -	} else if (dev_is_pci(uport)) {
> -		pdev = to_pci_dev(uport);
> -	}
> -
>   	if (!pdev)
>   		return;
>   
> @@ -591,6 +578,7 @@ void read_cdat_data(struct cxl_port *port)
>   				      CXL_DOE_PROTOCOL_TABLE_ACCESS);
>   	if (!doe_mb) {
>   		dev_dbg(dev, "No CDAT mailbox\n");
> +		pci_dev_put(pdev);
>   		return;
>   	}
>   
> @@ -598,6 +586,7 @@ void read_cdat_data(struct cxl_port *port)
>   
>   	if (cxl_cdat_get_length(dev, doe_mb, &length)) {
>   		dev_dbg(dev, "No CDAT length\n");
> +		pci_dev_put(pdev);
>   		return;
>   	}
>   
> @@ -625,11 +614,13 @@ void read_cdat_data(struct cxl_port *port)
>   	port->cdat.table = buf->data;
>   	port->cdat.length = length;
>   
> +	pci_dev_put(pdev);
>   	return;
>   err:
>   	/* Don't leave table data allocated on error */
>   	devm_kfree(dev, buf);
>   	dev_err(dev, "Failed to read/validate CDAT.\n");
> +	pci_dev_put(pdev);
>   }
>   EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL");
>   
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 625e4aa427db..5dc2815d82d8 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -34,6 +34,32 @@
>   static DEFINE_IDA(cxl_port_ida);
>   static DEFINE_XARRAY(cxl_root_buses);
>   
> +/**
> + * cxl_port_get_uport_pci_dev - get the PCI device for a port's upstream device
> + * @port: CXL port to map to a PCI device
> + *
> + * Return: A referenced PCI device, or NULL if the upstream device is not PCI.
> + * The caller must release the returned reference with pci_dev_put().
> + */
> +struct pci_dev *cxl_port_get_uport_pci_dev(struct cxl_port *port)
> +{
> +	struct device *uport = port->uport_dev;
> +	struct device *host;
> +
> +	if (is_cxl_memdev(uport)) {
> +		struct cxl_memdev *cxlmd = to_cxl_memdev(uport);
> +
> +		host = cxlmd->dev.parent;
> +	} else {
> +		host = uport;
> +	}
> +
> +	if (!host || !dev_is_pci(host))
> +		return NULL;
> +
> +	return pci_dev_get(to_pci_dev(host));
> +}
> +
>   /*
>    * The terminal device in PCI is NULL and @platform_bus
>    * for platform devices (for cxl_test)

  parent reply	other threads:[~2026-10-07 12:22 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-01  9:22 [PATCH v14 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-02  9:33   ` Richard Cheng
2026-10-07 12:07   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-02  9:48   ` Richard Cheng
2026-10-07 12:22   ` Li Ming [this message]
2026-10-11  2:54     ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-02  9:49   ` Richard Cheng
2026-10-07 12:29   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-02 10:17   ` Richard Cheng
2026-10-11  2:38     ` Srirangan Madhavan
2026-10-02 19:07   ` Dave Jiang
2026-10-07 12:34   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 05/16] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-10-02 19:59   ` Dave Jiang
2026-10-07 13:12     ` Li Ming
2026-10-07 16:23       ` Dave Jiang
2026-10-08 13:18         ` Li Ming
2026-10-08 15:19           ` Dave Jiang
2026-10-09 14:41             ` Li Ming
2026-10-11  2:48             ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 06/16] cxl: Move HDM decoder helpers to built-in resource code Srirangan Madhavan
2026-10-05 21:42   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-02 21:46   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 08/16] cxl: Reject overflowing HDM decoder ranges Srirangan Madhavan
2026-10-02 21:50   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 09/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-02 23:57   ` Dave Jiang
2026-10-11  2:52     ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 10/16] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-06 15:39   ` Dave Jiang
2026-10-07 19:37     ` Alison Schofield
2026-10-11  2:45       ` Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 11/16] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 12/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-02  8:06   ` Richard Cheng
2026-10-11  2:35     ` Srirangan Madhavan
2026-10-07 19:44   ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 13/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-08 23:33   ` Bjorn Helgaas
2026-10-01  9:22 ` [PATCH v14 14/16] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-07 19:49   ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 15/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 16/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-08 23:35   ` Bjorn Helgaas

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