From: Dave Hansen <dave.hansen@intel.com>
To: Borislav Petkov <bp@alien8.de>,
Colin Mitchell <colinmitchell@google.com>
Cc: chang.seok.bae@intel.com, dave.hansen@linux.intel.com,
linux-kernel@vger.kernel.org, mingo@redhat.com,
tglx@linutronix.de, x86@kernel.org
Subject: Re: [PATCH 0/6] x86/microcode: Support for Intel Staging Feature
Date: Fri, 28 Feb 2025 15:23:53 -0800 [thread overview]
Message-ID: <526df712-6091-4b04-97d5-9007789dc750@intel.com> (raw)
In-Reply-To: <20250228225236.GHZ8I-NBTC6L6Qc-iM@fat_crate.local>
On 2/28/25 14:52, Borislav Petkov wrote:
> On Fri, Feb 28, 2025 at 02:27:15PM -0800, Colin Mitchell wrote:
>> As a potential user, I'd advocate for an option to disable legacy
>> loading if staging is supported.
> What happens if staging is failing indefinitely, for whatever reason?
>
> You can't load any microcode anymore if you've disabled the legacy method
> too.
Yeah, I'm perplexed by this choice too.
You seem to be saying that you'd rather be (for instance) insecure
running old microcode than have the latency blip from a legacy microcode
load.
What action would you take if a staging-load fails? Retry again a few
times? Go back to the CPU vendor and get a new image? Or just ignore it?
next prev parent reply other threads:[~2025-02-28 23:23 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-01 16:10 [PATCH RFC 0/7] " Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 1/7] x86/microcode/intel: Remove unnecessary cache writeback and invalidation Chang S. Bae
2024-10-25 16:24 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 2/7] x86/microcode: Introduce staging option to reduce late-loading latency Chang S. Bae
2024-11-04 10:45 ` Borislav Petkov
2024-10-01 16:10 ` [PATCH RFC 3/7] x86/msr-index: Define MSR index and bit for the microcode staging feature Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2024-11-04 11:16 ` Borislav Petkov
2024-11-04 16:08 ` Dave Hansen
2024-11-04 18:34 ` Chang S. Bae
2024-11-04 20:10 ` Chang S. Bae
2024-11-06 18:23 ` [PATCH] cpufreq: Simplify MSR read on the boot CPU Chang S. Bae
2024-11-12 20:44 ` Rafael J. Wysocki
2024-11-06 18:28 ` [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2024-11-07 1:12 ` Thomas Gleixner
2024-11-08 22:42 ` Chang S. Bae
2024-11-08 22:51 ` Dave Hansen
2024-10-01 16:10 ` [PATCH RFC 5/7] x86/microcode/intel_staging: Implement staging logic Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 6/7] x86/microcode/intel_staging: Support mailbox data transfer Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 7/7] x86/microcode/intel: Enable staging when available Chang S. Bae
2024-12-11 1:42 ` [PATCH 0/6] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2024-12-11 1:42 ` [PATCH 1/6] x86/microcode: Introduce staging option to reduce late-loading latency Chang S. Bae
2025-02-17 13:33 ` Borislav Petkov
2025-02-18 7:51 ` Chang S. Bae
2025-02-18 11:36 ` Borislav Petkov
2025-02-18 15:16 ` Dave Hansen
2024-12-11 1:42 ` [PATCH 2/6] x86/msr-index: Define MSR index and bit for the microcode staging feature Chang S. Bae
2025-02-26 17:19 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 3/6] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2025-02-26 17:52 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 4/6] x86/microcode/intel_staging: Implement staging logic Chang S. Bae
2025-02-18 20:16 ` Dave Hansen
2025-02-26 17:56 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 5/6] x86/microcode/intel_staging: Support mailbox data transfer Chang S. Bae
2025-02-18 20:54 ` Dave Hansen
2025-03-20 23:42 ` Chang S. Bae
2024-12-11 1:42 ` [PATCH 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-02-07 18:37 ` [PATCH 0/6] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2025-02-28 22:27 ` Colin Mitchell
2025-02-28 22:52 ` Borislav Petkov
2025-02-28 23:23 ` Dave Hansen [this message]
2025-03-26 21:29 ` Colin Mitchell
2025-04-02 17:14 ` Dave Hansen
2025-02-28 23:05 ` Dave Hansen
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