From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>, Borislav Petkov <bp@alien8.de>
Cc: <linux-kernel@vger.kernel.org>, <x86@kernel.org>,
<mingo@redhat.com>, <dave.hansen@linux.intel.com>
Subject: Re: [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging
Date: Fri, 8 Nov 2024 14:42:58 -0800 [thread overview]
Message-ID: <dcb6d46d-c34d-4921-a881-ad8705d7129c@intel.com> (raw)
In-Reply-To: <871pznq229.ffs@tglx>
On 11/6/2024 5:12 PM, Thomas Gleixner wrote:
>
> This looks all overly complicated. The documentation says:
>
> "There is one set of mailbox registers and internal staging buffers per
> physical processor package. Therefore, the IA32_MCU_STAGING_MBOX_ADDR
> MSR is package-scoped and will provide a different physical address on
> each physical package."
>
> So why going through loops and hoops?
While the initial approach was like the one below, the aspect I bought
was to avoid relying on topology knowledge by simply searching for
unique addresses. But you're right -- this introduces unnecessary loops,
complicating the code anyway.
I should have explicitly highlighted this as a review point, so thank
you for taking a closer look and correcting the approach.
Given that the scope is clearly stated in the spec as packaged-scoped
and should be permanent, I think there is no question in leveraging it
to make the code simple as you suggested:
>
> pkg_id = UINT_MAX;
>
> for_each_online_cpu(cpu) {
> if (topology_logical_package_id(cpu) == pkg_id)
> continue;
> pkg_id = topology_logical_package_id(cpu);
>
> rdmsrl_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &pa);
> staging_work(pa, ucode_patch_late, totalsize);
> }
>
> Something like that should just work, no?
Yes, indeed.
Then I observed the package number repeated according to the CPU number
mapping. For example, all SMT sibling threads map in the later CPU numbers.
Unless staging redundancy is intentional, it can be avoided by tracking
package ids. But, in this case, the loop may be streamlined to SMT
primary threads instead of all online CPUs, since core::setup_cpus()
already ensures primary threads are online. Perhaps,
/*
* The MMIO address is unique per package, and all the SMT
* primary threads are ensured online. Find staging addresses
* by their package ids.
*/
for_each_cpu(cpu, cpu_primary_thread_mask) {
...
}
Thanks,
Chang
next prev parent reply other threads:[~2024-11-08 22:43 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-01 16:10 [PATCH RFC 0/7] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 1/7] x86/microcode/intel: Remove unnecessary cache writeback and invalidation Chang S. Bae
2024-10-25 16:24 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 2/7] x86/microcode: Introduce staging option to reduce late-loading latency Chang S. Bae
2024-11-04 10:45 ` Borislav Petkov
2024-10-01 16:10 ` [PATCH RFC 3/7] x86/msr-index: Define MSR index and bit for the microcode staging feature Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2024-11-04 11:16 ` Borislav Petkov
2024-11-04 16:08 ` Dave Hansen
2024-11-04 18:34 ` Chang S. Bae
2024-11-04 20:10 ` Chang S. Bae
2024-11-06 18:23 ` [PATCH] cpufreq: Simplify MSR read on the boot CPU Chang S. Bae
2024-11-12 20:44 ` Rafael J. Wysocki
2024-11-06 18:28 ` [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2024-11-07 1:12 ` Thomas Gleixner
2024-11-08 22:42 ` Chang S. Bae [this message]
2024-11-08 22:51 ` Dave Hansen
2024-10-01 16:10 ` [PATCH RFC 5/7] x86/microcode/intel_staging: Implement staging logic Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 6/7] x86/microcode/intel_staging: Support mailbox data transfer Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 7/7] x86/microcode/intel: Enable staging when available Chang S. Bae
2024-12-11 1:42 ` [PATCH 0/6] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2024-12-11 1:42 ` [PATCH 1/6] x86/microcode: Introduce staging option to reduce late-loading latency Chang S. Bae
2025-02-17 13:33 ` Borislav Petkov
2025-02-18 7:51 ` Chang S. Bae
2025-02-18 11:36 ` Borislav Petkov
2025-02-18 15:16 ` Dave Hansen
2024-12-11 1:42 ` [PATCH 2/6] x86/msr-index: Define MSR index and bit for the microcode staging feature Chang S. Bae
2025-02-26 17:19 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 3/6] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2025-02-26 17:52 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 4/6] x86/microcode/intel_staging: Implement staging logic Chang S. Bae
2025-02-18 20:16 ` Dave Hansen
2025-02-26 17:56 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 5/6] x86/microcode/intel_staging: Support mailbox data transfer Chang S. Bae
2025-02-18 20:54 ` Dave Hansen
2025-03-20 23:42 ` Chang S. Bae
2024-12-11 1:42 ` [PATCH 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-02-07 18:37 ` [PATCH 0/6] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2025-02-28 22:27 ` Colin Mitchell
2025-02-28 22:52 ` Borislav Petkov
2025-02-28 23:23 ` Dave Hansen
2025-03-26 21:29 ` Colin Mitchell
2025-04-02 17:14 ` Dave Hansen
2025-02-28 23:05 ` Dave Hansen
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