From: Dave Hansen <dave.hansen@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>,
"Chang S. Bae" <chang.seok.bae@intel.com>,
Borislav Petkov <bp@alien8.de>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org, mingo@redhat.com,
dave.hansen@linux.intel.com
Subject: Re: [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging
Date: Fri, 8 Nov 2024 14:51:39 -0800 [thread overview]
Message-ID: <aca2cbc5-35fd-4662-afe3-7d2642a5e9f8@intel.com> (raw)
In-Reply-To: <871pznq229.ffs@tglx>
On 11/6/24 17:12, Thomas Gleixner wrote:
> This looks all overly complicated. The documentation says:
>
> "There is one set of mailbox registers and internal staging buffers per
> physical processor package. Therefore, the IA32_MCU_STAGING_MBOX_ADDR
> MSR is package-scoped and will provide a different physical address on
> each physical package."
>
> So why going through loops and hoops?
I'm to blame for that one.
It was the smallest amount of code I could think of at the time that
could work when all the CPUs in a package aren't consecutively numbered.
It also happens to work even if the topology parsing or firmware goes
wonky.
next prev parent reply other threads:[~2024-11-08 22:51 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-01 16:10 [PATCH RFC 0/7] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 1/7] x86/microcode/intel: Remove unnecessary cache writeback and invalidation Chang S. Bae
2024-10-25 16:24 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 2/7] x86/microcode: Introduce staging option to reduce late-loading latency Chang S. Bae
2024-11-04 10:45 ` Borislav Petkov
2024-10-01 16:10 ` [PATCH RFC 3/7] x86/msr-index: Define MSR index and bit for the microcode staging feature Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2024-11-04 11:16 ` Borislav Petkov
2024-11-04 16:08 ` Dave Hansen
2024-11-04 18:34 ` Chang S. Bae
2024-11-04 20:10 ` Chang S. Bae
2024-11-06 18:23 ` [PATCH] cpufreq: Simplify MSR read on the boot CPU Chang S. Bae
2024-11-12 20:44 ` Rafael J. Wysocki
2024-11-06 18:28 ` [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2024-11-07 1:12 ` Thomas Gleixner
2024-11-08 22:42 ` Chang S. Bae
2024-11-08 22:51 ` Dave Hansen [this message]
2024-10-01 16:10 ` [PATCH RFC 5/7] x86/microcode/intel_staging: Implement staging logic Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 6/7] x86/microcode/intel_staging: Support mailbox data transfer Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 7/7] x86/microcode/intel: Enable staging when available Chang S. Bae
2024-12-11 1:42 ` [PATCH 0/6] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2024-12-11 1:42 ` [PATCH 1/6] x86/microcode: Introduce staging option to reduce late-loading latency Chang S. Bae
2025-02-17 13:33 ` Borislav Petkov
2025-02-18 7:51 ` Chang S. Bae
2025-02-18 11:36 ` Borislav Petkov
2025-02-18 15:16 ` Dave Hansen
2024-12-11 1:42 ` [PATCH 2/6] x86/msr-index: Define MSR index and bit for the microcode staging feature Chang S. Bae
2025-02-26 17:19 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 3/6] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2025-02-26 17:52 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 4/6] x86/microcode/intel_staging: Implement staging logic Chang S. Bae
2025-02-18 20:16 ` Dave Hansen
2025-02-26 17:56 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 5/6] x86/microcode/intel_staging: Support mailbox data transfer Chang S. Bae
2025-02-18 20:54 ` Dave Hansen
2025-03-20 23:42 ` Chang S. Bae
2024-12-11 1:42 ` [PATCH 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-02-07 18:37 ` [PATCH 0/6] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2025-02-28 22:27 ` Colin Mitchell
2025-02-28 22:52 ` Borislav Petkov
2025-02-28 23:23 ` Dave Hansen
2025-03-26 21:29 ` Colin Mitchell
2025-04-02 17:14 ` Dave Hansen
2025-02-28 23:05 ` Dave Hansen
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