Re: [PATCH 00/10] irqchip/gic-v5: Fix misc IRS and ITS host driver issues

[Sascha Bischoff <sascha.bischoff@arm.com>]

On 03/11/2026 14:59, Lorenzo Pieralisi wrote:
> On Mon, Nov 02, 2026 at 01:32:53PM +0000, Sascha Bischoff wrote:
>> This series fixes issues in the GICv5 host IRS and ITS drivers.
>>
>> The ITS invalidation serialisation fix addresses Sashiko's report of a
>> race between event and device invalidation commands [1]. The other
>> patches correct IRS allocation and routing behaviour, serialise IRS
>> synchronisation, and fix ITS L1/L2 table selection, cache maintenance,
>> ACPI coherency handling, and resource cleanup.
>>
>> The IRS changes:
>> * Reject allocation of an SPI without an IRS, preventing a null-pointer
>>    dereference, and warn about low-quality firmware.
>> * Only program IRS_PE_CR0.DPS when 1-of-N routing is supported as this field
>>    is RES0, otherwise.
>> * Serialise IRS synchronisation requests, as the IRS ignores a request while
>>    an earlier one is still active.
>>
>> The ITS changes:
>> * Serialise event and device cache invalidations because both use the ITS's
>>    shared DIDR register, so concurrent writes are a bad idea!
>> * Select linear device and interrupt translation tables when one L2
>>    table covers the full ID space. Currently, this selects the wrong
>>    path, then the L1 table code rejects the attempt to create the
>>    table.
>> * Check the ACPI noncoherent flag with ACPI, rather than checking the
>>    DT's property.
>> * Correct cache-maintenance sizing after limiting the DeviceID width.
>> * Invalidate the device cache before freeing an ITT.
>> * Use firmware-node names in initialisation warnings.
>> * Release the reserved MMIO region if DT-based ITS initialisation fails.
>>
>> I've CC'd stable for the IRS/ITS locking fixes, the ITS table alloc
>> issue, and the ACPI coherency fix, as these are the most important
>> changes to backport.
>>
>> The series is based on v7.4-rc1. Thanks for taking a look!
> 
> Thank you for fixing these bugs Sascha.
> 

Absolutely no worries. One of those times where one pulls on a thread, 
and a few more things unravel than one expects :)

V2 incoming.

Thanks,
Sascha

> Lorenzo
> 
>>
>> Sascha
>>
>> [1] https://sashiko.dev/#/patchset/20261016155741.979985-1-sascha.bischoff@arm.com?part=11
>>
>> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
>> ---
>> Sascha Bischoff (10):
>>        irqchip/gic-v5: Reject SPIs not backed by an IRS
>>        irqchip/gic-v5: Only set IRS DPS when 1ofN routing is supported
>>        irqchip/gic-v5: Serialise IRS synchronisation requests
>>        irqchip/gic-v5: Serialise ITS invalidation commands
>>        irqchip/gic-v5: Use linear DT and ITT when L2 covers all IDs
>>        irqchip/gic-v5: Honour ACPI ITS noncoherent flag
>>        irqchip/gic-v5: Use firmware node name in ITS warning
>>        irqchip/gic-v5: Invalidate ITS device cache before freeing ITT
>>        irqchip/gic-v5: Clean the allocated linear device table size
>>        irqchip/gic-v5: Release ITS MMIO region on DT probe failure
>>
>>   drivers/irqchip/irq-gic-v5-irs.c   | 22 +++++++++++++++-------
>>   drivers/irqchip/irq-gic-v5-its.c   | 29 ++++++++++++++++++++++++-----
>>   drivers/irqchip/irq-gic-v5.c       |  9 +++++++++
>>   include/linux/irqchip/arm-gic-v5.h |  1 +
>>   4 files changed, 49 insertions(+), 12 deletions(-)
>> ---
>> base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
>> change-id: 20261102-host_gicv5_fixes-1eeea29d2ea4
>>
>> Best regards,
>> --
>> Sascha Bischoff <sascha.bischoff@arm.com>
>>