Re: [PATCH RESEND v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10

[Robert Richter <rrichter@amd.com>]

On 18.09.26 20:40:35, Borislav Petkov wrote:
> On Thu, Sep 03, 2026 at 02:58:39PM +0530, Naveen N Rao (AMD) wrote:
> > For AMD family 0x10, EILVT offsets are not assigned by BIOS and is
> > instead assigned by picking the next available EILVT offset.  Use the
> > maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than
> > an arbitrary maximum EILVT count when looking for the next available
> > EILVT offset.
> 
> Huh?
> 
> #define         APIC_EILVT_NR_MAX       APIC_EILVT_NR_AMD_10H

Right, found that too.

> 
> What is this "fixing"?

Nothing to do as long APIC_EILVT_NR_MAX does not change.

It shouldn't be sent as a standalone patch. Instead, embed it in a
broader change to keep it in that context.

-Robert

> 
> Also,
> 
> + Robert
> 
> who happens to know something about that code. Don't forget to use git
> annotate, do some git archeology and CC the relevant people on patches.
> 
> Leaving in the rest for him.
> 
> > Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
> > Tested-by: Manali Shukla <manali.shukla@amd.com>
> > ---
> >  arch/x86/events/amd/ibs.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)