From: Naveen N Rao <naveen@kernel.org>
To: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>,
linux-kernel@vger.kernel.org, x86@kernel.org,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Bharata B Rao <bharata@amd.com>,
Manali Shukla <manali.shukla@amd.com>,
Nikunj A Dadhania <nikunj@amd.com>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH RESEND v4 2/3] x86/apic: Introduce a variable to track the number of EILVT registers
Date: Thu, 24 Sep 2026 17:28:48 +0530 [thread overview]
Message-ID: <arUKzQZx77r49plq@blrnaveerao1> (raw)
In-Reply-To: <20260922053610.GBarITypxf7zPAB83g@fat_crate.local>
On Mon, Sep 21, 2026 at 10:36:10PM -0700, Borislav Petkov wrote:
> On Thu, Sep 03, 2026 at 02:58:40PM +0530, Naveen N Rao (AMD) wrote:
> > diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> > index 90025451ace2..c990f403ec7f 100644
> > --- a/arch/x86/kernel/apic/apic.c
> > +++ b/arch/x86/kernel/apic/apic.c
> > @@ -410,6 +410,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
> > }
> > EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
> >
> > +static __init void init_eilvt(void)
> > +{
> > + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
> > + apic->eilvt_regs_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
> > +
> > + if (!apic->eilvt_regs_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> > + apic->eilvt_regs_count = APIC_EILVT_NR_AMD_10H;
>
> Why not simply:
>
> if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
> apic->eilvt_regs_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
> else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> apic->eilvt_regs_count = APIC_EILVT_NR_AMD_10H;
Cause I didn't want to risk changing the current default EILVT register
count for some ~2 decade old processor that may be advertising
X86_FEATURE_EXTAPIC but encoding a count of zero in APIC_EFEAT.
I did look up BKDGs for some of the older processors, but couldn't work
out if this ever was a problem. This was discussed here:
https://lore.kernel.org/all/agckJQQuLsARA4ul@blrnaveerao1/
> And now I see the big picture - you have a single logical patch - add
> eilvt_regs_count - and the rest of the code is reorg and cleanup.
Isn't that the case for most patch series? ;)
>
> So why are there three patches?
Right, the split reflects how I viewed the changes, and to hopefully
simplify the review. Looks like I got the split wrong as it looks to
have been counter-productive here.
Thanks,
- Naveen
next prev parent reply other threads:[~2026-09-24 11:59 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 9:28 [PATCH RESEND v4 0/3] x86/apic: Add support for additional AMD " Naveen N Rao (AMD)
2026-09-03 9:28 ` [PATCH RESEND v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Naveen N Rao (AMD)
2026-09-19 3:40 ` Borislav Petkov
2026-09-21 9:18 ` Robert Richter
2026-09-22 5:26 ` Borislav Petkov
2026-09-03 9:28 ` [PATCH RESEND v4 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Naveen N Rao (AMD)
2026-09-22 5:36 ` Borislav Petkov
2026-09-24 11:58 ` Naveen N Rao [this message]
2026-09-25 4:26 ` Borislav Petkov
2026-09-25 16:09 ` Naveen N Rao
2026-09-03 9:28 ` [PATCH RESEND v4 3/3] x86/apic: Drop APIC_EILVT_NR_MAX Naveen N Rao (AMD)
2026-09-07 5:16 ` [PATCH RESEND v4 0/3] x86/apic: Add support for additional AMD EILVT registers Bharata B Rao
2026-09-15 0:29 ` Borislav Petkov
2026-09-18 7:03 ` Ravi Bangoria
2026-09-19 1:46 ` Borislav Petkov
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