[PATCH 0/5] iommu/arm-smmu-v3: power domain and clock of the RK3588 PCIe SMMU

[PATCH 0/5] iommu/arm-smmu-v3: power domain and clock of the RK3588 PCIe SMMU

[Arun Iyengar via B4 Relay]

The MMU-600 in front of the PCIe controllers of the Rockchip RK3588
(mmu600_pcie) is enabled for every RK3588 board, but its node describes
neither the power domain it lives in (RK3588_PD_PCIE) nor its clock
(ACLK_MMU_PCIE). Both are held by any enabled PCIe controller, which is
why nobody noticed: on a board that enables no PCIe controller in that
domain (an Orange Pi 5 with its M.2 slot in SATA mode, or any RK3588
board without PCIe), genpd powers the domain off and the clock framework
gates the clock as unused after boot, while arm-smmu-v3 stays bound.
At reboot, arm_smmu_device_shutdown() then writes CR0 and polls CR0ACK on
the dead block, the interconnect stalls, "reboot: Restarting system" is
never reached and the board only comes back ~90 s later when the
watchdog fires.

Patches 1 and 2 allow power-domains and clocks in the arm,smmu-v3
binding (arm,smmu.yaml already allows both for the earlier SMMUs).
Patch 3 makes the driver get and enable the clocks of its firmware node
before the first register access, for as long as it is bound; nodes
without clocks (and ACPI/IORT systems) are unaffected. Patches 4 and 5
describe the power domain and the clock in rk3588-base.dtsi. Both DT
patches are needed: with the power domain alone the clock is still
gated and the shutdown still hangs.

Related: Pranjal Shrivastava's "iommu/arm-smmu-v3: Add runtime PM
support" v11 (2026-09-29, 20260929034510.2023173-1-praan@google.com,
not merged) adds pm_domain-based runtime PM and resumes the SMMU around
shutdown, but has no clock handling. This series is compatible with it:
once it lands, the clocks from patch 3 should move into its runtime
suspend/resume callbacks.

Tested on an Orange Pi 5 (RK3588S) with the M.2 slot in SATA mode and
the root filesystem on the SATA SSD, where every reboot used to hang:
three consecutive reboots printed "reboot: Restarting system" and the
boot loader started 0.6 s later (previously ~89 s, from the watchdog);
clk_summary shows aclk_mmu_pcie enabled with iommu@fc900000 as consumer
and pm_genpd_summary shows PD_PCIE on; the SMMU probes as before and
SATA keeps running at 6.0 Gbps without errors. With patch 4 alone
(power domain, clock still gated) the reboot still hung at
"arm-smmu-v3 fc900000.iommu: shutdown" on the serial console. Boards
with PCIe enabled are already in the state these patches describe.

This series was developed with Claude (Anthropic) as a coding assistant:
it wrote the code and the commit messages, and I reviewed and tested
every change as described above.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
Arun Iyengar (5):
      dt-bindings: iommu: arm,smmu-v3: allow a power domain
      dt-bindings: iommu: arm,smmu-v3: allow clocks
      iommu/arm-smmu-v3: enable optional clocks
      arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU
      arm64: dts: rockchip: add the clock of the RK3588 PCIe SMMU

 Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 10 ++++++++++
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi            |  2 ++
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c              |  7 +++++++
 3 files changed, 19 insertions(+)
---
base-commit: 2cf4be57b301ed2d7af82e70cff5dfd96894d8de
change-id: 20261110-smmu-v3-pcie-pd-a2f127b81d8f

Best regards,
--  
Arun Iyengar <aiyengar1990@gmail.com>

[PATCH 1/5] dt-bindings: iommu: arm,smmu-v3: allow a power domain

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

An SMMUv3 instance can sit in a switchable power domain of the SoC, for
example the MMU-600 in front of the PCIe controllers on the Rockchip
RK3588, which is part of the PCIe power domain. If the domain is not
described, nothing keeps it powered while the SMMU is bound, and any
register access after it has been turned off as unused stalls the
interconnect.

Allow a single power-domains entry, as arm,smmu.yaml already does for
the earlier SMMU architectures.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 3c044e4f03d4..c8f22dfdb1db 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -63,6 +63,9 @@ properties:
 
   msi-parent: true
 
+  power-domains:
+    maxItems: 1
+
   nvidia,cmdqv:
     description: |
       A phandle to its pairing CMDQV extension for an implementation on NVIDIA

-- 
2.55.0

[PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

Some SoCs feed the SMMUv3 from a clock that the OS controls. On the
Rockchip RK3588 the MMU-600 for PCIe runs from ACLK_MMU_PCIE, whose only
other consumers are the PCIe controllers. When no PCIe controller is
enabled, the clock framework gates it as unused, and the SMMU can no
longer be accessed.

Allow up to four clocks, so that such a clock can be described and held
by the SMMU driver.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index c8f22dfdb1db..f8a74730667c 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -63,6 +63,13 @@ properties:
 
   msi-parent: true
 
+  clocks:
+    minItems: 1
+    maxItems: 4
+    description:
+      Clocks needed to access the SMMU registers and to keep its translation
+      units running, if they are not managed by firmware.
+
   power-domains:
     maxItems: 1
 

-- 
2.55.0

[PATCH 3/5] iommu/arm-smmu-v3: enable optional clocks

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

On some platforms the SMMU's clock is controlled by the OS, and without a
consumer the clock framework gates it as unused late in boot. Any later
register access, for example the CR0 write in the shutdown path, then
stalls the interconnect. This happens on the RK3588 when no PCIe
controller keeps the PCIe MMU-600 clock running.

Get and enable all clocks described in the firmware node before the
registers are first accessed, and keep them enabled while the driver is
bound. Nodes without clocks are not affected.

Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 6d4520c47308..cce66db93219 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -12,6 +12,7 @@
 #include <linux/acpi.h>
 #include <linux/acpi_iort.h>
 #include <linux/bitops.h>
+#include <linux/clk.h>
 #include <linux/crash_dump.h>
 #include <linux/delay.h>
 #include <linux/err.h>
@@ -5786,6 +5787,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
 	resource_size_t ioaddr;
 	struct arm_smmu_device *smmu;
 	struct device *dev = &pdev->dev;
+	struct clk_bulk_data *clks;
 
 	smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
 	if (!smmu)
@@ -5800,6 +5802,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	/* Optional clocks: keep them running for as long as we are bound */
+	ret = devm_clk_bulk_get_all_enabled(dev, &clks);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "failed to enable clocks\n");
+
 	smmu = arm_smmu_impl_probe(smmu);
 	if (IS_ERR(smmu))
 		return PTR_ERR(smmu);

-- 
2.55.0

[PATCH 4/5] arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

The MMU-600 for the PCIe controllers (mmu600_pcie) is enabled for every
RK3588 board, but its node does not describe that it lives in
RK3588_PD_PCIE. It only works today because TF-A leaves the domain on at
boot and, on most boards, an enabled PCIe controller holds it on later.

On a board that disables all PCIe controllers using that domain (the
Orange Pi 5 with its M.2 slot in SATA mode is one), genpd powers
PD_PCIE off as unused after boot while arm-smmu-v3 is still bound. Then
at reboot arm_smmu_device_shutdown() writes CR0 and polls CR0ACK on the
unpowered block, which stalls the bus: the kernel never reaches
"reboot: Restarting system" and the board only comes back once the
watchdog fires.

Describe the power domain, so genpd keeps it on for as long as the SMMU
is bound.

Fixes: da92d3dfc871 ("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC")
Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index aa69fd3793fd..bcd342c025c9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -560,6 +560,7 @@ mmu600_pcie: iommu@fc900000 {
 			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
 		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
 		#iommu-cells = <1>;
+		power-domains = <&power RK3588_PD_PCIE>;
 	};
 
 	mmu600_php: iommu@fcb00000 {

-- 
2.55.0

[PATCH 5/5] arm64: dts: rockchip: add the clock of the RK3588 PCIe SMMU

[Arun Iyengar via B4 Relay]

From: Arun Iyengar <aiyengar1990@gmail.com>

The PCIe MMU-600 runs from ACLK_MMU_PCIE, which is also the parent of
the PCIe controllers' master clocks. When no PCIe controller is enabled,
nothing holds it and it gets gated as unused after boot, while
arm-smmu-v3 is still bound to the SMMU.

Describe the clock, so that the SMMU driver keeps it running.

Fixes: da92d3dfc871 ("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC")
Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index bcd342c025c9..8eed22ca69ab 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -559,6 +559,7 @@ mmu600_pcie: iommu@fc900000 {
 			     <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
 			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
 		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+		clocks = <&cru ACLK_MMU_PCIE>;
 		#iommu-cells = <1>;
 		power-domains = <&power RK3588_PD_PCIE>;
 	};

-- 
2.55.0

Re: [PATCH 0/5] iommu/arm-smmu-v3: power domain and clock of the RK3588 PCIe SMMU

[Shawn Lin]

Cc: Simon and Finley

在 2026/11/10 星期二 15:11, Arun Iyengar via B4 Relay 写道:
> The MMU-600 in front of the PCIe controllers of the Rockchip RK3588
> (mmu600_pcie) is enabled for every RK3588 board, but its node describes
> neither the power domain it lives in (RK3588_PD_PCIE) nor its clock
> (ACLK_MMU_PCIE). Both are held by any enabled PCIe controller, which is
> why nobody noticed: on a board that enables no PCIe controller in that
> domain (an Orange Pi 5 with its M.2 slot in SATA mode, or any RK3588
> board without PCIe), genpd powers the domain off and the clock framework
> gates the clock as unused after boot, while arm-smmu-v3 stays bound.
> At reboot, arm_smmu_device_shutdown() then writes CR0 and polls CR0ACK on
> the dead block, the interconnect stalls, "reboot: Restarting system" is
> never reached and the board only comes back ~90 s later when the
> watchdog fires.
> 
> Patches 1 and 2 allow power-domains and clocks in the arm,smmu-v3
> binding (arm,smmu.yaml already allows both for the earlier SMMUs).
> Patch 3 makes the driver get and enable the clocks of its firmware node
> before the first register access, for as long as it is bound; nodes
> without clocks (and ACPI/IORT systems) are unaffected. Patches 4 and 5
> describe the power domain and the clock in rk3588-base.dtsi. Both DT
> patches are needed: with the power domain alone the clock is still
> gated and the shutdown still hangs.
> 
> Related: Pranjal Shrivastava's "iommu/arm-smmu-v3: Add runtime PM
> support" v11 (2026-09-29, 20260929034510.2023173-1-praan@google.com,
> not merged) adds pm_domain-based runtime PM and resumes the SMMU around
> shutdown, but has no clock handling. This series is compatible with it:
> once it lands, the clocks from patch 3 should move into its runtime
> suspend/resume callbacks.
> 
> Tested on an Orange Pi 5 (RK3588S) with the M.2 slot in SATA mode and
> the root filesystem on the SATA SSD, where every reboot used to hang:
> three consecutive reboots printed "reboot: Restarting system" and the
> boot loader started 0.6 s later (previously ~89 s, from the watchdog);
> clk_summary shows aclk_mmu_pcie enabled with iommu@fc900000 as consumer
> and pm_genpd_summary shows PD_PCIE on; the SMMU probes as before and
> SATA keeps running at 6.0 Gbps without errors. With patch 4 alone
> (power domain, clock still gated) the reboot still hung at
> "arm-smmu-v3 fc900000.iommu: shutdown" on the serial console. Boards
> with PCIe enabled are already in the state these patches describe.
> 
> This series was developed with Claude (Anthropic) as a coding assistant:
> it wrote the code and the commit messages, and I reviewed and tested
> every change as described above.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---
> Arun Iyengar (5):
>        dt-bindings: iommu: arm,smmu-v3: allow a power domain
>        dt-bindings: iommu: arm,smmu-v3: allow clocks
>        iommu/arm-smmu-v3: enable optional clocks
>        arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU
>        arm64: dts: rockchip: add the clock of the RK3588 PCIe SMMU
> 
>   Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 10 ++++++++++
>   arch/arm64/boot/dts/rockchip/rk3588-base.dtsi            |  2 ++
>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c              |  7 +++++++
>   3 files changed, 19 insertions(+)
> ---
> base-commit: 2cf4be57b301ed2d7af82e70cff5dfd96894d8de
> change-id: 20261110-smmu-v3-pcie-pd-a2f127b81d8f
> 
> Best regards,
> --
> Arun Iyengar <aiyengar1990@gmail.com>
> 
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
> 

Re: [PATCH 0/5] iommu/arm-smmu-v3: power domain and clock of the RK3588 PCIe SMMU

[Heiko Stübner]

Am Dienstag, 10. November 2026, 09:40:44 Mitteleuropäische Normalzeit schrieb Shawn Lin:
> Cc: Simon and Finley
> 
> 在 2026/11/10 星期二 15:11, Arun Iyengar via B4 Relay 写道:
> > The MMU-600 in front of the PCIe controllers of the Rockchip RK3588
> > (mmu600_pcie) is enabled for every RK3588 board, but its node describes
> > neither the power domain it lives in (RK3588_PD_PCIE) nor its clock
> > (ACLK_MMU_PCIE). Both are held by any enabled PCIe controller, which is
> > why nobody noticed: on a board that enables no PCIe controller in that
> > domain (an Orange Pi 5 with its M.2 slot in SATA mode, or any RK3588
> > board without PCIe), genpd powers the domain off and the clock framework
> > gates the clock as unused after boot, while arm-smmu-v3 stays bound.
> > At reboot, arm_smmu_device_shutdown() then writes CR0 and polls CR0ACK on
> > the dead block, the interconnect stalls, "reboot: Restarting system" is
> > never reached and the board only comes back ~90 s later when the
> > watchdog fires.

We have a work-around for that in some boards, manually disabling the
smmu until now. As the SMMU is part of the SoC and always present
the general DT practice is to have it always enabled, as it does not
depend on the actual board design.

Hence we end up in the situation described above.

So this series fixes the actual underlying problem, making these
workarounds unnecessary in the future :-)


So definitly thanks a lot
Heiko

Re: [PATCH 1/5] dt-bindings: iommu: arm,smmu-v3: allow a power domain

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 1477 bytes --]

Hi,

On Tue, Nov 10, 2026 at 07:11:48AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> An SMMUv3 instance can sit in a switchable power domain of the SoC, for
> example the MMU-600 in front of the PCIe controllers on the Rockchip
> RK3588, which is part of the PCIe power domain. If the domain is not
> described, nothing keeps it powered while the SMMU is bound, and any
> register access after it has been turned off as unused stalls the
> interconnect.
> 
> Allow a single power-domains entry, as arm,smmu.yaml already does for
> the earlier SMMU architectures.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

>  Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index 3c044e4f03d4..c8f22dfdb1db 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -63,6 +63,9 @@ properties:
>  
>    msi-parent: true
>  
> +  power-domains:
> +    maxItems: 1
> +
>    nvidia,cmdqv:
>      description: |
>        A phandle to its pairing CMDQV extension for an implementation on NVIDIA
> 
> -- 
> 2.55.0
> 
> 
> 

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Re: [PATCH 3/5] iommu/arm-smmu-v3: enable optional clocks

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 2228 bytes --]

Hi,

On Tue, Nov 10, 2026 at 07:11:50AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> On some platforms the SMMU's clock is controlled by the OS, and without a
> consumer the clock framework gates it as unused late in boot. Any later
> register access, for example the CR0 write in the shutdown path, then
> stalls the interconnect. This happens on the RK3588 when no PCIe
> controller keeps the PCIe MMU-600 clock running.
> 
> Get and enable all clocks described in the firmware node before the
> registers are first accessed, and keep them enabled while the driver is
> bound. Nodes without clocks are not affected.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index 6d4520c47308..cce66db93219 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -12,6 +12,7 @@
>  #include <linux/acpi.h>
>  #include <linux/acpi_iort.h>
>  #include <linux/bitops.h>
> +#include <linux/clk.h>
>  #include <linux/crash_dump.h>
>  #include <linux/delay.h>
>  #include <linux/err.h>
> @@ -5786,6 +5787,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>  	resource_size_t ioaddr;
>  	struct arm_smmu_device *smmu;
>  	struct device *dev = &pdev->dev;
> +	struct clk_bulk_data *clks;
>  
>  	smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
>  	if (!smmu)
> @@ -5800,6 +5802,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> +	/* Optional clocks: keep them running for as long as we are bound */

useless comment, otherwise

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

> +	ret = devm_clk_bulk_get_all_enabled(dev, &clks);
> +	if (ret < 0)
> +		return dev_err_probe(dev, ret, "failed to enable clocks\n");
> +
>  	smmu = arm_smmu_impl_probe(smmu);
>  	if (IS_ERR(smmu))
>  		return PTR_ERR(smmu);
> 
> -- 
> 2.55.0
> 
> 
> 

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Re: [PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 1504 bytes --]

Hi,

On Tue, Nov 10, 2026 at 07:11:49AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> Some SoCs feed the SMMUv3 from a clock that the OS controls. On the
> Rockchip RK3588 the MMU-600 for PCIe runs from ACLK_MMU_PCIE, whose only
> other consumers are the PCIe controllers. When no PCIe controller is
> enabled, the clock framework gates it as unused, and the SMMU can no
> longer be accessed.
> 
> Allow up to four clocks, so that such a clock can be described and held
> by the SMMU driver.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---

This does not explain why a maximum of four clocks is allowed.

Greetings,

-- Sebastian

>  Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index c8f22dfdb1db..f8a74730667c 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -63,6 +63,13 @@ properties:
>  
>    msi-parent: true
>  
> +  clocks:
> +    minItems: 1
> +    maxItems: 4
> +    description:
> +      Clocks needed to access the SMMU registers and to keep its translation
> +      units running, if they are not managed by firmware.
> +
>    power-domains:
>      maxItems: 1
>  
> 
> -- 
> 2.55.0
> 
> 
> 

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Re: [PATCH 4/5] arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU

[Sebastian Reichel]

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Hi,

On Tue, Nov 10, 2026 at 07:11:51AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> The MMU-600 for the PCIe controllers (mmu600_pcie) is enabled for every
> RK3588 board, but its node does not describe that it lives in
> RK3588_PD_PCIE. It only works today because TF-A leaves the domain on at
> boot and, on most boards, an enabled PCIe controller holds it on later.
> 
> On a board that disables all PCIe controllers using that domain (the
> Orange Pi 5 with its M.2 slot in SATA mode is one), genpd powers
> PD_PCIE off as unused after boot while arm-smmu-v3 is still bound. Then
> at reboot arm_smmu_device_shutdown() writes CR0 and polls CR0ACK on the
> unpowered block, which stalls the bus: the kernel never reaches
> "reboot: Restarting system" and the board only comes back once the
> watchdog fires.
> 
> Describe the power domain, so genpd keeps it on for as long as the SMMU
> is bound.
> 
> Fixes: da92d3dfc871 ("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC")
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index aa69fd3793fd..bcd342c025c9 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -560,6 +560,7 @@ mmu600_pcie: iommu@fc900000 {
>  			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
>  		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
>  		#iommu-cells = <1>;
> +		power-domains = <&power RK3588_PD_PCIE>;

The TRM says the power domain of MMU600_PCIE is PD_PHP, not PD_PCIE.
See Table 7-1 RK3588 Voltage Domain and Power Domain Summary around
page 1096 (depending on specific TRM version).

Note, that PD_PCIE is a child of PD_PHP, so it makes sense that
PD_PCIE also works.

Greetings,

-- Sebastian

>  	};
>  
>  	mmu600_php: iommu@fcb00000 {
> 
> -- 
> 2.55.0
> 
> 
> 

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Re: [PATCH 5/5] arm64: dts: rockchip: add the clock of the RK3588 PCIe SMMU

[Sebastian Reichel]

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Hi,

On Tue, Nov 10, 2026 at 07:11:52AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> The PCIe MMU-600 runs from ACLK_MMU_PCIE, which is also the parent of
> the PCIe controllers' master clocks. When no PCIe controller is enabled,
> nothing holds it and it gets gated as unused after boot, while
> arm-smmu-v3 is still bound to the SMMU.
> 
> Describe the clock, so that the SMMU driver keeps it running.
> 
> Fixes: da92d3dfc871 ("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC")
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index bcd342c025c9..8eed22ca69ab 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -559,6 +559,7 @@ mmu600_pcie: iommu@fc900000 {
>  			     <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
>  			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
>  		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> +		clocks = <&cru ACLK_MMU_PCIE>;
>  		#iommu-cells = <1>;
>  		power-domains = <&power RK3588_PD_PCIE>;
>  	};
> 
> -- 
> 2.55.0
> 
> 
> 

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Re: [PATCH 0/5] iommu/arm-smmu-v3: power domain and clock of the RK3588 PCIe SMMU

[Sebastian Reichel]

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Hi,

On Tue, Nov 10, 2026 at 07:11:47AM +0000, Arun Iyengar via B4 Relay wrote:
> The MMU-600 in front of the PCIe controllers of the Rockchip RK3588
> (mmu600_pcie) is enabled for every RK3588 board, but its node describes
> neither the power domain it lives in (RK3588_PD_PCIE) nor its clock
> (ACLK_MMU_PCIE). Both are held by any enabled PCIe controller, which is
> why nobody noticed: on a board that enables no PCIe controller in that
> domain (an Orange Pi 5 with its M.2 slot in SATA mode, or any RK3588
> board without PCIe), genpd powers the domain off and the clock framework
> gates the clock as unused after boot, while arm-smmu-v3 stays bound.
> At reboot, arm_smmu_device_shutdown() then writes CR0 and polls CR0ACK on
> the dead block, the interconnect stalls, "reboot: Restarting system" is
> never reached and the board only comes back ~90 s later when the
> watchdog fires.
> 
> Patches 1 and 2 allow power-domains and clocks in the arm,smmu-v3
> binding (arm,smmu.yaml already allows both for the earlier SMMUs).
> Patch 3 makes the driver get and enable the clocks of its firmware node
> before the first register access, for as long as it is bound; nodes
> without clocks (and ACPI/IORT systems) are unaffected. Patches 4 and 5
> describe the power domain and the clock in rk3588-base.dtsi. Both DT
> patches are needed: with the power domain alone the clock is still
> gated and the shutdown still hangs.
> 
> Related: Pranjal Shrivastava's "iommu/arm-smmu-v3: Add runtime PM
> support" v11 (2026-09-29, 20260929034510.2023173-1-praan@google.com,
> not merged) adds pm_domain-based runtime PM and resumes the SMMU around
> shutdown, but has no clock handling. This series is compatible with it:
> once it lands, the clocks from patch 3 should move into its runtime
> suspend/resume callbacks.
> 
> Tested on an Orange Pi 5 (RK3588S) with the M.2 slot in SATA mode and
> the root filesystem on the SATA SSD, where every reboot used to hang:
> three consecutive reboots printed "reboot: Restarting system" and the
> boot loader started 0.6 s later (previously ~89 s, from the watchdog);
> clk_summary shows aclk_mmu_pcie enabled with iommu@fc900000 as consumer
> and pm_genpd_summary shows PD_PCIE on; the SMMU probes as before and
> SATA keeps running at 6.0 Gbps without errors. With patch 4 alone
> (power domain, clock still gated) the reboot still hung at
> "arm-smmu-v3 fc900000.iommu: shutdown" on the serial console. Boards
> with PCIe enabled are already in the state these patches describe.
> 
> This series was developed with Claude (Anthropic) as a coding assistant:
> it wrote the code and the commit messages, and I reviewed and tested
> every change as described above.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---

While at it, maybe also add the reset line (SRST_A_MMU_PCIE on
RK3588) to make the hardware description complete? See also the
MMU-600 TRM, that there is one clock and one reset line:

Link: https://support.arm.com/documentation/100310/0202/Signal-descriptions/Clock-and-reset-signals?lang=en

Greetings,

-- Sebastian

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