[PATCH 0/3] net: phy: at803x: support qca8081 1G version chip

[PATCH 0/3] net: phy: at803x: support qca8081 1G version chip

[Luo Jie]

This patch series add supporting qca8081 1G version chip, the 1G version
chip can be identified by the register mmd7.0x901d bit0.

In addition, qca8081 does not support 1000BaseX mode and the fifo reset
is added on the link changed, which assert the fifo on the link down,
deassert the fifo on the link up.

Luo Jie (3):
  net: phy: at803x: support qca8081 1G chip type
  net: phy: at803x: remove 1000BaseX mode of qca8081
  net: phy: at803x: add qca8081 fifo reset on the link down

 drivers/net/phy/at803x.c | 79 +++++++++++++++++++++++++++++-----------
 1 file changed, 58 insertions(+), 21 deletions(-)


base-commit: ae230642190a51b85656d6da2df744d534d59544
-- 
2.17.1

[PATCH 1/3] net: phy: at803x: support qca8081 1G chip type

[Luo Jie]

The qca8081 1G chip version does not support 2.5 capability, which
is distinguished from qca8081 2.5G chip according to the bit0 of
register mmd7.0x901d.

The fast retrain and master slave seed configs are only needed when
the 2.5G capability is supported.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/at803x.c | 58 ++++++++++++++++++++++++++--------------
 1 file changed, 38 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index c1f307d90518..3339ca372b24 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -272,6 +272,10 @@
 #define QCA808X_CDT_STATUS_STAT_OPEN		2
 #define QCA808X_CDT_STATUS_STAT_SHORT		3
 
+/* QCA808X 1G chip type */
+#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
+#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
+
 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
 MODULE_AUTHOR("Matus Ujhelyi");
 MODULE_LICENSE("GPL");
@@ -898,12 +902,22 @@ static int at803x_get_features(struct phy_device *phydev)
 		return err;
 
 	if (phydev->drv->phy_id == QCA8081_PHY_ID) {
-		err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE);
+		err = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
 		if (err < 0)
 			return err;
 
-		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported,
-				err & MDIO_PMA_NG_EXTABLE_2_5GBT);
+		/* QCA808X does not support 2.5G capability if the chip type is 1G according
+		 * to the register MMD7.QCA808X_PHY_MMD7_CHIP_TYPE.
+		 */
+
+		if (!(QCA808X_PHY_CHIP_TYPE_1G & err)) {
+			err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE);
+			if (err < 0)
+				return err;
+
+			linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported,
+					err & MDIO_PMA_NG_EXTABLE_2_5GBT);
+		}
 	}
 
 	if (phydev->drv->phy_id != ATH8031_PHY_ID)
@@ -1770,20 +1784,22 @@ static int qca808x_config_init(struct phy_device *phydev)
 	if (ret)
 		return ret;
 
-	/* Config the fast retrain for the link 2500M */
-	ret = qca808x_phy_fast_retrain_config(phydev);
-	if (ret)
-		return ret;
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
+		/* Config the fast retrain for the link 2500M */
+		ret = qca808x_phy_fast_retrain_config(phydev);
+		if (ret)
+			return ret;
 
-	/* Configure lower ramdom seed to make phy linked as slave mode */
-	ret = qca808x_phy_ms_random_seed_set(phydev);
-	if (ret)
-		return ret;
+		/* Configure lower ramdom seed to make phy linked as slave mode */
+		ret = qca808x_phy_ms_random_seed_set(phydev);
+		if (ret)
+			return ret;
 
-	/* Enable seed */
-	ret = qca808x_phy_ms_seed_enable(phydev, true);
-	if (ret)
-		return ret;
+		/* Enable seed */
+		ret = qca808x_phy_ms_seed_enable(phydev, true);
+		if (ret)
+			return ret;
+	}
 
 	/* Configure adc threshold as 100mv for the link 10M */
 	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
@@ -1822,11 +1838,13 @@ static int qca808x_read_status(struct phy_device *phydev)
 		 * value is configured as the same value, the link can't be up and no link change
 		 * occurs.
 		 */
-		if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) {
-			qca808x_phy_ms_seed_enable(phydev, false);
-		} else {
-			qca808x_phy_ms_random_seed_set(phydev);
-			qca808x_phy_ms_seed_enable(phydev, true);
+		if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
+			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) {
+				qca808x_phy_ms_seed_enable(phydev, false);
+			} else {
+				qca808x_phy_ms_random_seed_set(phydev);
+				qca808x_phy_ms_seed_enable(phydev, true);
+			}
 		}
 	}
 
-- 
2.17.1

[PATCH 2/3] net: phy: at803x: remove 1000BaseX mode of qca8081

[Luo Jie]

QCA808x does not support the link mode 1000BaseX.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/at803x.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 3339ca372b24..29aab7eaaa90 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -920,7 +920,7 @@ static int at803x_get_features(struct phy_device *phydev)
 		}
 	}
 
-	if (phydev->drv->phy_id != ATH8031_PHY_ID)
+	if (phydev->drv->phy_id != ATH8031_PHY_ID && phydev->drv->phy_id != QCA8081_PHY_ID)
 		return 0;
 
 	/* AR8031/AR8033 have different status registers
@@ -933,6 +933,8 @@ static int at803x_get_features(struct phy_device *phydev)
 	 *
 	 * Remove this mode from the supported link modes
 	 * when not operating in 1000BaseX mode.
+	 *
+	 * QCA808x does not support 1000BaseX mode.
 	 */
 	if (!priv->is_1000basex)
 		linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
-- 
2.17.1

[PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Luo Jie]

The qca8081 fifo needs to be reset on link down and released
on the link up in case of any abnormal issue such as the
packet blocked on the PHY.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/at803x.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 29aab7eaaa90..5dc707eaf18c 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -276,6 +276,9 @@
 #define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
 #define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
 
+#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
+#define QCA8081_PHY_FIFO_RSTN			BIT(11)
+
 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
 MODULE_AUTHOR("Matus Ujhelyi");
 MODULE_LICENSE("GPL");
@@ -1808,6 +1811,16 @@ static int qca808x_config_init(struct phy_device *phydev)
 			QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);
 }
 
+static int qca808x_fifo_reset(struct phy_device *phydev)
+{
+	/* Reset serdes fifo on link down, Release serdes fifo on link up,
+	 * the serdes address is phy address added by 1.
+	 */
+	return mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
+			MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
+			QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
+}
+
 static int qca808x_read_status(struct phy_device *phydev)
 {
 	int ret;
@@ -1827,6 +1840,10 @@ static int qca808x_read_status(struct phy_device *phydev)
 	if (ret < 0)
 		return ret;
 
+	ret = qca808x_fifo_reset(phydev);
+	if (ret < 0)
+		return ret;
+
 	if (phydev->link) {
 		if (phydev->speed == SPEED_2500)
 			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-- 
2.17.1

Re: [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type

[Andrew Lunn]

On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
> The qca8081 1G chip version does not support 2.5 capability, which
> is distinguished from qca8081 2.5G chip according to the bit0 of
> register mmd7.0x901d.
> 
> The fast retrain and master slave seed configs are only needed when
> the 2.5G capability is supported.

Does genphy_c45_pma_read_abilities() work on these devices? 

     Andrew

Re: [PATCH 2/3] net: phy: at803x: remove 1000BaseX mode of qca8081

[Andrew Lunn]

On Thu, Jun 29, 2023 at 11:48:45AM +0800, Luo Jie wrote:
> QCA808x does not support the link mode 1000BaseX.
> 
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Andrew Lunn]

> +static int qca808x_fifo_reset(struct phy_device *phydev)
> +{
> +	/* Reset serdes fifo on link down, Release serdes fifo on link up,
> +	 * the serdes address is phy address added by 1.
> +	 */
> +	return mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
> +			MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
> +			QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);

In polling mode, this is going to be called once per second. Do you
really want to be setting that register all the time? Consider using
the link_change_notify callback.

Also, can you tell us more about this SERDES device on the bus. I just
want to make sure this is not a PCS and should have its own driver.

     Andrew

Re: [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type

[Jie Luo]

On 6/29/2023 9:14 PM, Andrew Lunn wrote:
> On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
>> The qca8081 1G chip version does not support 2.5 capability, which
>> is distinguished from qca8081 2.5G chip according to the bit0 of
>> register mmd7.0x901d.
>>
>> The fast retrain and master slave seed configs are only needed when
>> the 2.5G capability is supported.
> 
> Does genphy_c45_pma_read_abilities() work on these devices?
> 
>       Andrew

Hi Andrew,
yes, genphy_c45_pma_read_abilities works on both normal qca8081 2.5G 
chip and qca8081 1G version chip, even the PHY ID is same, the only 
difference between qca8081 1G and 2.5G chip is the 2.5G capability 
removed on 1G version chip.

Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Jie Luo]

On 6/29/2023 9:23 PM, Andrew Lunn wrote:
>> +static int qca808x_fifo_reset(struct phy_device *phydev)
>> +{
>> +	/* Reset serdes fifo on link down, Release serdes fifo on link up,
>> +	 * the serdes address is phy address added by 1.
>> +	 */
>> +	return mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
>> +			MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
>> +			QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
> 
> In polling mode, this is going to be called once per second. Do you
> really want to be setting that register all the time? Consider using
> the link_change_notify callback.
> 
> Also, can you tell us more about this SERDES device on the bus. I just
> want to make sure this is not a PCS and should have its own driver.
> 
>       Andrew
Hi Andrew,
Thanks for the review.
yes, we can use the link_change_notify, since the fifo reset is needed 
on the link changed, i will update the patch to use link_change_notify.

SERDES device is the block converts data between serial data and 
parallel interfaces in each direction, which is the SGMII interface in 
qca8081 PHY, it's address is always the PHY address added by 1 in 
qca8081 PHY.

Re: [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type

[Andrew Lunn]

On Fri, Jun 30, 2023 at 02:39:06PM +0800, Jie Luo wrote:
> 
> 
> On 6/29/2023 9:14 PM, Andrew Lunn wrote:
> > On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
> > > The qca8081 1G chip version does not support 2.5 capability, which
> > > is distinguished from qca8081 2.5G chip according to the bit0 of
> > > register mmd7.0x901d.
> > > 
> > > The fast retrain and master slave seed configs are only needed when
> > > the 2.5G capability is supported.
> > 
> > Does genphy_c45_pma_read_abilities() work on these devices?
> > 
> >       Andrew
> 
> Hi Andrew,
> yes, genphy_c45_pma_read_abilities works on both normal qca8081 2.5G chip
> and qca8081 1G version chip, even the PHY ID is same, the only difference
> between qca8081 1G and 2.5G chip is the 2.5G capability removed on 1G
> version chip.

Great, then please use it to simply the driver.

       Andrew

Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Andrew Lunn]

> SERDES device is the block converts data between serial data and parallel
> interfaces in each direction, which is the SGMII interface in qca8081 PHY,
> it's address is always the PHY address added by 1 in qca8081 PHY.

What other registers does this block have? What behaviour can be
configured? Does it have any support for Clause 73? Is there an open
datasheet for it?

	    Andrew

Re: [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type

[Jie Luo]

On 6/30/2023 9:16 PM, Andrew Lunn wrote:
> On Fri, Jun 30, 2023 at 02:39:06PM +0800, Jie Luo wrote:
>>
>>
>> On 6/29/2023 9:14 PM, Andrew Lunn wrote:
>>> On Thu, Jun 29, 2023 at 11:48:44AM +0800, Luo Jie wrote:
>>>> The qca8081 1G chip version does not support 2.5 capability, which
>>>> is distinguished from qca8081 2.5G chip according to the bit0 of
>>>> register mmd7.0x901d.
>>>>
>>>> The fast retrain and master slave seed configs are only needed when
>>>> the 2.5G capability is supported.
>>>
>>> Does genphy_c45_pma_read_abilities() work on these devices?
>>>
>>>        Andrew
>>
>> Hi Andrew,
>> yes, genphy_c45_pma_read_abilities works on both normal qca8081 2.5G chip
>> and qca8081 1G version chip, even the PHY ID is same, the only difference
>> between qca8081 1G and 2.5G chip is the 2.5G capability removed on 1G
>> version chip.
> 
> Great, then please use it to simply the driver.
> 
>         Andrew
Hi Andrew,
Per double check qca8081 PHY registers, the PHY ID only exists in the 
MII register, which is not in the MMD device register.

There are MMD device 1, 3, 7 in qca8081 PHY, the PMA abilities 
10/100/1000/2500 are compliant with genphy_c45_pma_read_abilities, but 
the MDIO_AN_STAT1_ABLE does not exist in MMD7.1 register.

so the genphy_c45_pma_read_abilities can't be fully supported by qca8081 
phy, sorry for this misunderstanding.

Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Jie Luo]

On 6/30/2023 9:21 PM, Andrew Lunn wrote:
>> SERDES device is the block converts data between serial data and parallel
>> interfaces in each direction, which is the SGMII interface in qca8081 PHY,
>> it's address is always the PHY address added by 1 in qca8081 PHY.
> 
> What other registers does this block have? What behaviour can be
> configured? Does it have any support for Clause 73? Is there an open
> datasheet for it?
> 
> 	    Andrew

Hi Andrew,
This block includes MII and MMD1 registers, which mainly configure the 
PLL clocks, reset and calibration of the interface sgmii, there is no 
related Clause 73 control register in this block.

Normally it is the hardware behavior, driver do not need to configure 
these registers, adding this interface fifo reset is for avoiding the 
packet block issue in some corner case.

it seems there is no open datasheet after searching the internet, but 
you can get the basic information of qca8081 from the following link.
https://www.qualcomm.com/products/internet-of-things/networking/wi-fi-networks/qca8081

Thanks,
Jie

Re: [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type

[Andrew Lunn]

> There are MMD device 1, 3, 7 in qca8081 PHY, the PMA abilities
> 10/100/1000/2500 are compliant with genphy_c45_pma_read_abilities, but the
> MDIO_AN_STAT1_ABLE does not exist in MMD7.1 register.
> 
> so the genphy_c45_pma_read_abilities can't be fully supported by qca8081
> phy, sorry for this misunderstanding.

If all you are missing is MDIO_AN_STAT1_ABLE, then i assume you are
missing Autoneg? So have your tried using
genphy_c45_pma_read_abilities() and then just doing:

                        linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
                                         phydev->supported);

with a comment explaining why.

	Andrew					 

Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Andrew Lunn]

> Hi Andrew,
> This block includes MII and MMD1 registers, which mainly configure the PLL
> clocks, reset and calibration of the interface sgmii, there is no related
> Clause 73 control register in this block.

O.K. What does it have in the MII ID registers? Does Linux think it is
a PHY and instantiating an generic PHY driver for it?

	Andrew

Re: [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type

[Jie Luo]

On 7/1/2023 10:30 PM, Andrew Lunn wrote:
>> There are MMD device 1, 3, 7 in qca8081 PHY, the PMA abilities
>> 10/100/1000/2500 are compliant with genphy_c45_pma_read_abilities, but the
>> MDIO_AN_STAT1_ABLE does not exist in MMD7.1 register.
>>
>> so the genphy_c45_pma_read_abilities can't be fully supported by qca8081
>> phy, sorry for this misunderstanding.
> 
> If all you are missing is MDIO_AN_STAT1_ABLE, then i assume you are
> missing Autoneg? So have your tried using
> genphy_c45_pma_read_abilities() and then just doing:
> 
>                          linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
>                                           phydev->supported);
> 
> with a comment explaining why.
> 
> 	Andrew					
Thanks Andrew for this suggestion, i will verify this code and update 
the patch series.

Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Jie Luo]

On 7/1/2023 10:34 PM, Andrew Lunn wrote:
>> Hi Andrew,
>> This block includes MII and MMD1 registers, which mainly configure the PLL
>> clocks, reset and calibration of the interface sgmii, there is no related
>> Clause 73 control register in this block.
> 
> O.K. What does it have in the MII ID registers? Does Linux think it is
> a PHY and instantiating an generic PHY driver for it?
> 
> 	Andrew
Hi Andrew,
it is the PLL related registers, there is no PHY ID existed in MII 
register 2, 3 of this block, so it can't be instantiated as the generic 
PHY device.

Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Andrew Lunn]

> Hi Andrew,
> it is the PLL related registers, there is no PHY ID existed in MII register
> 2, 3 of this block, so it can't be instantiated as the generic PHY device.

Well, phylib is going to scan those ID registers, and if it finds
something other than 0xffff 0xffff in those two ID registers it is
going to think a PHY is there. And then if there is no driver using
that ID, it will instantiate a generic PHY.

You might be able to see this in /sys/bus/mdio_bus, especially if you
don't have a DT node representing the MDIO bus.

      Andrew

Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down

[Jie Luo]

On 7/2/2023 12:21 AM, Andrew Lunn wrote:
>> Hi Andrew,
>> it is the PLL related registers, there is no PHY ID existed in MII register
>> 2, 3 of this block, so it can't be instantiated as the generic PHY device.
> 
> Well, phylib is going to scan those ID registers, and if it finds
> something other than 0xffff 0xffff in those two ID registers it is
> going to think a PHY is there. And then if there is no driver using
> that ID, it will instantiate a generic PHY.
> 
> You might be able to see this in /sys/bus/mdio_bus, especially if you
> don't have a DT node representing the MDIO bus.
> 
>        Andrew
Okay, understand it. thanks Andrew for pointing this.
i will check it.