[PATCH v2] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[PATCH v2] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.

The CMN PLL driver did not account for the ref clock divider which is 2
for IPQ5018. Therefore, the computed rate was twice the actual output.

With the driver now accounting for the CMN PLL reference clock
divider (commit: 88c543fff756), set the correct reference clock rate.

Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
Changes in v2:
- Removed line break in commit message between Fixes and SOB tags
- Link to v1: https://patch.msgid.link/20260519-ipq5018-cmn-pll-rate-fix-v1-1-3c83a173c27f@outlook.com
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 6f8004a22a1f..f6cf2cca44eb 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -256,7 +256,7 @@ cmn_pll: clock-controller@9b000 {
 				      "sys";
 			#clock-cells = <1>;
 			assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
-			assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
+			assigned-clock-rates-u64 = /bits/ 64 <4800000000>;
 		};
 
 		qfprom: qfprom@a0000 {

---
base-commit: 80dd246accce631c328ea43294e53b2b2dd2aa32
change-id: 20260519-ipq5018-cmn-pll-rate-fix-388a379bfe10

Best regards,
--  
George Moussalem <george.moussalem@outlook.com>

Re: [PATCH v2] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[Konrad Dybcio]

On 5/21/26 9:55 AM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
> 
> The CMN PLL driver did not account for the ref clock divider which is 2
> for IPQ5018. Therefore, the computed rate was twice the actual output.
> 
> With the driver now accounting for the CMN PLL reference clock
> divider (commit: 88c543fff756), set the correct reference clock rate.
> 
> Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
> Changes in v2:
> - Removed line break in commit message between Fixes and SOB tags
> - Link to v1: https://patch.msgid.link/20260519-ipq5018-cmn-pll-rate-fix-v1-1-3c83a173c27f@outlook.com
> ---

I have no reference for this, but I trust you.. maybe +Kathiravan
could double-check

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[Kathiravan Thirumoorthy]

On 6/9/2026 8:42 PM, Konrad Dybcio wrote:
> On 5/21/26 9:55 AM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
>>
>> The CMN PLL driver did not account for the ref clock divider which is 2
>> for IPQ5018. Therefore, the computed rate was twice the actual output.
>>
>> With the driver now accounting for the CMN PLL reference clock
>> divider (commit: 88c543fff756), set the correct reference clock rate.
>>
>> Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>> ---
>> Changes in v2:
>> - Removed line break in commit message between Fixes and SOB tags
>> - Link to v1: https://patch.msgid.link/20260519-ipq5018-cmn-pll-rate-fix-v1-1-3c83a173c27f@outlook.com
>> ---
> I have no reference for this, but I trust you.. maybe +Kathiravan
> could double-check

Thanks Konrad. As per the HW doc and the commit 88c543fff756 ("clk: 
qcom: cmnpll: Account for reference clock divider"), default ref clock 
divider is 1 in IPQ5018.

@Jie, Can you help here?

>
> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Konrad

Re: [PATCH v2] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[Jie Luo]

On 6/10/2026 12:59 AM, Kathiravan Thirumoorthy wrote:
> 
> On 6/9/2026 8:42 PM, Konrad Dybcio wrote:
>> On 5/21/26 9:55 AM, George Moussalem via B4 Relay wrote:
>>> From: George Moussalem <george.moussalem@outlook.com>
>>>
>>> The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
>>>
>>> The CMN PLL driver did not account for the ref clock divider which is 2
>>> for IPQ5018. Therefore, the computed rate was twice the actual output.
>>>
>>> With the driver now accounting for the CMN PLL reference clock
>>> divider (commit: 88c543fff756), set the correct reference clock rate.
>>>
>>> Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
>>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>>> ---
>>> Changes in v2:
>>> - Removed line break in commit message between Fixes and SOB tags
>>> - Link to v1: https://patch.msgid.link/20260519-ipq5018-cmn-pll-rate-
>>> fix-v1-1-3c83a173c27f@outlook.com
>>> ---
>> I have no reference for this, but I trust you.. maybe +Kathiravan
>> could double-check
> 
> Thanks Konrad. As per the HW doc and the commit 88c543fff756 ("clk:
> qcom: cmnpll: Account for reference clock divider"), default ref clock
> divider is 1 in IPQ5018.
> 
> @Jie, Can you help here?
> 

Hello Konrad, Kathiravan,
As confirmed on the IPQ5018 RDP board, the ref clock divider is set to 2.

>>
>> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Konrad

Re: [PATCH v2] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[Konrad Dybcio]

On 6/10/26 5:10 AM, Jie Luo wrote:
> 
> 
> On 6/10/2026 12:59 AM, Kathiravan Thirumoorthy wrote:
>>
>> On 6/9/2026 8:42 PM, Konrad Dybcio wrote:
>>> On 5/21/26 9:55 AM, George Moussalem via B4 Relay wrote:
>>>> From: George Moussalem <george.moussalem@outlook.com>
>>>>
>>>> The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
>>>>
>>>> The CMN PLL driver did not account for the ref clock divider which is 2
>>>> for IPQ5018. Therefore, the computed rate was twice the actual output.
>>>>
>>>> With the driver now accounting for the CMN PLL reference clock
>>>> divider (commit: 88c543fff756), set the correct reference clock rate.
>>>>
>>>> Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
>>>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>>>> ---
>>>> Changes in v2:
>>>> - Removed line break in commit message between Fixes and SOB tags
>>>> - Link to v1: https://patch.msgid.link/20260519-ipq5018-cmn-pll-rate-
>>>> fix-v1-1-3c83a173c27f@outlook.com
>>>> ---
>>> I have no reference for this, but I trust you.. maybe +Kathiravan
>>> could double-check
>>
>> Thanks Konrad. As per the HW doc and the commit 88c543fff756 ("clk:
>> qcom: cmnpll: Account for reference clock divider"), default ref clock
>> divider is 1 in IPQ5018.
>>
>> @Jie, Can you help here?
>>
> 
> Hello Konrad, Kathiravan,
> As confirmed on the IPQ5018 RDP board, the ref clock divider is set to 2.

Thanks

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[Bjorn Andersson]

On Thu, 21 May 2026 11:55:58 +0400, George Moussalem wrote:
> The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
> 
> The CMN PLL driver did not account for the ref clock divider which is 2
> for IPQ5018. Therefore, the computed rate was twice the actual output.
> 
> With the driver now accounting for the CMN PLL reference clock
> divider (commit: 88c543fff756), set the correct reference clock rate.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate
      commit: 02320d694fa1124b8b77fcb52191141004ef7fbb

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>