[PATCH 0/3] drm/msm/adreno: Support for CLX feature on A8xx

[PATCH 0/3] drm/msm/adreno: Support for CLX feature on A8xx

[Akhil P Oommen]

Add support for Current Limit Extension (CLX) feature found on a few A8x
GPUs. This feature is required to limit the peak current consumption to
avoid HW spec violation on GX/MX rails.

Add the necessary HFI interface support to pass the recommended CLX and
IFF/PCLX limits tables to the GMU. And enable this feature on both A840
and X285 GPU by adding the repective configurations to the gpu catalog.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
---
Akhil P Oommen (3):
      drm/msm/a6xx: Add HFI support for CLX feature
      drm/msm/a6xx: Enable CLX feature on A840
      drm/msm/a8xx: Enable CLX feature on Adreno X2-85

 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 172 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h     |  15 +++
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c     |  71 ++++++++++++
 3 files changed, 258 insertions(+)
---
base-commit: b462608de92a7cac450781f9d8d4c7cf3ccf82db
change-id: 20260514-a8xx-clx-support-2ee492a88da1

Best regards,
-- 
Akhil P Oommen <akhilpo@oss.qualcomm.com>

[PATCH 1/3] drm/msm/a6xx: Add HFI support for CLX feature

[Akhil P Oommen]

Add support for Current Limit Extension (CLX) feature found on a few A8x
GPUs. This feature is required to limit the peak current consumption to
avoid HW spec violation on GX/MX rails.

Add the necessary HFI interface support to pass the recommended CLX and
IFF/PCLX limits tables to the GMU. Per-GPU configuration is consumed
from the catalog entries.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 ++++++++
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 71 +++++++++++++++++++++++++++++++++++
 2 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index eb431e5e00b1..f6a3f1924bb3 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -34,6 +34,19 @@ struct cpu_gpu_lock {
 	uint64_t regs[62];
 };
 
+struct a6xx_limits_tbl {
+	/** @tbl: List of limits table **/
+	struct a6xx_hfi_limits_tbl *tbl;
+	/** @count: Number of entries in the list **/
+	u32 count;
+};
+
+#define DECLARE_ADRENO_LIMITS_TABLE(name)	\
+static const struct a6xx_limits_tbl name = {	\
+	.tbl = name ## _tbl,			\
+	.count = ARRAY_SIZE(name ## _tbl),	\
+}
+
 /**
  * struct a6xx_info - a6xx specific information from device table
  *
@@ -54,6 +67,8 @@ struct a6xx_info {
 	u32 gmu_cgc_mode;
 	u32 prim_fifo_threshold;
 	const struct a6xx_bcm *bcms;
+	const struct a6xx_hfi_clx_table_v2_cmd *clx_tbl;
+	const struct a6xx_limits_tbl *limits_tbl;
 };
 
 struct a6xx_gpu {
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 487c2736f2b3..13ae34d0d898 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -886,6 +886,73 @@ static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu)
 	return 0;
 }
 
+static int a6xx_hfi_enable_iff_pclx(struct a6xx_gmu *gmu, const struct a6xx_limits_tbl *limits)
+{
+	struct a6xx_hfi_table_entry *entry;
+	struct a6xx_hfi_table *tbl;
+	size_t entry_size;
+	size_t size;
+	int ret;
+
+	if (!limits)
+		return 0;
+
+	ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFF_PCLX, 1, 0);
+	if (ret) {
+		DRM_DEV_ERROR(gmu->dev, "Unable to enable IFF PCLX (%d)\n", ret);
+		return ret;
+	}
+
+	entry_size = limits->count * sizeof(struct a6xx_hfi_limits_tbl);
+	size = sizeof(*tbl) + sizeof(*entry) + entry_size;
+
+	tbl = kzalloc(size, GFP_KERNEL);
+	if (!tbl)
+		return -ENOMEM;
+
+	tbl->type = HFI_TABLE_LIMITS_MIT;
+	entry = &tbl->entry[0];
+	entry->count = limits->count;
+	entry->stride = sizeof(struct a6xx_hfi_limits_tbl) >> 2;
+
+	memcpy(entry->data, limits->tbl, entry_size);
+
+	ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TABLE, tbl, size, NULL, 0);
+	if (ret)
+		DRM_DEV_ERROR(gmu->dev, "Unable to send PCLX table (%d)\n", ret);
+
+	kfree(tbl);
+	return ret;
+}
+
+static int a6xx_hfi_enable_clx(struct a6xx_gmu *gmu)
+{
+	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
+	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+	const struct a6xx_info *info = adreno_gpu->info->a6xx;
+	struct a6xx_hfi_clx_table_v2_cmd cmd = { 0 };
+	int ret;
+
+	if (!info->clx_tbl)
+		return 0;
+
+	ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_CLX, 1, 0);
+	if (ret) {
+		DRM_DEV_ERROR(gmu->dev, "Unable to enable CLX (%d)\n", ret);
+		return ret;
+	}
+
+	memcpy(&cmd, info->clx_tbl, sizeof(cmd));
+
+	ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_CLX_TBL, &cmd, sizeof(cmd), NULL, 0);
+	if (ret) {
+		DRM_DEV_ERROR(gmu->dev, "Unable to send CLX table (%d)\n", ret);
+		return ret;
+	}
+
+	return a6xx_hfi_enable_iff_pclx(gmu, info->limits_tbl);
+}
+
 static int a6xx_hfi_send_test(struct a6xx_gmu *gmu)
 {
 	struct a6xx_hfi_msg_test msg = { 0 };
@@ -987,6 +1054,10 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state)
 	if (ret)
 		return ret;
 
+	ret = a6xx_hfi_enable_clx(gmu);
+	if (ret)
+		return ret;
+
 	ret = a6xx_hfi_enable_ifpc(gmu);
 	if (ret)
 		return ret;

-- 
2.51.0

Re: [PATCH 1/3] drm/msm/a6xx: Add HFI support for CLX feature

[Konrad Dybcio]

On 5/15/26 10:07 PM, Akhil P Oommen wrote:
> Add support for Current Limit Extension (CLX) feature found on a few A8x
> GPUs. This feature is required to limit the peak current consumption to
> avoid HW spec violation on GX/MX rails.
> 
> Add the necessary HFI interface support to pass the recommended CLX and
> IFF/PCLX limits tables to the GMU. Per-GPU configuration is consumed
> from the catalog entries.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---

[...]

> +static int a6xx_hfi_enable_clx(struct a6xx_gmu *gmu)
> +{
> +	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
> +	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> +	const struct a6xx_info *info = adreno_gpu->info->a6xx;
> +	struct a6xx_hfi_clx_table_v2_cmd cmd = { 0 };
> +	int ret;
> +
> +	if (!info->clx_tbl)
> +		return 0;
> +
> +	ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_CLX, 1, 0);
> +	if (ret) {
> +		DRM_DEV_ERROR(gmu->dev, "Unable to enable CLX (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	memcpy(&cmd, info->clx_tbl, sizeof(cmd));

You're not adjusting anything (unlike the other function), so you can just pass
info->clx_tbl below

> +
> +	ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_CLX_TBL, &cmd, sizeof(cmd), NULL, 0);
> +	if (ret) {
> +		DRM_DEV_ERROR(gmu->dev, "Unable to send CLX table (%d)\n", ret);
> +		return ret;
> +	}

Konrad

Re: [PATCH 1/3] drm/msm/a6xx: Add HFI support for CLX feature

[Konrad Dybcio]

On 5/15/26 10:07 PM, Akhil P Oommen wrote:
> Add support for Current Limit Extension (CLX) feature found on a few A8x
> GPUs. This feature is required to limit the peak current consumption to
> avoid HW spec violation on GX/MX rails.
> 
> Add the necessary HFI interface support to pass the recommended CLX and
> IFF/PCLX limits tables to the GMU. Per-GPU configuration is consumed
> from the catalog entries.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 ++++++++
>  drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 71 +++++++++++++++++++++++++++++++++++
>  2 files changed, 86 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index eb431e5e00b1..f6a3f1924bb3 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -34,6 +34,19 @@ struct cpu_gpu_lock {
>  	uint64_t regs[62];
>  };
>  
> +struct a6xx_limits_tbl {
> +	/** @tbl: List of limits table **/
> +	struct a6xx_hfi_limits_tbl *tbl;
> +	/** @count: Number of entries in the list **/
> +	u32 count;
> +};
> +
> +#define DECLARE_ADRENO_LIMITS_TABLE(name)	\
> +static const struct a6xx_limits_tbl name = {	\
> +	.tbl = name ## _tbl,			\
> +	.count = ARRAY_SIZE(name ## _tbl),	\
> +}
> +
>  /**
>   * struct a6xx_info - a6xx specific information from device table
>   *
> @@ -54,6 +67,8 @@ struct a6xx_info {
>  	u32 gmu_cgc_mode;
>  	u32 prim_fifo_threshold;
>  	const struct a6xx_bcm *bcms;
> +	const struct a6xx_hfi_clx_table_v2_cmd *clx_tbl;
> +	const struct a6xx_limits_tbl *limits_tbl;
>  };
>  
>  struct a6xx_gpu {
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index 487c2736f2b3..13ae34d0d898 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -886,6 +886,73 @@ static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu)
>  	return 0;
>  }
>  
> +static int a6xx_hfi_enable_iff_pclx(struct a6xx_gmu *gmu, const struct a6xx_limits_tbl *limits)
> +{
> +	struct a6xx_hfi_table_entry *entry;
> +	struct a6xx_hfi_table *tbl;
> +	size_t entry_size;
> +	size_t size;
> +	int ret;
> +
> +	if (!limits)
> +		return 0;

Is this considered a valid configuation (CLX on without IFF_PCLX data)?
If not, let's throw an error here since it's only called from _enable_clx()

Konrad

[PATCH 2/3] drm/msm/a6xx: Enable CLX feature on A840

[Akhil P Oommen]

Add the A840 CLX domain table and the IFF/PCLX limits table to the
catalog. With the HFI plumbing in place, this enables the Current Limit
Extension (CLX) feature on Adreno 840.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 86 +++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 550ff3a9b82e..c503912a61c7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -2108,6 +2108,90 @@ static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = {
 };
 DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist);
 
+static const struct a6xx_hfi_clx_table_v2_cmd a840_clx_tbl = {
+	.version = (2 << 16) | 1,
+	.domain = {
+		/* GX DOMAIN */
+		{
+			.data = CLX_DATA(60, 5, 1, 1),
+			.clxt = 0,
+			.clxh = 0,
+			.urg_mode = 1,
+			.lkg_en = 0,
+			.curr_budget = 100,
+		},
+		/* MXG DOMAIN */
+		{
+			.data = CLX_DATA(60, 1, 1, 1),
+			.clxt = 0,
+			.clxh = 0,
+			.urg_mode = 1,
+			.lkg_en = 0,
+			.curr_budget = 50,
+		},
+	},
+};
+
+struct a6xx_hfi_limits_tbl a840_limits_tbl[] = {
+	{
+		.feature_id = GMU_MIT_IFF,
+		.domain = GMU_GX_DOMAIN,
+		.feature_rev = 0,
+		.cfg = {
+			.enable = 1,
+			.msg_path = 0,
+			.lkg_en = 0,
+			.mode = 0,
+			.sid = 12,
+			.mit_time = 5,
+			.curr_limit = 6000,
+		},
+	},
+	{
+		.feature_id = GMU_MIT_IFF,
+		.domain = GMU_MX_DOMAIN,
+		.feature_rev = 0,
+		.cfg = {
+			.enable = 1,
+			.msg_path = 0,
+			.lkg_en = 0,
+			.mode = 0,
+			.sid = 9,
+			.mit_time = 2000,
+			.curr_limit = 6000,
+		},
+	},
+	{
+		.feature_id = GMU_MIT_PCLX,
+		.domain = GMU_GX_DOMAIN,
+		.feature_rev = 0,
+		.cfg = {
+			.enable = 1,
+			.msg_path = 0,
+			.lkg_en = 0,
+			.mode = 0,
+			.sid = 7,
+			.mit_time = 3,
+			.curr_limit = 30000,
+		},
+	},
+	{
+		.feature_id = GMU_MIT_PCLX,
+		.domain = GMU_MX_DOMAIN,
+		.feature_rev = 0,
+		.cfg = {
+			.enable = 0,
+			.msg_path = 0,
+			.lkg_en = 0,
+			.mode = 0,
+			.sid = 7,
+			.mit_time = 3,
+			.curr_limit = 6000,
+		},
+	},
+};
+DECLARE_ADRENO_LIMITS_TABLE(a840_limits);
+
 static const struct adreno_info a8xx_gpus[] = {
 	{
 		.chip_ids = ADRENO_CHIP_IDS(0x44070001),
@@ -2185,6 +2269,8 @@ static const struct adreno_info a8xx_gpus[] = {
 				},
 				{ /* sentinel */ },
 			},
+			.clx_tbl = &a840_clx_tbl,
+			.limits_tbl = &a840_limits,
 		},
 		.preempt_record_size = 19708 * SZ_1K,
 		.speedbins = ADRENO_SPEEDBINS(

-- 
2.51.0

Re: [PATCH 2/3] drm/msm/a6xx: Enable CLX feature on A840

[Konrad Dybcio]

On 5/15/26 10:07 PM, Akhil P Oommen wrote:
> Add the A840 CLX domain table and the IFF/PCLX limits table to the
> catalog. With the HFI plumbing in place, this enables the Current Limit
> Extension (CLX) feature on Adreno 840.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 86 +++++++++++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 550ff3a9b82e..c503912a61c7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -2108,6 +2108,90 @@ static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = {
>  };
>  DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist);
>  
> +static const struct a6xx_hfi_clx_table_v2_cmd a840_clx_tbl = {
> +	.version = (2 << 16) | 1,

Is that major/minor or major=2 minor=0 patch=1? Please add a define

otherwise

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85

[Akhil P Oommen]

Add the CLX domain table and the IFF/PCLX limits tables to the catalog to
enable CLX feature support on Adreno X2-85 GPU present in the Glymur
chipset.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 86 +++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index c503912a61c7..9ad13eb173de 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1799,6 +1799,90 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
 };
 DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
 
+static const struct a6xx_hfi_clx_table_v2_cmd x285_clx_tbl = {
+	.version = (2 << 16) | 1,
+	.domain = {
+		/* GX DOMAIN */
+		{
+			.data = CLX_DATA(60, 11, 0, 1),
+			.clxt = 0,
+			.clxh = 0,
+			.urg_mode = 1,
+			.lkg_en = 0,
+			.curr_budget = 100,
+		},
+		/* MXG DOMAIN */
+		{
+			.data = CLX_DATA(60, 3, 1, 1),
+			.clxt = 0,
+			.clxh = 0,
+			.urg_mode = 1,
+			.lkg_en = 0,
+			.curr_budget = 100,
+		},
+	},
+};
+
+struct a6xx_hfi_limits_tbl x285_limits_tbl[] = {
+	{
+		.feature_id = GMU_MIT_IFF,
+		.domain = GMU_GX_DOMAIN,
+		.feature_rev = 0,
+		.cfg = {
+			.enable = 1,
+			.msg_path = 0,
+			.lkg_en = 0,
+			.mode = 0,
+			.sid = 12,
+			.mit_time = 5,
+			.curr_limit = 18000,
+		},
+	},
+	{
+		.feature_id = GMU_MIT_IFF,
+		.domain = GMU_MX_DOMAIN,
+		.feature_rev = 0,
+		.cfg = {
+			.enable = 1,
+			.msg_path = 0,
+			.lkg_en = 0,
+			.mode = 0,
+			.sid = 18,
+			.mit_time = 2000,
+			.curr_limit = 6000,
+		},
+	},
+	{
+		.feature_id = GMU_MIT_PCLX,
+		.domain = GMU_GX_DOMAIN,
+		.feature_rev = 0,
+		.cfg = {
+			.enable = 1,
+			.msg_path = 0,
+			.lkg_en = 0,
+			.mode = 0,
+			.sid = 6,
+			.mit_time = 3,
+			.curr_limit = 66000,
+		},
+	},
+	{
+		.feature_id = GMU_MIT_PCLX,
+		.domain = GMU_MX_DOMAIN,
+		.feature_rev = 0,
+		.cfg = {
+			.enable = 0,
+			.msg_path = 0,
+			.lkg_en = 0,
+			.mode = 0,
+			.sid = 6,
+			.mit_time = 3,
+			.curr_limit = 18000,
+		},
+	},
+};
+DECLARE_ADRENO_LIMITS_TABLE(x285_limits);
+
 static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
 	{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
 	{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
@@ -2227,6 +2311,8 @@ static const struct adreno_info a8xx_gpus[] = {
 				},
 				{ /* sentinel */ },
 			},
+			.clx_tbl = &x285_clx_tbl,
+			.limits_tbl = &x285_limits,
 		},
 		.speedbins = ADRENO_SPEEDBINS(
 			{ 0,   0 },

-- 
2.51.0

Re: [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85

[Konrad Dybcio]

On 5/15/26 10:07 PM, Akhil P Oommen wrote:
> Add the CLX domain table and the IFF/PCLX limits tables to the catalog to
> enable CLX feature support on Adreno X2-85 GPU present in the Glymur
> chipset.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85

[Bjorn Andersson]

On Sat, May 16, 2026 at 01:37:51AM +0530, Akhil P Oommen wrote:
> Add the CLX domain table and the IFF/PCLX limits tables to the catalog to
> enable CLX feature support on Adreno X2-85 GPU present in the Glymur
> chipset.
> 

This patch landed in next-20261001 and while it works on my Glymur CRD
(COB), on the Asus Zenbook A14 I see the following failure during boot:

[    4.843643] platform 3d6c000.gmu: [drm:a6xx_hfi_wait_for_msg_interrupt [msm]] *ERROR* Message HFI_H2F_MSG_GX_BW_PERF_VOTE id 11 timed out waiting for response
[    4.853804] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob [msm]] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
[    4.853878] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu [msm]] *ERROR* gpu hw init failed: -110
[    4.863980] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob [msm]] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
[    4.864038] platform 3d6c000.gmu: [drm:a6xx_hfi_stop [msm]] *ERROR* HFI queue 2 is not empty
[    5.128548] ------------[ cut here ]------------

And then as one can expect there's no more GPU.

Reverting this single patch makes next-20261001 work again.

#regzb introduced: 93b6c8d10fad ("drm/msm/a8xx: Enable CLX feature on Adreno X2-85")

Regards,
Bjorn

> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 86 +++++++++++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index c503912a61c7..9ad13eb173de 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1799,6 +1799,90 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
>  };
>  DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
>  
> +static const struct a6xx_hfi_clx_table_v2_cmd x285_clx_tbl = {
> +	.version = (2 << 16) | 1,
> +	.domain = {
> +		/* GX DOMAIN */
> +		{
> +			.data = CLX_DATA(60, 11, 0, 1),
> +			.clxt = 0,
> +			.clxh = 0,
> +			.urg_mode = 1,
> +			.lkg_en = 0,
> +			.curr_budget = 100,
> +		},
> +		/* MXG DOMAIN */
> +		{
> +			.data = CLX_DATA(60, 3, 1, 1),
> +			.clxt = 0,
> +			.clxh = 0,
> +			.urg_mode = 1,
> +			.lkg_en = 0,
> +			.curr_budget = 100,
> +		},
> +	},
> +};
> +
> +struct a6xx_hfi_limits_tbl x285_limits_tbl[] = {
> +	{
> +		.feature_id = GMU_MIT_IFF,
> +		.domain = GMU_GX_DOMAIN,
> +		.feature_rev = 0,
> +		.cfg = {
> +			.enable = 1,
> +			.msg_path = 0,
> +			.lkg_en = 0,
> +			.mode = 0,
> +			.sid = 12,
> +			.mit_time = 5,
> +			.curr_limit = 18000,
> +		},
> +	},
> +	{
> +		.feature_id = GMU_MIT_IFF,
> +		.domain = GMU_MX_DOMAIN,
> +		.feature_rev = 0,
> +		.cfg = {
> +			.enable = 1,
> +			.msg_path = 0,
> +			.lkg_en = 0,
> +			.mode = 0,
> +			.sid = 18,
> +			.mit_time = 2000,
> +			.curr_limit = 6000,
> +		},
> +	},
> +	{
> +		.feature_id = GMU_MIT_PCLX,
> +		.domain = GMU_GX_DOMAIN,
> +		.feature_rev = 0,
> +		.cfg = {
> +			.enable = 1,
> +			.msg_path = 0,
> +			.lkg_en = 0,
> +			.mode = 0,
> +			.sid = 6,
> +			.mit_time = 3,
> +			.curr_limit = 66000,
> +		},
> +	},
> +	{
> +		.feature_id = GMU_MIT_PCLX,
> +		.domain = GMU_MX_DOMAIN,
> +		.feature_rev = 0,
> +		.cfg = {
> +			.enable = 0,
> +			.msg_path = 0,
> +			.lkg_en = 0,
> +			.mode = 0,
> +			.sid = 6,
> +			.mit_time = 3,
> +			.curr_limit = 18000,
> +		},
> +	},
> +};
> +DECLARE_ADRENO_LIMITS_TABLE(x285_limits);
> +
>  static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
>  	{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
>  	{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
> @@ -2227,6 +2311,8 @@ static const struct adreno_info a8xx_gpus[] = {
>  				},
>  				{ /* sentinel */ },
>  			},
> +			.clx_tbl = &x285_clx_tbl,
> +			.limits_tbl = &x285_limits,
>  		},
>  		.speedbins = ADRENO_SPEEDBINS(
>  			{ 0,   0 },
> 
> -- 
> 2.51.0
> 
> 

Re: [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85

[Oleg Keri]

Same on a Lenovo Yoga Slim 7x Gen 11 (Glymur) with next-20261001, GMU
firmware v5.2.38:

[    1.632277] platform 3d6c000.gmu: [drm:a6xx_hfi_wait_for_msg_interrupt] *ERROR* Message HFI_H2F_MSG_GX_BW_PERF_VOTE id 11 timed out waiting for response
[    1.642345] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
[    1.642360] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* gpu hw init failed: -110
[    8.053367] platform 3d6c000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU firmware initialization timed out
[    8.053584] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* Couldn't power up the GPU: -110

Compositor fails on the first start and works on the second.

Reverting this patch fixes it here as well.

Oleg

Re: [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85

[Rob Clark]

On Fri, Oct 2, 2026 at 10:47 AM Oleg Keri <okerixx@gmail.com> wrote:
>
> Same on a Lenovo Yoga Slim 7x Gen 11 (Glymur) with next-20261001, GMU
> firmware v5.2.38:
>
> [    1.632277] platform 3d6c000.gmu: [drm:a6xx_hfi_wait_for_msg_interrupt] *ERROR* Message HFI_H2F_MSG_GX_BW_PERF_VOTE id 11 timed out waiting for response
> [    1.642345] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
> [    1.642360] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* gpu hw init failed: -110
> [    8.053367] platform 3d6c000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU firmware initialization timed out
> [    8.053584] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* Couldn't power up the GPU: -110
>
> Compositor fails on the first start and works on the second.
>
> Reverting this patch fixes it here as well.

Interesting.. I'd been using this patch, but cherry-picked on v7.3-rc3
(on glymur slim7x) for a few weeks with no issue

Can you share `dmesg | grep drm`?  In my case the initrd is missing fw
so gpu is initialized later, I guess when the compositor starts.

BR,
-R

Re: [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85

[Oleg Keri]

On Fri, Oct 02, 2026, Rob Clark wrote:
> Can you share `dmesg | grep drm`?  In my case the initrd is missing fw
> so gpu is initialized later, I guess when the compositor starts.

Here it is. The kernel is built without modules and with the firmware
built in, so the GPU is brought up right at boot. The GMU firmware is
gen80100_gmu.bin from linux-firmware (v5.2.38).

[    0.620358] msm_dpu ae01000.display-controller: [drm] Using Transparent Hugepage
[    0.621120] [drm:dpu_kms_hw_init:1168] dpu hardware revision:0xc0020000
[    0.625910] [drm] Initialized msm 1.13.0 for ae01000.display-controller on minor 0
[    0.626015] msm_dpu ae01000.display-controller: [drm:adreno_request_fw] loaded qcom/gen80100_sqe.fw from new location
[    0.626115] msm_dpu ae01000.display-controller: [drm:adreno_request_fw] loaded qcom/gen80100_gmu.bin from new location
[    0.626994] [drm] Loaded GMU firmware v5.2.38
[    1.632277] platform 3d6c000.gmu: [drm:a6xx_hfi_wait_for_msg_interrupt] *ERROR* Message HFI_H2F_MSG_GX_BW_PERF_VOTE id 11 timed out waiting for response
[    1.642345] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
[    1.642360] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* gpu hw init failed: -110
[    1.652389] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
[    1.652401] platform 3d6c000.gmu: [drm:a6xx_hfi_stop] *ERROR* HFI queue 2 is not empty
[    1.858322] msm_dpu ae01000.display-controller: [drm] fb0: msmdrmfb frame buffer device
[    8.053367] platform 3d6c000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU firmware initialization timed out
[    8.053584] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* Couldn't power up the GPU: -110
[    8.187443] platform 3d6c000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU firmware initialization timed out
[    8.187650] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* Couldn't power up the GPU: -110

Oleg

Re: [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85

[Rob Clark]

On Fri, Oct 2, 2026 at 11:29 AM Oleg Keri <okerixx@gmail.com> wrote:
>
> On Fri, Oct 02, 2026, Rob Clark wrote:
> > Can you share `dmesg | grep drm`?  In my case the initrd is missing fw
> > so gpu is initialized later, I guess when the compositor starts.
>
> Here it is. The kernel is built without modules and with the firmware
> built in, so the GPU is brought up right at boot. The GMU firmware is
> gen80100_gmu.bin from linux-firmware (v5.2.38).
>
> [    0.620358] msm_dpu ae01000.display-controller: [drm] Using Transparent Hugepage
> [    0.621120] [drm:dpu_kms_hw_init:1168] dpu hardware revision:0xc0020000
> [    0.625910] [drm] Initialized msm 1.13.0 for ae01000.display-controller on minor 0
> [    0.626015] msm_dpu ae01000.display-controller: [drm:adreno_request_fw] loaded qcom/gen80100_sqe.fw from new location
> [    0.626115] msm_dpu ae01000.display-controller: [drm:adreno_request_fw] loaded qcom/gen80100_gmu.bin from new location
> [    0.626994] [drm] Loaded GMU firmware v5.2.38
> [    1.632277] platform 3d6c000.gmu: [drm:a6xx_hfi_wait_for_msg_interrupt] *ERROR* Message HFI_H2F_MSG_GX_BW_PERF_VOTE id 11 timed out waiting for response
> [    1.642345] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
> [    1.642360] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* gpu hw init failed: -110
> [    1.652389] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
> [    1.652401] platform 3d6c000.gmu: [drm:a6xx_hfi_stop] *ERROR* HFI queue 2 is not empty
> [    1.858322] msm_dpu ae01000.display-controller: [drm] fb0: msmdrmfb frame buffer device
> [    8.053367] platform 3d6c000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU firmware initialization timed out
> [    8.053584] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* Couldn't power up the GPU: -110
> [    8.187443] platform 3d6c000.gmu: [drm:a6xx_gmu_resume] *ERROR* GMU firmware initialization timed out
> [    8.187650] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu] *ERROR* Couldn't power up the GPU: -110
>

Ok, now it would be interesting to compare the same from Bjorn's CRD
vs zenbook..

BR,
-R

Re: [PATCH 3/3] drm/msm/a8xx: Enable CLX feature on Adreno X2-85

[Akhil P Oommen]

On 10/2/2026 8:08 PM, Bjorn Andersson wrote:
> On Sat, May 16, 2026 at 01:37:51AM +0530, Akhil P Oommen wrote:
>> Add the CLX domain table and the IFF/PCLX limits tables to the catalog to
>> enable CLX feature support on Adreno X2-85 GPU present in the Glymur
>> chipset.
>>
> 
> This patch landed in next-20261001 and while it works on my Glymur CRD
> (COB), on the Asus Zenbook A14 I see the following failure during boot:
> 
> [    4.843643] platform 3d6c000.gmu: [drm:a6xx_hfi_wait_for_msg_interrupt [msm]] *ERROR* Message HFI_H2F_MSG_GX_BW_PERF_VOTE id 11 timed out waiting for response
> [    4.853804] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob [msm]] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
> [    4.853878] msm_dpu ae01000.display-controller: [drm:adreno_load_gpu [msm]] *ERROR* gpu hw init failed: -110
> [    4.863980] platform 3d6c000.gmu: [drm:a6xx_gmu_set_oob [msm]] *ERROR* Timeout waiting for GMU OOB set GPU_SET: 0x4
> [    4.864038] platform 3d6c000.gmu: [drm:a6xx_hfi_stop [msm]] *ERROR* HFI queue 2 is not empty
> [    5.128548] ------------[ cut here ]------------
> 
> And then as one can expect there's no more GPU.
> 
> Reverting this single patch makes next-20261001 work again.
> 
> #regzb introduced: 93b6c8d10fad ("drm/msm/a8xx: Enable CLX feature on Adreno X2-85")

Could you please try this fix?

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 662f09bec9d5..52cd60272870 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1241,8 +1241,12 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)
                        goto done;
                }

-               ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ |
-                                            QCOM_SCM_GPU_TSENSE_EN_REQ);
+               u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ | QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+               if (adreno_gpu->info->a6xx->clx_tbl)
+                       gpu_req |= QCOM_SCM_GPU_CLX_EN_REQ;
+
+               ret = qcom_scm_gpu_init_regs(gpu_req);
                if (ret) {
                        dev_warn_once(gpu->dev->dev,
                                "SCM call failed\n");
> 
> Regards,
> Bjorn
> 
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 86 +++++++++++++++++++++++++++++++
>>  1 file changed, 86 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index c503912a61c7..9ad13eb173de 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1799,6 +1799,90 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
>>  };
>>  DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
>>  
>> +static const struct a6xx_hfi_clx_table_v2_cmd x285_clx_tbl = {
>> +	.version = (2 << 16) | 1,
>> +	.domain = {
>> +		/* GX DOMAIN */
>> +		{
>> +			.data = CLX_DATA(60, 11, 0, 1),
>> +			.clxt = 0,
>> +			.clxh = 0,
>> +			.urg_mode = 1,
>> +			.lkg_en = 0,
>> +			.curr_budget = 100,
>> +		},
>> +		/* MXG DOMAIN */
>> +		{
>> +			.data = CLX_DATA(60, 3, 1, 1),
>> +			.clxt = 0,
>> +			.clxh = 0,
>> +			.urg_mode = 1,
>> +			.lkg_en = 0,
>> +			.curr_budget = 100,
>> +		},
>> +	},
>> +};
>> +
>> +struct a6xx_hfi_limits_tbl x285_limits_tbl[] = {
>> +	{
>> +		.feature_id = GMU_MIT_IFF,
>> +		.domain = GMU_GX_DOMAIN,
>> +		.feature_rev = 0,
>> +		.cfg = {
>> +			.enable = 1,
>> +			.msg_path = 0,
>> +			.lkg_en = 0,
>> +			.mode = 0,
>> +			.sid = 12,
>> +			.mit_time = 5,
>> +			.curr_limit = 18000,
>> +		},
>> +	},
>> +	{
>> +		.feature_id = GMU_MIT_IFF,
>> +		.domain = GMU_MX_DOMAIN,
>> +		.feature_rev = 0,
>> +		.cfg = {
>> +			.enable = 1,
>> +			.msg_path = 0,
>> +			.lkg_en = 0,
>> +			.mode = 0,
>> +			.sid = 18,
>> +			.mit_time = 2000,
>> +			.curr_limit = 6000,
>> +		},
>> +	},
>> +	{
>> +		.feature_id = GMU_MIT_PCLX,
>> +		.domain = GMU_GX_DOMAIN,
>> +		.feature_rev = 0,
>> +		.cfg = {
>> +			.enable = 1,
>> +			.msg_path = 0,
>> +			.lkg_en = 0,
>> +			.mode = 0,
>> +			.sid = 6,
>> +			.mit_time = 3,
>> +			.curr_limit = 66000,
>> +		},
>> +	},
>> +	{
>> +		.feature_id = GMU_MIT_PCLX,
>> +		.domain = GMU_MX_DOMAIN,
>> +		.feature_rev = 0,
>> +		.cfg = {
>> +			.enable = 0,
>> +			.msg_path = 0,
>> +			.lkg_en = 0,
>> +			.mode = 0,
>> +			.sid = 6,
>> +			.mit_time = 3,
>> +			.curr_limit = 18000,
>> +		},
>> +	},
>> +};
>> +DECLARE_ADRENO_LIMITS_TABLE(x285_limits);
>> +
>>  static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
>>  	{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
>>  	{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
>> @@ -2227,6 +2311,8 @@ static const struct adreno_info a8xx_gpus[] = {
>>  				},
>>  				{ /* sentinel */ },
>>  			},
>> +			.clx_tbl = &x285_clx_tbl,
>> +			.limits_tbl = &x285_limits,
>>  		},
>>  		.speedbins = ADRENO_SPEEDBINS(
>>  			{ 0,   0 },
>>
>> -- 
>> 2.51.0
>>
>>

-Akhil