From: xiong <xiong@qca.qualcomm.com>
To: <davem@davemloft.net>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <qca-linux-team@qualcomm.com>, <nic-devel@qualcomm.com>,
xiong <xiong@qca.qualcomm.com>
Subject: [PATCH 18/37] atl1c: refine reg definition of REG_MASTER_CTRL
Date: Fri, 13 Apr 2012 08:14:43 +0800 [thread overview]
Message-ID: <1334276102-15866-19-git-send-email-xiong@qca.qualcomm.com> (raw)
In-Reply-To: <1334276102-15866-1-git-send-email-xiong@qca.qualcomm.com>
refine/update register REG_MASTER_CTRL definition according with
hardware spec.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 41 +++++++++++++----------
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 2 +-
2 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index a4fd36e..8246c29 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -188,26 +188,31 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
#define REG_LTSSM_ID_CTRL 0x12FC
#define LTSSM_ID_EN_WRO 0x1000
+
+
/* Selene Master Control Register */
#define REG_MASTER_CTRL 0x1400
-#define MASTER_CTRL_SOFT_RST 0x1
-#define MASTER_CTRL_TEST_MODE_MASK 0x3
-#define MASTER_CTRL_TEST_MODE_SHIFT 2
-#define MASTER_CTRL_BERT_START 0x10
-#define MASTER_CTRL_OOB_DIS_OFF 0x40
-#define MASTER_CTRL_SA_TIMER_EN 0x80
-#define MASTER_CTRL_MTIMER_EN 0x100
-#define MASTER_CTRL_MANUAL_INT 0x200
-#define MASTER_CTRL_TX_ITIMER_EN 0x400
-#define MASTER_CTRL_RX_ITIMER_EN 0x800
-#define MASTER_CTRL_CLK_SEL_DIS 0x1000
-#define MASTER_CTRL_CLK_SWH_MODE 0x2000
-#define MASTER_CTRL_INT_RDCLR 0x4000
-#define MASTER_CTRL_REV_NUM_SHIFT 16
-#define MASTER_CTRL_REV_NUM_MASK 0xff
-#define MASTER_CTRL_DEV_ID_SHIFT 24
-#define MASTER_CTRL_DEV_ID_MASK 0x7f
-#define MASTER_CTRL_OTP_SEL 0x80000000
+#define MASTER_CTRL_OTP_SEL BIT(31)
+#define MASTER_DEV_NUM_MASK 0x7FUL
+#define MASTER_DEV_NUM_SHIFT 24
+#define MASTER_REV_NUM_MASK 0xFFUL
+#define MASTER_REV_NUM_SHIFT 16
+#define MASTER_CTRL_INT_RDCLR BIT(14)
+#define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from
+ * serdes, not sw to 25M */
+#define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */
+#define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */
+#define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */
+#define MASTER_CTRL_MANUTIMER_EN BIT(8)
+#define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */
+#define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */
+#define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */
+#define MASTER_CTRL_BERT_START BIT(4)
+#define MASTER_PCIE_TSTMOD_MASK 3UL
+#define MASTER_PCIE_TSTMOD_SHIFT 2
+#define MASTER_PCIE_RST BIT(1)
+#define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */
+#define DMA_MAC_RST_TO 50
/* Timer Initial Value Register */
#define REG_MANUAL_TIMER_INIT 0x1404
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 9295aee..4fc824d 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -1177,7 +1177,7 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
* clearing, and should clear within a microsecond.
*/
AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
- master_ctrl_data |= MASTER_CTRL_OOB_DIS_OFF;
+ master_ctrl_data |= MASTER_CTRL_OOB_DIS;
AT_WRITE_REGW(hw, REG_MASTER_CTRL, ((master_ctrl_data | MASTER_CTRL_SOFT_RST)
& 0xFFFF));
--
1.7.7
next prev parent reply other threads:[~2012-04-13 0:24 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-13 0:14 [PATCH 00/37] atl1c: update hardware settings xiong
2012-04-13 0:14 ` [PATCH 01/37] atl1c: update author contact info & company/driver desciption xiong
2012-04-13 0:14 ` [PATCH 02/37] atl1c: remove multiple-RX-Q code xiong
2012-04-13 0:14 ` [PATCH 03/37] atl1c: remove HDS register xiong
2012-04-13 0:14 ` [PATCH 04/37] atl1c: remove VPD register xiong
2012-04-14 0:45 ` David Miller
2012-04-14 9:12 ` Huang, Xiong
2012-04-14 14:22 ` Ben Hutchings
2012-04-14 18:24 ` David Miller
2012-04-17 8:36 ` Huang, Xiong
2012-04-13 0:14 ` [PATCH 05/37] atl1c: remove SMB/CMB DMA related code xiong
2012-04-13 0:14 ` [PATCH 06/37] atl1c: split 2 32bit registers of TPD to 4 16bit registers xiong
2012-04-13 0:14 ` [PATCH 07/37] atl1c: remove code related to rxq 1/2/3 xiong
2012-04-13 0:14 ` [PATCH 08/37] atl1c: wrong register used to stop TXQ xiong
2012-04-13 0:14 ` [PATCH 09/37] atl1c: correct wrong definition of REG_DMA_CTRL xiong
2012-04-13 0:14 ` [PATCH 10/37] atl1c: remove dmaw_block xiong
2012-04-13 0:14 ` [PATCH 11/37] atl1c: using fixed TXQ configuration for l2cb and l1c xiong
2012-04-13 0:14 ` [PATCH 12/37] atl1c: restore max-read-request-size in Device Conrol Register xiong
2012-04-13 17:02 ` Ben Hutchings
2012-04-14 10:39 ` Huang, Xiong
2012-04-13 0:14 ` [PATCH 13/37] atl1c: threshold for ASPM is changed based on chip capability xiong
2012-04-13 0:14 ` [PATCH 14/37] atl1c: add module parameter for l1c_wait_until_idle xiong
2012-04-13 0:14 ` [PATCH 15/37] atl1c: update right threshold for TSO xiong
2012-04-13 0:14 ` [PATCH 16/37] atl1c: remove dmar_dly_cnt and dmaw_dly_cnt xiong
2012-04-13 0:14 ` [PATCH 17/37] atl1c: clear PCIE error status in atl1c_reset_pcie xiong
2012-04-13 0:14 ` xiong [this message]
2012-04-13 0:14 ` [PATCH 19/37] atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch xiong
2012-04-13 0:14 ` [PATCH 20/37] atl1c: refine/update ASPM configuration xiong
2012-04-13 0:14 ` [PATCH 21/37] atl1c: refine atl1c_pcie_patch xiong
2012-04-13 0:14 ` [PATCH 22/37] atl1c: fix WoL(magic) issue for l2cb 1.1 xiong
2012-04-13 0:14 ` [PATCH 23/37] atl1c: remove MDIO_REG_ADDR_MASK in atl1c_mdio_read/write xiong
2012-04-13 0:14 ` [PATCH 24/37] atl1c: remove REG_PHY_STATUS xiong
2012-04-13 0:14 ` [PATCH 25/37] atl1c: refine phy-register read/write function xiong
2012-04-13 0:14 ` [PATCH 26/37] atl1c: remove PHY contrl in atl1c_reset_pcie xiong
2012-04-13 0:14 ` [PATCH 27/37] atl1c: refine SERDES-clock related code xiong
2012-04-13 0:14 ` [PATCH 28/37] atl1c: remove PHY polling from atl1c_open xiong
2012-04-13 0:14 ` [PATCH 29/37] atl1c: update PHY reset related routine xiong
2012-04-13 0:14 ` [PATCH 30/37] atl1c: remove PHY reset/init for link down event xiong
2012-04-13 0:14 ` [PATCH 31/37] atl1c: add function atl1c_power_saving xiong
2012-04-13 0:14 ` [PATCH 32/37] atl1c: refine start/enable code for MAC module xiong
2012-04-13 0:14 ` [PATCH 33/37] atl1c: add PHY link event(up/down) patch xiong
2012-04-13 0:14 ` [PATCH 34/37] atl1c: clear WoL status when reset pcie xiong
2012-04-13 0:15 ` [PATCH 35/37] atl1c: remove code of closing register writable attribution xiong
2012-04-13 0:15 ` [PATCH 36/37] atl1c: refine mac address related code xiong
2012-04-13 0:15 ` [PATCH 37/37] atl1c: cancel task when interface closed xiong
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