From: xiong <xiong@qca.qualcomm.com>
To: <davem@davemloft.net>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <qca-linux-team@qualcomm.com>, <nic-devel@qualcomm.com>,
xiong <xiong@qca.qualcomm.com>
Subject: [PATCH 27/37] atl1c: refine SERDES-clock related code
Date: Fri, 13 Apr 2012 08:14:52 +0800 [thread overview]
Message-ID: <1334276102-15866-28-git-send-email-xiong@qca.qualcomm.com> (raw)
In-Reply-To: <1334276102-15866-1-git-send-email-xiong@qca.qualcomm.com>
bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause
the write-reg operation fail without cable connected.
so, please do connect the cable when apply this patch to the driver
to make sure these 2bits are cleared by new driver.
The revised code is move to al1c_reset_mac.
SERDES register definition is refined as well.
when do reset MAC, speed/duplex control right should be transferred
to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW.
SERDES register definition is refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c | 2 +-
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 34 +++++++++++------
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 40 +++++++++++++-------
3 files changed, 49 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c b/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
index ce63615..ac44538 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
@@ -153,7 +153,7 @@ static void atl1c_get_regs(struct net_device *netdev,
AT_READ_REG(hw, REG_LINK_CTRL, p++);
AT_READ_REG(hw, REG_IDLE_STATUS, p++);
AT_READ_REG(hw, REG_MDIO_CTRL, p++);
- AT_READ_REG(hw, REG_SERDES_LOCK, p++);
+ AT_READ_REG(hw, REG_SERDES, p++);
AT_READ_REG(hw, REG_MAC_CTRL, p++);
AT_READ_REG(hw, REG_MAC_IPG_IFG, p++);
AT_READ_REG(hw, REG_MAC_STA_ADDR, p++);
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 85623cc..672217d 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -366,18 +366,28 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
#define BIST1_FUSE_FLAG 0x4
/* SerDes Lock Detect Control and Status Register */
-#define REG_SERDES_LOCK 0x1424
-#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
- * comes from Analog SerDes */
-#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
-#define SERDES_LOCK_STS_SELFB_PLL_SHIFT 0xE
-#define SERDES_LOCK_STS_SELFB_PLL_MASK 0x3
-#define SERDES_OVCLK_18_25 0x0
-#define SERDES_OVCLK_12_18 0x1
-#define SERDES_OVCLK_0_4 0x2
-#define SERDES_OVCLK_4_12 0x3
-#define SERDES_MAC_CLK_SLOWDOWN 0x20000
-#define SERDES_PYH_CLK_SLOWDOWN 0x40000
+#define REG_SERDES 0x1424
+#define SERDES_PHY_CLK_SLOWDOWN BIT(18)
+#define SERDES_MAC_CLK_SLOWDOWN BIT(17)
+#define SERDES_SELFB_PLL_MASK 0x3UL
+#define SERDES_SELFB_PLL_SHIFT 14
+#define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */
+#define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */
+#define SERDES_BUFS_RX_EN BIT(11)
+#define SERDES_PD_RX BIT(10)
+#define SERDES_PLL_EN BIT(9)
+#define SERDES_EN BIT(8)
+#define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */
+#define SERDES_SELFB_PLL_CSR_MASK 0x3UL
+#define SERDES_SELFB_PLL_CSR_SHIFT 4
+#define SERDES_SELFB_PLL_CSR_4 3 /* 4-12% OV-CLK */
+#define SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */
+#define SERDES_SELFB_PLL_CSR_12 1 /* 12-18% OV-CLK */
+#define SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */
+#define SERDES_VCO_SLOW BIT(3)
+#define SERDES_VCO_FAST BIT(2)
+#define SERDES_LOCK_DETECT_EN BIT(1)
+#define SERDES_LOCK_DETECT BIT(0)
/* MAC Control Register */
#define REG_MAC_CTRL 0x1480
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index ef431c9..a85f2af 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -1002,7 +1002,6 @@ static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
adapter->tpd_ring;
- u32 data;
/* TPD */
AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
@@ -1046,13 +1045,6 @@ static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
}
- if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d_2) {
- /* Power Saving for L2c_B */
- AT_READ_REG(hw, REG_SERDES_LOCK, &data);
- data |= SERDES_MAC_CLK_SLOWDOWN;
- data |= SERDES_PYH_CLK_SLOWDOWN;
- AT_WRITE_REG(hw, REG_SERDES_LOCK, data);
- }
/* Load all of base address above */
AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
}
@@ -1175,7 +1167,7 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
{
struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
struct pci_dev *pdev = adapter->pdev;
- u32 master_ctrl_data = 0;
+ u32 ctrl_data = 0;
AT_WRITE_REG(hw, REG_IMR, 0);
AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
@@ -1187,10 +1179,9 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
* the current PCI configuration. The global reset bit is self-
* clearing, and should clear within a microsecond.
*/
- AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
- master_ctrl_data |= MASTER_CTRL_OOB_DIS;
- AT_WRITE_REG(hw, REG_MASTER_CTRL,
- master_ctrl_data | MASTER_CTRL_SOFT_RST);
+ AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
+ ctrl_data |= MASTER_CTRL_OOB_DIS;
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
AT_WRITE_FLUSH(hw);
msleep(10);
@@ -1202,7 +1193,28 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
" disabled for 10ms second\n");
return -1;
}
- AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
+
+ /* driver control speed/duplex */
+ AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
+ AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
+
+ /* clk switch setting */
+ AT_READ_REG(hw, REG_SERDES, &ctrl_data);
+ switch (hw->nic_type) {
+ case athr_l2c_b:
+ ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
+ SERDES_MAC_CLK_SLOWDOWN);
+ AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
+ break;
+ case athr_l2c_b2:
+ case athr_l1d_2:
+ ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
+ AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
+ break;
+ default:
+ break;
+ }
return 0;
}
--
1.7.7
next prev parent reply other threads:[~2012-04-13 0:19 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-13 0:14 [PATCH 00/37] atl1c: update hardware settings xiong
2012-04-13 0:14 ` [PATCH 01/37] atl1c: update author contact info & company/driver desciption xiong
2012-04-13 0:14 ` [PATCH 02/37] atl1c: remove multiple-RX-Q code xiong
2012-04-13 0:14 ` [PATCH 03/37] atl1c: remove HDS register xiong
2012-04-13 0:14 ` [PATCH 04/37] atl1c: remove VPD register xiong
2012-04-14 0:45 ` David Miller
2012-04-14 9:12 ` Huang, Xiong
2012-04-14 14:22 ` Ben Hutchings
2012-04-14 18:24 ` David Miller
2012-04-17 8:36 ` Huang, Xiong
2012-04-13 0:14 ` [PATCH 05/37] atl1c: remove SMB/CMB DMA related code xiong
2012-04-13 0:14 ` [PATCH 06/37] atl1c: split 2 32bit registers of TPD to 4 16bit registers xiong
2012-04-13 0:14 ` [PATCH 07/37] atl1c: remove code related to rxq 1/2/3 xiong
2012-04-13 0:14 ` [PATCH 08/37] atl1c: wrong register used to stop TXQ xiong
2012-04-13 0:14 ` [PATCH 09/37] atl1c: correct wrong definition of REG_DMA_CTRL xiong
2012-04-13 0:14 ` [PATCH 10/37] atl1c: remove dmaw_block xiong
2012-04-13 0:14 ` [PATCH 11/37] atl1c: using fixed TXQ configuration for l2cb and l1c xiong
2012-04-13 0:14 ` [PATCH 12/37] atl1c: restore max-read-request-size in Device Conrol Register xiong
2012-04-13 17:02 ` Ben Hutchings
2012-04-14 10:39 ` Huang, Xiong
2012-04-13 0:14 ` [PATCH 13/37] atl1c: threshold for ASPM is changed based on chip capability xiong
2012-04-13 0:14 ` [PATCH 14/37] atl1c: add module parameter for l1c_wait_until_idle xiong
2012-04-13 0:14 ` [PATCH 15/37] atl1c: update right threshold for TSO xiong
2012-04-13 0:14 ` [PATCH 16/37] atl1c: remove dmar_dly_cnt and dmaw_dly_cnt xiong
2012-04-13 0:14 ` [PATCH 17/37] atl1c: clear PCIE error status in atl1c_reset_pcie xiong
2012-04-13 0:14 ` [PATCH 18/37] atl1c: refine reg definition of REG_MASTER_CTRL xiong
2012-04-13 0:14 ` [PATCH 19/37] atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch xiong
2012-04-13 0:14 ` [PATCH 20/37] atl1c: refine/update ASPM configuration xiong
2012-04-13 0:14 ` [PATCH 21/37] atl1c: refine atl1c_pcie_patch xiong
2012-04-13 0:14 ` [PATCH 22/37] atl1c: fix WoL(magic) issue for l2cb 1.1 xiong
2012-04-13 0:14 ` [PATCH 23/37] atl1c: remove MDIO_REG_ADDR_MASK in atl1c_mdio_read/write xiong
2012-04-13 0:14 ` [PATCH 24/37] atl1c: remove REG_PHY_STATUS xiong
2012-04-13 0:14 ` [PATCH 25/37] atl1c: refine phy-register read/write function xiong
2012-04-13 0:14 ` [PATCH 26/37] atl1c: remove PHY contrl in atl1c_reset_pcie xiong
2012-04-13 0:14 ` xiong [this message]
2012-04-13 0:14 ` [PATCH 28/37] atl1c: remove PHY polling from atl1c_open xiong
2012-04-13 0:14 ` [PATCH 29/37] atl1c: update PHY reset related routine xiong
2012-04-13 0:14 ` [PATCH 30/37] atl1c: remove PHY reset/init for link down event xiong
2012-04-13 0:14 ` [PATCH 31/37] atl1c: add function atl1c_power_saving xiong
2012-04-13 0:14 ` [PATCH 32/37] atl1c: refine start/enable code for MAC module xiong
2012-04-13 0:14 ` [PATCH 33/37] atl1c: add PHY link event(up/down) patch xiong
2012-04-13 0:14 ` [PATCH 34/37] atl1c: clear WoL status when reset pcie xiong
2012-04-13 0:15 ` [PATCH 35/37] atl1c: remove code of closing register writable attribution xiong
2012-04-13 0:15 ` [PATCH 36/37] atl1c: refine mac address related code xiong
2012-04-13 0:15 ` [PATCH 37/37] atl1c: cancel task when interface closed xiong
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