From: James Clark <james.clark@linaro.org>
To: Leo Yan <leo.yan@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Tamas Petz <tamas.petz@arm.com>,
Tamas Zsoldos <tamas.zsoldos@arm.com>,
Suyash Mahar <smahar@meta.com>, Amir Ayupov <aaupov@fb.com>
Subject: Re: [PATCH v2 11/23] coresight: trbe: Assign the perf handle in enable and disable
Date: Tue, 10 Nov 2026 15:31:54 +0000 [thread overview]
Message-ID: <1b528cd9-eac0-43b3-8166-db9f78c9f044@linaro.org> (raw)
In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-11-3f57cf3199b1@arm.com>
On 16/10/2026 17:55, Leo Yan wrote:
> etm-perf owns the perf output handle embedded in its per-CPU etm_ctxt and
> passes it to TRBE through arm_trbe_enable(). TRBE binds that handle after
> successful sink enable and unbinds it in arm_trbe_disable(). The handle
> object remains valid throughout this interval, even if the current AUX
> transaction ends or a new transaction begins.
>
> The inner enable helper currently publishes the handle, while truncation
> and failed rollover clear it. Sink disable leaves the handle installed
> after dropping the buffer association. These assignments track the AUX
> transaction rather than the enabled sink session.
>
> Publish the handle only in arm_trbe_enable() after successful setup and
> clear it in arm_trbe_disable() before dropping the buffer association.
> Remove the assignments from the inner enable, overflow and truncation
> paths so the handle association follows the enabled sink session.
>
> A valid handle object may have no active AUX transaction, so the IRQ
> handler continues to check perf_get_aux() before accessing the
> transaction's configuration.
>
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-trbe.c | 20 +++++++-------------
> 1 file changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 4a041bbc6e970d72a7d735e15f7221037cb091d6..1f51c33de83638479436683fd96e31d69c3b860f 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -303,11 +303,8 @@ static void trbe_report_wrap_event(struct perf_output_handle *handle)
>
> static void trbe_truncate_event(struct perf_output_handle *handle)
> {
> - struct trbe_buf *buf = etm_perf_sink_config(handle);
> -
> perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> perf_aux_output_end(handle, 0);
> - *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> }
>
> /*
> @@ -1012,7 +1009,6 @@ static int __arm_trbe_enable(struct trbe_buf *buf,
> if (ret)
> goto err;
>
> - *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
> trbe_enable_hw(buf);
> return 0;
> err:
> @@ -1042,6 +1038,7 @@ static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode,
> return ret;
> }
>
> + *this_cpu_ptr(drvdata->handle) = handle;
> cpudata->buf = buf;
> cpudata->mode = mode;
> return 0;
> @@ -1062,6 +1059,7 @@ static int arm_trbe_disable(struct coresight_device *csdev)
> trbe_drain_and_disable_local(cpudata);
> clr_trbe_status();
>
> + *this_cpu_ptr(drvdata->handle) = NULL;
> buf->cpudata = NULL;
> cpudata->buf = NULL;
> cpudata->mode = CS_MODE_DISABLED;
> @@ -1102,16 +1100,12 @@ static int trbe_handle_overflow(struct perf_output_handle *handle)
> trbe_report_wrap_event(handle);
> perf_aux_output_end(handle, size);
> event_data = perf_aux_output_begin(handle, event);
> - if (!event_data) {
> - /*
> - * We are unable to restart the trace collection,
> - * thus leave the TRBE disabled. The etm-perf driver
> - * is able to detect this with a disconnected handle
> - * (handle->event = NULL).
> - */
> - *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> + /*
> + * If trace collection cannot be restarted, leave TRBE disabled.
> + * The etm-perf driver detects this through handle->event == NULL.
> + */
> + if (!event_data)
> return -EINVAL;
> - }
>
> return __arm_trbe_enable(buf, handle);
> }
>
Reviewed-by: James Clark <james.clark@linaro.org>
next prev parent reply other threads:[~2026-11-10 15:31 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 16:54 [PATCH v2 00/23] coresight: trbe: Refactor buffer and IRQ handling Leo Yan
2026-10-16 16:54 ` [PATCH v2 01/23] arm64/sysreg: Define TRBSR_EL1.EC event classes Leo Yan
2026-11-10 15:28 ` James Clark
2026-10-16 16:55 ` [PATCH v2 02/23] coresight: trbe: Make watermark range check overflow safe in __trbe_normal_offset() Leo Yan
2026-11-10 15:28 ` James Clark
2026-10-16 16:55 ` [PATCH v2 03/23] coresight: trbe: Use helpers for checking errata Leo Yan
2026-11-10 15:29 ` James Clark
2026-10-16 16:55 ` [PATCH v2 04/23] coresight: trbe: Check the buffer association before IRQ validation Leo Yan
2026-11-10 15:29 ` James Clark
2026-10-16 16:55 ` [PATCH v2 05/23] coresight: trbe: Validate perf handle before using sink data Leo Yan
2026-11-10 15:29 ` James Clark
2026-10-16 16:55 ` [PATCH v2 06/23] coresight: trbe: Drop redundant disable from enable path Leo Yan
2026-11-09 16:27 ` James Clark
2026-10-16 16:55 ` [PATCH v2 07/23] coresight: trbe: Publish the session after successful enable Leo Yan
2026-11-10 15:30 ` James Clark
2026-10-16 16:55 ` [PATCH v2 08/23] coresight: trbe: Clear stale external abort status Leo Yan
2026-11-10 15:30 ` James Clark
2026-10-16 16:55 ` [PATCH v2 09/23] coresight: trbe: Clear TRBSR status at stop sites Leo Yan
2026-11-09 16:40 ` James Clark
2026-11-09 16:51 ` James Clark
2026-11-09 22:51 ` Suzuki K Poulose
2026-11-10 8:48 ` Leo Yan
2026-11-10 15:25 ` Suzuki K Poulose
2026-10-16 16:55 ` [PATCH v2 10/23] coresight: trbe: Drop redundant disables Leo Yan
2026-11-10 15:31 ` James Clark
2026-10-16 16:55 ` [PATCH v2 11/23] coresight: trbe: Assign the perf handle in enable and disable Leo Yan
2026-11-10 15:31 ` James Clark [this message]
2026-10-16 16:55 ` [PATCH v2 12/23] coresight: trbe: Decode TRBSR status codes Leo Yan
2026-11-10 15:32 ` James Clark
2026-10-16 16:55 ` [PATCH v2 13/23] coresight: trbe: Simplify wrap status handling Leo Yan
2026-11-10 15:32 ` James Clark
2026-10-16 16:55 ` [PATCH v2 14/23] coresight: trbe: Treat access not allowed stops as fatal Leo Yan
2026-11-10 15:33 ` James Clark
2026-10-16 16:55 ` [PATCH v2 15/23] coresight: trbe: Report truncated trace on buffer update errors Leo Yan
2026-11-10 15:33 ` James Clark
2026-10-16 16:55 ` [PATCH v2 16/23] coresight: trbe: Always classify TRBSR when updating buffer Leo Yan
2026-11-10 15:34 ` James Clark
2026-10-16 16:55 ` [PATCH v2 17/23] coresight: trbe: Calculate trace size across buffer wrap Leo Yan
2026-11-10 15:34 ` James Clark
2026-10-16 16:55 ` [PATCH v2 18/23] coresight: trbe: Keep the perf handle in per-CPU data Leo Yan
2026-11-10 15:34 ` James Clark
2026-10-16 16:55 ` [PATCH v2 19/23] coresight: trbe: Reload the AUX buffer on overflow restart Leo Yan
2026-11-10 15:12 ` James Clark
2026-10-16 16:55 ` [PATCH v2 20/23] coresight: trbe: Add fault action argument to trbe_handle_overflow() Leo Yan
2026-11-10 15:34 ` James Clark
2026-10-16 16:55 ` [PATCH v2 21/23] coresight: trbe: Read TRBSR after prohibiting and flushing trace Leo Yan
2026-11-10 15:24 ` James Clark
2026-10-16 16:55 ` [PATCH v2 22/23] coresight: trbe: Restart trace source for stopped buffers Leo Yan
2026-11-10 15:35 ` James Clark
2026-10-16 16:55 ` [PATCH v2 23/23] coresight: trbe: Report trace gaps with PARTIAL instead of COLLISION Leo Yan
2026-11-10 15:35 ` James Clark
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