From: James Clark <james.clark@linaro.org>
To: Leo Yan <leo.yan@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Tamas Petz <tamas.petz@arm.com>,
Tamas Zsoldos <tamas.zsoldos@arm.com>,
Suyash Mahar <smahar@meta.com>, Amir Ayupov <aaupov@fb.com>
Subject: Re: [PATCH v2 18/23] coresight: trbe: Keep the perf handle in per-CPU data
Date: Tue, 10 Nov 2026 15:34:33 +0000 [thread overview]
Message-ID: <38e4f4dc-e2ea-4b7f-82d1-e7b298e88002@linaro.org> (raw)
In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-18-3f57cf3199b1@arm.com>
On 16/10/2026 17:55, Leo Yan wrote:
> Arm SPE owns a per-CPU perf output handle for the PMU lifetime. TRBE
> instead receives a handle from CoreSight when enabling its sink.
>
> Store that session handle in trbe_cpudata instead of a separate per-CPU
> pointer array, and pass the CPU data as the per-CPU IRQ context. Use this
> context directly for overflow and spurious interrupt handling so local
> hardware control does not depend on the current AUX buffer configuration.
>
> Allocate the CPU data before registering the IRQ and free it after
> releasing the IRQ, keeping the IRQ context valid throughout registration.
>
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-trbe.c | 44 ++++++++++++----------------
> 1 file changed, 19 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 9a469c8009ce8a8a8b804c2b63a68e741f1dceaa..2328aab0a084a0ac123e950f846f404d120ec2c0 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -139,6 +139,7 @@ struct trbe_save_state {
> * @cpu - CPU this TRBE belongs to.
> * @mode - Mode of current operation. (perf/disabled)
> * @buf - Buffer configuration retained for the enabled session.
> + * @handle - Perf output handle from successful enable until disable.
> * @drvdata - TRBE specific drvdata
> * @errata - Bit map for the errata on this TRBE.
> */
> @@ -149,6 +150,7 @@ struct trbe_cpudata {
> int cpu;
> enum cs_mode mode;
> struct trbe_buf *buf;
> + struct perf_output_handle *handle;
> struct trbe_drvdata *drvdata;
> struct trbe_save_state save_state;
> DECLARE_BITMAP(errata, TRBE_ERRATA_MAX);
> @@ -156,7 +158,6 @@ struct trbe_cpudata {
>
> struct trbe_drvdata {
> struct trbe_cpudata __percpu *cpudata;
> - struct perf_output_handle * __percpu *handle;
> struct hlist_node hotplug_node;
> int irq;
> cpumask_t supported_cpus;
> @@ -1091,7 +1092,7 @@ static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode,
> return ret;
> }
>
> - *this_cpu_ptr(drvdata->handle) = handle;
> + cpudata->handle = handle;
> cpudata->buf = buf;
> cpudata->mode = mode;
> return 0;
> @@ -1112,16 +1113,15 @@ static int arm_trbe_disable(struct coresight_device *csdev)
> trbe_drain_and_disable_local(cpudata);
> clr_trbe_status();
>
> - *this_cpu_ptr(drvdata->handle) = NULL;
> buf->cpudata = NULL;
> + cpudata->handle = NULL;
> cpudata->buf = NULL;
> cpudata->mode = CS_MODE_DISABLED;
> return 0;
> }
>
> -static void trbe_handle_spurious(struct perf_output_handle *handle)
> +static void trbe_handle_spurious(struct trbe_cpudata *cpudata)
> {
> - struct trbe_buf *buf = etm_perf_sink_config(handle);
> u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
>
> /*
> @@ -1129,11 +1129,12 @@ static void trbe_handle_spurious(struct perf_output_handle *handle)
> * back without modifying the buffer parameters to
> * retain the trace collected so far.
> */
> - set_trbe_enabled(buf->cpudata, trblimitr);
> + set_trbe_enabled(cpudata, trblimitr);
> }
>
> -static int trbe_handle_overflow(struct perf_output_handle *handle)
> +static int trbe_handle_overflow(struct trbe_cpudata *cpudata)
> {
> + struct perf_output_handle *handle = cpudata->handle;
> struct perf_event *event = handle->event;
> struct trbe_buf *buf = etm_perf_sink_config(handle);
> unsigned long size;
> @@ -1203,9 +1204,8 @@ static u64 cpu_prohibit_trace(void)
>
> static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
> {
> - struct perf_output_handle **handle_ptr = dev;
> - struct perf_output_handle *handle = *handle_ptr;
> - struct trbe_buf *buf;
> + struct trbe_cpudata *cpudata = dev;
> + struct perf_output_handle *handle = cpudata->handle;
> enum trbe_fault_action act;
> u64 status;
> bool truncated = false;
> @@ -1232,18 +1232,17 @@ static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
> * Ensure the trace is visible to the CPUs and
> * any external aborts have been resolved.
> */
> - buf = etm_perf_sink_config(handle);
> - trbe_drain_and_disable_local(buf->cpudata);
> + trbe_drain_and_disable_local(cpudata);
> clr_trbe_irq();
> isb();
>
> act = trbe_get_fault_act(handle, status);
> switch (act) {
> case TRBE_FAULT_ACT_WRAP:
> - truncated = !!trbe_handle_overflow(handle);
> + truncated = !!trbe_handle_overflow(cpudata);
> break;
> case TRBE_FAULT_ACT_SPURIOUS:
> - trbe_handle_spurious(handle);
> + trbe_handle_spurious(cpudata);
> break;
> case TRBE_FAULT_ACT_FATAL:
> trbe_truncate_event(handle);
> @@ -1507,10 +1506,6 @@ static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
> {
> int cpu;
>
> - drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> - if (!drvdata->cpudata)
> - return -ENOMEM;
> -
> for_each_cpu(cpu, &drvdata->supported_cpus) {
> /* If we fail to probe the CPU, let us defer it to hotplug callbacks */
> if (smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1))
> @@ -1531,7 +1526,6 @@ static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
> smp_call_function_single(cpu, arm_trbe_disable_cpu, drvdata, 1);
> arm_trbe_remove_coresight_cpu(drvdata, cpu);
> }
> - free_percpu(drvdata->cpudata);
> return 0;
> }
>
> @@ -1618,14 +1612,14 @@ static int arm_trbe_probe_irq(struct platform_device *pdev,
>
> cpumask_copy(&drvdata->supported_cpus, affinity);
>
> - drvdata->handle = alloc_percpu(struct perf_output_handle *);
> - if (!drvdata->handle)
> + drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> + if (!drvdata->cpudata)
> return -ENOMEM;
>
> ret = request_percpu_irq_affinity(drvdata->irq, arm_trbe_irq_handler, DRVNAME,
> - affinity, drvdata->handle);
> + affinity, drvdata->cpudata);
> if (ret) {
> - free_percpu(drvdata->handle);
> + free_percpu(drvdata->cpudata);
> return ret;
> }
> return 0;
> @@ -1633,8 +1627,8 @@ static int arm_trbe_probe_irq(struct platform_device *pdev,
>
> static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
> {
> - free_percpu_irq(drvdata->irq, drvdata->handle);
> - free_percpu(drvdata->handle);
> + free_percpu_irq(drvdata->irq, drvdata->cpudata);
> + free_percpu(drvdata->cpudata);
> }
>
> static int arm_trbe_device_probe(struct platform_device *pdev)
>
Reviewed-by: James Clark <james.clark@linaro.org>
next prev parent reply other threads:[~2026-11-10 15:34 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 16:54 [PATCH v2 00/23] coresight: trbe: Refactor buffer and IRQ handling Leo Yan
2026-10-16 16:54 ` [PATCH v2 01/23] arm64/sysreg: Define TRBSR_EL1.EC event classes Leo Yan
2026-11-10 15:28 ` James Clark
2026-10-16 16:55 ` [PATCH v2 02/23] coresight: trbe: Make watermark range check overflow safe in __trbe_normal_offset() Leo Yan
2026-11-10 15:28 ` James Clark
2026-10-16 16:55 ` [PATCH v2 03/23] coresight: trbe: Use helpers for checking errata Leo Yan
2026-11-10 15:29 ` James Clark
2026-10-16 16:55 ` [PATCH v2 04/23] coresight: trbe: Check the buffer association before IRQ validation Leo Yan
2026-11-10 15:29 ` James Clark
2026-10-16 16:55 ` [PATCH v2 05/23] coresight: trbe: Validate perf handle before using sink data Leo Yan
2026-11-10 15:29 ` James Clark
2026-10-16 16:55 ` [PATCH v2 06/23] coresight: trbe: Drop redundant disable from enable path Leo Yan
2026-11-09 16:27 ` James Clark
2026-10-16 16:55 ` [PATCH v2 07/23] coresight: trbe: Publish the session after successful enable Leo Yan
2026-11-10 15:30 ` James Clark
2026-10-16 16:55 ` [PATCH v2 08/23] coresight: trbe: Clear stale external abort status Leo Yan
2026-11-10 15:30 ` James Clark
2026-10-16 16:55 ` [PATCH v2 09/23] coresight: trbe: Clear TRBSR status at stop sites Leo Yan
2026-11-09 16:40 ` James Clark
2026-11-09 16:51 ` James Clark
2026-11-09 22:51 ` Suzuki K Poulose
2026-11-10 8:48 ` Leo Yan
2026-11-10 15:25 ` Suzuki K Poulose
2026-10-16 16:55 ` [PATCH v2 10/23] coresight: trbe: Drop redundant disables Leo Yan
2026-11-10 15:31 ` James Clark
2026-10-16 16:55 ` [PATCH v2 11/23] coresight: trbe: Assign the perf handle in enable and disable Leo Yan
2026-11-10 15:31 ` James Clark
2026-10-16 16:55 ` [PATCH v2 12/23] coresight: trbe: Decode TRBSR status codes Leo Yan
2026-11-10 15:32 ` James Clark
2026-10-16 16:55 ` [PATCH v2 13/23] coresight: trbe: Simplify wrap status handling Leo Yan
2026-11-10 15:32 ` James Clark
2026-10-16 16:55 ` [PATCH v2 14/23] coresight: trbe: Treat access not allowed stops as fatal Leo Yan
2026-11-10 15:33 ` James Clark
2026-10-16 16:55 ` [PATCH v2 15/23] coresight: trbe: Report truncated trace on buffer update errors Leo Yan
2026-11-10 15:33 ` James Clark
2026-10-16 16:55 ` [PATCH v2 16/23] coresight: trbe: Always classify TRBSR when updating buffer Leo Yan
2026-11-10 15:34 ` James Clark
2026-10-16 16:55 ` [PATCH v2 17/23] coresight: trbe: Calculate trace size across buffer wrap Leo Yan
2026-11-10 15:34 ` James Clark
2026-10-16 16:55 ` [PATCH v2 18/23] coresight: trbe: Keep the perf handle in per-CPU data Leo Yan
2026-11-10 15:34 ` James Clark [this message]
2026-10-16 16:55 ` [PATCH v2 19/23] coresight: trbe: Reload the AUX buffer on overflow restart Leo Yan
2026-11-10 15:12 ` James Clark
2026-10-16 16:55 ` [PATCH v2 20/23] coresight: trbe: Add fault action argument to trbe_handle_overflow() Leo Yan
2026-11-10 15:34 ` James Clark
2026-10-16 16:55 ` [PATCH v2 21/23] coresight: trbe: Read TRBSR after prohibiting and flushing trace Leo Yan
2026-11-10 15:24 ` James Clark
2026-10-16 16:55 ` [PATCH v2 22/23] coresight: trbe: Restart trace source for stopped buffers Leo Yan
2026-11-10 15:35 ` James Clark
2026-10-16 16:55 ` [PATCH v2 23/23] coresight: trbe: Report trace gaps with PARTIAL instead of COLLISION Leo Yan
2026-11-10 15:35 ` James Clark
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