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From: James Clark <james.clark@linaro.org>
To: Leo Yan <leo.yan@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Tamas Petz <tamas.petz@arm.com>,
	Tamas Zsoldos <tamas.zsoldos@arm.com>,
	Suyash Mahar <smahar@meta.com>, Amir Ayupov <aaupov@fb.com>
Subject: Re: [PATCH v2 07/23] coresight: trbe: Publish the session after successful enable
Date: Tue, 10 Nov 2026 15:30:12 +0000	[thread overview]
Message-ID: <6a607357-f613-4a9e-8d38-96ff4f02eec8@linaro.org> (raw)
In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-7-3f57cf3199b1@arm.com>



On 16/10/2026 17:55, Leo Yan wrote:
> arm_trbe_enable() records the session buffer and perf mode before
> __arm_trbe_enable() can fail. CoreSight skips the sink disable callback
> when sink enable fails, leaving that session state published even though
> tracing did not start.
> 
> Install buf->cpudata temporarily for the buffer setup helpers, then call
> __arm_trbe_enable() before assigning cpudata->buf and cpudata->mode.
> Clear the temporary buffer association if setup fails; the inner helper
> still truncates and ends the AUX transaction.
> 
> After successful enable, retain the buffer association across AUX
> transactions and clear it in arm_trbe_disable().
> 
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
>   drivers/hwtracing/coresight/coresight-trbe.c | 15 ++++++++++++---
>   1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 979d0fa84c1c7b448c1ce5cd7a37dff8845795ef..9dfc6bb7afb4c42dfdec643ee7e4f2f193e2b70c 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -69,6 +69,7 @@ struct trbe_buf {
>   	int nr_pages;
>   	void **pages;
>   	bool snapshot;
> +	/* CPU used to configure this buffer. */
>   	struct trbe_cpudata *cpudata;
>   };
>   
> @@ -137,6 +138,7 @@ struct trbe_save_state {
>    * @trbe_align		- Software alignment used for the TRBPTR_EL1.
>    * @cpu			- CPU this TRBE belongs to.
>    * @mode		- Mode of current operation. (perf/disabled)
> + * @buf			- Buffer configuration retained for the enabled session.
>    * @drvdata		- TRBE specific drvdata
>    * @errata		- Bit map for the errata on this TRBE.
>    */
> @@ -1033,17 +1035,24 @@ static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode,
>   	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>   	struct perf_output_handle *handle = path->handle;
>   	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	int ret;
>   
>   	WARN_ON(cpudata->cpu != smp_processor_id());
>   	WARN_ON(cpudata->drvdata != drvdata);
>   	if (mode != CS_MODE_PERF)
>   		return -EINVAL;
>   
> -	cpudata->buf = buf;
> -	cpudata->mode = mode;
> +	/* Buffer helpers need the CPU association while setting up tracing. */
>   	buf->cpudata = cpudata;
> +	ret = __arm_trbe_enable(buf, handle);
> +	if (ret) {
> +		buf->cpudata = NULL;
> +		return ret;
> +	}
>   
> -	return __arm_trbe_enable(buf, handle);
> +	cpudata->buf = buf;
> +	cpudata->mode = mode;
> +	return 0;
>   }
>   
>   static int arm_trbe_disable(struct coresight_device *csdev)
> 
Reviewed-by: James Clark <james.clark@linaro.org>

  reply	other threads:[~2026-11-10 15:30 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-16 16:54 [PATCH v2 00/23] coresight: trbe: Refactor buffer and IRQ handling Leo Yan
2026-10-16 16:54 ` [PATCH v2 01/23] arm64/sysreg: Define TRBSR_EL1.EC event classes Leo Yan
2026-11-10 15:28   ` James Clark
2026-10-16 16:55 ` [PATCH v2 02/23] coresight: trbe: Make watermark range check overflow safe in __trbe_normal_offset() Leo Yan
2026-11-10 15:28   ` James Clark
2026-10-16 16:55 ` [PATCH v2 03/23] coresight: trbe: Use helpers for checking errata Leo Yan
2026-11-10 15:29   ` James Clark
2026-10-16 16:55 ` [PATCH v2 04/23] coresight: trbe: Check the buffer association before IRQ validation Leo Yan
2026-11-10 15:29   ` James Clark
2026-10-16 16:55 ` [PATCH v2 05/23] coresight: trbe: Validate perf handle before using sink data Leo Yan
2026-11-10 15:29   ` James Clark
2026-10-16 16:55 ` [PATCH v2 06/23] coresight: trbe: Drop redundant disable from enable path Leo Yan
2026-11-09 16:27   ` James Clark
2026-10-16 16:55 ` [PATCH v2 07/23] coresight: trbe: Publish the session after successful enable Leo Yan
2026-11-10 15:30   ` James Clark [this message]
2026-10-16 16:55 ` [PATCH v2 08/23] coresight: trbe: Clear stale external abort status Leo Yan
2026-11-10 15:30   ` James Clark
2026-10-16 16:55 ` [PATCH v2 09/23] coresight: trbe: Clear TRBSR status at stop sites Leo Yan
2026-11-09 16:40   ` James Clark
2026-11-09 16:51     ` James Clark
2026-11-09 22:51   ` Suzuki K Poulose
2026-11-10  8:48     ` Leo Yan
2026-11-10 15:25       ` Suzuki K Poulose
2026-10-16 16:55 ` [PATCH v2 10/23] coresight: trbe: Drop redundant disables Leo Yan
2026-11-10 15:31   ` James Clark
2026-10-16 16:55 ` [PATCH v2 11/23] coresight: trbe: Assign the perf handle in enable and disable Leo Yan
2026-11-10 15:31   ` James Clark
2026-10-16 16:55 ` [PATCH v2 12/23] coresight: trbe: Decode TRBSR status codes Leo Yan
2026-11-10 15:32   ` James Clark
2026-10-16 16:55 ` [PATCH v2 13/23] coresight: trbe: Simplify wrap status handling Leo Yan
2026-11-10 15:32   ` James Clark
2026-10-16 16:55 ` [PATCH v2 14/23] coresight: trbe: Treat access not allowed stops as fatal Leo Yan
2026-11-10 15:33   ` James Clark
2026-10-16 16:55 ` [PATCH v2 15/23] coresight: trbe: Report truncated trace on buffer update errors Leo Yan
2026-11-10 15:33   ` James Clark
2026-10-16 16:55 ` [PATCH v2 16/23] coresight: trbe: Always classify TRBSR when updating buffer Leo Yan
2026-11-10 15:34   ` James Clark
2026-10-16 16:55 ` [PATCH v2 17/23] coresight: trbe: Calculate trace size across buffer wrap Leo Yan
2026-11-10 15:34   ` James Clark
2026-10-16 16:55 ` [PATCH v2 18/23] coresight: trbe: Keep the perf handle in per-CPU data Leo Yan
2026-11-10 15:34   ` James Clark
2026-10-16 16:55 ` [PATCH v2 19/23] coresight: trbe: Reload the AUX buffer on overflow restart Leo Yan
2026-11-10 15:12   ` James Clark
2026-10-16 16:55 ` [PATCH v2 20/23] coresight: trbe: Add fault action argument to trbe_handle_overflow() Leo Yan
2026-11-10 15:34   ` James Clark
2026-10-16 16:55 ` [PATCH v2 21/23] coresight: trbe: Read TRBSR after prohibiting and flushing trace Leo Yan
2026-11-10 15:24   ` James Clark
2026-10-16 16:55 ` [PATCH v2 22/23] coresight: trbe: Restart trace source for stopped buffers Leo Yan
2026-11-10 15:35   ` James Clark
2026-10-16 16:55 ` [PATCH v2 23/23] coresight: trbe: Report trace gaps with PARTIAL instead of COLLISION Leo Yan
2026-11-10 15:35   ` James Clark

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