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From: James Clark <james.clark@linaro.org>
To: Leo Yan <leo.yan@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Tamas Petz <tamas.petz@arm.com>,
	Tamas Zsoldos <tamas.zsoldos@arm.com>,
	Suyash Mahar <smahar@meta.com>, Amir Ayupov <aaupov@fb.com>
Subject: Re: [PATCH v2 17/23] coresight: trbe: Calculate trace size across buffer wrap
Date: Tue, 10 Nov 2026 15:34:19 +0000	[thread overview]
Message-ID: <617d1821-ddbf-42fb-bb02-75aaacda21eb@linaro.org> (raw)
In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-17-3f57cf3199b1@arm.com>



On 16/10/2026 17:55, Leo Yan wrote:
> trbe_get_trace_size() assumes that the TRBE write pointer is always ahead
> of the perf AUX head. That is not true after a WRAP event, where the write
> pointer can move back to the start of the programmed TRBE span.
> 
> Calculate the size in two parts for WRAP: the bytes from the current AUX
> head to TRBLIMITR_EL1, plus any bytes from TRBBASER_EL1 to the current
> TRBPTR_EL1. Keep the non-WRAP path strict and reject an unexpected write
> pointer below the AUX head.
> 
> For CPUs affected by the overwrite-fill-mode or write-out-of-range errata,
> continue to ignore TRBPTR_EL1 on WRAP and account data only up to
> TRBLIMITR_EL1, since bytes beyond the programmed limit are uncertain.
> 
> Apply this fallback before validating the write pointer so a WRAP report
> with a pointer outside the programmed range still publishes the trace
> from the AUX head to the programmed limit.
> 
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
>   drivers/hwtracing/coresight/coresight-trbe.c | 62 +++++++++++++++++-----------
>   1 file changed, 37 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 661f4a78e67c30652de8c834e4773819fa67b5ac..9a469c8009ce8a8a8b804c2b63a68e741f1dceaa 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -730,43 +730,55 @@ static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *hand
>   static unsigned long trbe_get_trace_size(struct perf_output_handle *handle,
>   					 struct trbe_buf *buf, bool wrap)
>   {
> -	u64 write;
> -	u64 start_off, end_off;
> -	u64 size;
>   	u64 overwrite_skip = TRBE_WORKAROUND_OVERWRITE_FILL_MODE_SKIP_BYTES;
> +	u64 base = buf->trbe_base;
> +	u64 start_off = PERF_IDX2OFF(handle->head, buf);
> +	u64 write = get_trbe_write_pointer();
> +	u64 limit = get_trbe_limit_pointer();
> +	u64 limit_off, write_off, size;
>   
>   	/*
> -	 * If the TRBE has wrapped around the write pointer has
> -	 * wrapped and should be treated as limit.
> -	 *
>   	 * When the TRBE is affected by TRBE_WORKAROUND_WRITE_OUT_OF_RANGE,
> -	 * it may write upto 64bytes beyond the "LIMIT". The driver already
> +	 * it may write up to 64bytes beyond the "LIMIT". The driver already
>   	 * keeps a valid page next to the LIMIT and we could potentially
>   	 * consume the trace data that may have been collected there. But we
>   	 * cannot be really sure it is available, and the TRBPTR may not
> -	 * indicate the same. Also, affected cores are also affected by another
> -	 * erratum which forces the PAGE_SIZE alignment on the TRBPTR, and thus
> -	 * could potentially pad an entire PAGE_SIZE - 64bytes, to get those
> -	 * 64bytes. Thus we ignore the potential triggering of the erratum
> -	 * on WRAP and limit the data to LIMIT.
> +	 * indicate the same.
> +	 *
> +	 * Also, affected cores are also affected by another erratum
> +	 * TRBE_WORKAROUND_OVERWRITE_FILL_MODE, which forces the PAGE_SIZE
> +	 * alignment on the TRBPTR, and thus could potentially pad an entire
> +	 * PAGE_SIZE - 64bytes, to get those 64bytes. Thus we ignore the
> +	 * potential effects of the erratum on WRAP and limit the data to
> +	 * LIMIT.
>   	 */
> -	if (wrap)
> -		write = get_trbe_limit_pointer();
> -	else
> -		write = get_trbe_write_pointer();
> +	if (wrap &&
> +	    (trbe_may_overwrite_in_fill_mode(buf->cpudata) ||
> +	     trbe_may_write_out_of_range(buf->cpudata)))
> +		write = limit;
>   
> -	/*
> -	 * TRBE may use a different base address than the base
> -	 * of the ring buffer. Thus use the beginning of the ring
> -	 * buffer to compute the offsets.
> -	 */
> -	end_off = write - buf->trbe_base;
> -	start_off = PERF_IDX2OFF(handle->head, buf);
> +	/* Should never happen ... */
> +	if (WARN_ON_ONCE(write < base || write > limit))
> +		return 0;
>   
> -	if (WARN_ON_ONCE(end_off < start_off))
> +	limit_off = limit - base;
> +	write_off = write - base;
> +
> +	if (WARN_ON_ONCE(start_off >= limit_off))
>   		return 0;
>   
> -	size = end_off - start_off;
> +	if (!wrap) {
> +		if (WARN_ON_ONCE(write_off < start_off))
> +			return 0;
> +
> +		size = write_off - start_off;
> +	} else {
> +		size = limit_off - start_off;
> +
> +		if (write != limit)
> +			size += write_off;
> +	}
> +
>   	/*
>   	 * If the TRBE is affected by the following erratum, we must fill
>   	 * the space we skipped with IGNORE packets. And we are always
> 
Reviewed-by: James Clark <james.clark@linaro.org>

  reply	other threads:[~2026-11-10 15:34 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-16 16:54 [PATCH v2 00/23] coresight: trbe: Refactor buffer and IRQ handling Leo Yan
2026-10-16 16:54 ` [PATCH v2 01/23] arm64/sysreg: Define TRBSR_EL1.EC event classes Leo Yan
2026-11-10 15:28   ` James Clark
2026-10-16 16:55 ` [PATCH v2 02/23] coresight: trbe: Make watermark range check overflow safe in __trbe_normal_offset() Leo Yan
2026-11-10 15:28   ` James Clark
2026-10-16 16:55 ` [PATCH v2 03/23] coresight: trbe: Use helpers for checking errata Leo Yan
2026-11-10 15:29   ` James Clark
2026-10-16 16:55 ` [PATCH v2 04/23] coresight: trbe: Check the buffer association before IRQ validation Leo Yan
2026-11-10 15:29   ` James Clark
2026-10-16 16:55 ` [PATCH v2 05/23] coresight: trbe: Validate perf handle before using sink data Leo Yan
2026-11-10 15:29   ` James Clark
2026-10-16 16:55 ` [PATCH v2 06/23] coresight: trbe: Drop redundant disable from enable path Leo Yan
2026-11-09 16:27   ` James Clark
2026-10-16 16:55 ` [PATCH v2 07/23] coresight: trbe: Publish the session after successful enable Leo Yan
2026-11-10 15:30   ` James Clark
2026-10-16 16:55 ` [PATCH v2 08/23] coresight: trbe: Clear stale external abort status Leo Yan
2026-11-10 15:30   ` James Clark
2026-10-16 16:55 ` [PATCH v2 09/23] coresight: trbe: Clear TRBSR status at stop sites Leo Yan
2026-11-09 16:40   ` James Clark
2026-11-09 16:51     ` James Clark
2026-11-09 22:51   ` Suzuki K Poulose
2026-11-10  8:48     ` Leo Yan
2026-11-10 15:25       ` Suzuki K Poulose
2026-10-16 16:55 ` [PATCH v2 10/23] coresight: trbe: Drop redundant disables Leo Yan
2026-11-10 15:31   ` James Clark
2026-10-16 16:55 ` [PATCH v2 11/23] coresight: trbe: Assign the perf handle in enable and disable Leo Yan
2026-11-10 15:31   ` James Clark
2026-10-16 16:55 ` [PATCH v2 12/23] coresight: trbe: Decode TRBSR status codes Leo Yan
2026-11-10 15:32   ` James Clark
2026-10-16 16:55 ` [PATCH v2 13/23] coresight: trbe: Simplify wrap status handling Leo Yan
2026-11-10 15:32   ` James Clark
2026-10-16 16:55 ` [PATCH v2 14/23] coresight: trbe: Treat access not allowed stops as fatal Leo Yan
2026-11-10 15:33   ` James Clark
2026-10-16 16:55 ` [PATCH v2 15/23] coresight: trbe: Report truncated trace on buffer update errors Leo Yan
2026-11-10 15:33   ` James Clark
2026-10-16 16:55 ` [PATCH v2 16/23] coresight: trbe: Always classify TRBSR when updating buffer Leo Yan
2026-11-10 15:34   ` James Clark
2026-10-16 16:55 ` [PATCH v2 17/23] coresight: trbe: Calculate trace size across buffer wrap Leo Yan
2026-11-10 15:34   ` James Clark [this message]
2026-10-16 16:55 ` [PATCH v2 18/23] coresight: trbe: Keep the perf handle in per-CPU data Leo Yan
2026-11-10 15:34   ` James Clark
2026-10-16 16:55 ` [PATCH v2 19/23] coresight: trbe: Reload the AUX buffer on overflow restart Leo Yan
2026-11-10 15:12   ` James Clark
2026-10-16 16:55 ` [PATCH v2 20/23] coresight: trbe: Add fault action argument to trbe_handle_overflow() Leo Yan
2026-11-10 15:34   ` James Clark
2026-10-16 16:55 ` [PATCH v2 21/23] coresight: trbe: Read TRBSR after prohibiting and flushing trace Leo Yan
2026-11-10 15:24   ` James Clark
2026-10-16 16:55 ` [PATCH v2 22/23] coresight: trbe: Restart trace source for stopped buffers Leo Yan
2026-11-10 15:35   ` James Clark
2026-10-16 16:55 ` [PATCH v2 23/23] coresight: trbe: Report trace gaps with PARTIAL instead of COLLISION Leo Yan
2026-11-10 15:35   ` James Clark

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