[PATCH 0/8] powerpc/perf: mpc7450: Event fixes, SIAR sampling and sysfs event names

[PATCH 0/8] powerpc/perf: mpc7450: Event fixes, SIAR sampling and sysfs event names

[Matt Turner]

Patches 1-3 fix the MPC7450 perf driver's event tables against the
manual (MPC7450UM Rev. 5, chapter 11).  The worst is patch 3: an
alternatives row joins three different events, so perf can report the
count of a different event.  In one test it was 374 times the real
count.

Patch 4 fills in the L1 data cache events, patch 5 adds the PMC6 copies
of five L3 events to the alternatives table, and patch 6 adds a format/
directory.

Patch 7 takes sample addresses from SIAR on 32-bit.  When a counter
overflows with interrupts disabled, the interrupted PC is where they
are re-enabled; SIAR is not.

Patch 8 names the events in sysfs.

Tested on an iMac G4 (MPC7448).  The 7448 has no L3, so patch 5 and the
L3 half of patch 8 are untested.

Signed-off-by: Matt Turner <mattst88@gmail.com>
---
Matt Turner (8):
      powerpc/perf: mpc7450: Event 0x30d does not use the threshold
      powerpc/perf: mpc7450: Event 0x634 counts L2 prefetches, not L1I
      powerpc/perf: mpc7450: Remove the snoop retry alternatives
      powerpc/perf: mpc7450: Fill in the L1 data cache events
      powerpc/perf: mpc7450: Add the PMC6 L3 events to the alternatives table
      powerpc/perf: mpc7450: Export the event format in sysfs
      powerpc/perf: Use SIAR for sample addresses on 32-bit
      powerpc/perf: mpc7450: Export event names in sysfs

 arch/powerpc/perf/core-book3s.c         |  55 ++++---
 arch/powerpc/perf/mpc7450-events-list.h | 250 ++++++++++++++++++++++++++++++++
 arch/powerpc/perf/mpc7450-pmu.c         | 118 +++++++++++++--
 3 files changed, 388 insertions(+), 35 deletions(-)
---
base-commit: d68ce4e71248e1ff5af9654b407541d9260b3ba5
change-id: 20261106-ppc32-perf-bfa132a142db

Best regards,
--  
Matt Turner <mattst88@gmail.com>

[PATCH 1/8] powerpc/perf: mpc7450: Event 0x30d does not use the threshold

[Matt Turner]

mpc7450_threshold_use() reports event 0x30d (PMC3 select 13, FPR issue
queue entries) as using MMCR0[THRESHOLD], and the comment above it marks
the event with a question mark.  The manual (MPC7450UM Rev. 5, Table
11-11) says the event counts the valid FPR issue queue entries each
cycle, with no threshold.  PMC3 select 12, the GPR rename buffer event
next to it, is the one that uses the threshold.

The only effect is that r30d cannot be counted together with a threshold
event that uses a different threshold.  Drop it from the list.

Fixes: 7325927e5a20 ("perf_counter: powerpc: Add processor back-end for MPC7450 family")
Signed-off-by: Matt Turner <mattst88@gmail.com>
---
 arch/powerpc/perf/mpc7450-pmu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index db451b9aac35..564f6dac3a00 100644
--- a/arch/powerpc/perf/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
@@ -65,7 +65,6 @@ static int mpc7450_classify_event(u32 event)
  *	12b	Y	PM_LD_MISS_EXCEED_L1_CYC
  *	220	N	PM_CQ_EXCEED_CYC
  *	30c	N	PM_GPR_RB_EXCEED_CYC
- *	30d	?	PM_FPR_IQ_EXCEED_CYC ?
  *	311	Y	PM_ITLB_SEARCH_EXCEED
  *	410	N	PM_GPR_IQ_EXCEED_CYC
  */
@@ -92,7 +91,7 @@ static int mpc7450_threshold_use(u32 event)
 			return 1;
 		break;
 	case 3:
-		if (sel == 0xc || sel == 0xd)
+		if (sel == 0xc)
 			return 1;
 		if (sel == 0x11)
 			return 2;

-- 
2.55.0

[PATCH 2/8] powerpc/perf: mpc7450: Event 0x634 counts L2 prefetches, not L1I

[Matt Turner]

The cache event table maps L1-icache-prefetches to 0x634, PMC6 select
52.  The manual (MPC7450UM Rev. 5, Table 11-14) calls that event
"Prefetch engine request" and says it "counts new prefetches allocated
in the prefetch unit".  It is the first of six events about the L2
prefetch engine (selects 52-57), and the MPC7450 has no instruction
cache prefetch event.

On a 7448, a pointer chase over 64-byte nodes counts r634 at 0.00 per
load when the working set fits in the 1 MB L2, and at 1.00 per load,
one per L2 demand miss, at 4 MB.

The engine starts a prefetch only when an access misses in every cache,
fetches from the bus, and also fills the L3 if there is one (section
3.6.3.2), so it is a last-level prefetch with or without an L3.  Report
it as LL-prefetches, and L1-icache-prefetches as not supported.

Fixes: 7325927e5a20 ("perf_counter: powerpc: Add processor back-end for MPC7450 family")
Signed-off-by: Matt Turner <mattst88@gmail.com>
---
 arch/powerpc/perf/mpc7450-pmu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index 564f6dac3a00..5a882d934645 100644
--- a/arch/powerpc/perf/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
@@ -370,12 +370,12 @@ static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
 		[C(OP_READ)] = {	0x129,		0x115	},
 		[C(OP_WRITE)] = {	-1,		-1	},
-		[C(OP_PREFETCH)] = {	0x634,		0	},
+		[C(OP_PREFETCH)] = {	0,		0	},
 	},
 	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
 		[C(OP_READ)] = {	0,		0	},
 		[C(OP_WRITE)] = {	0,		0	},
-		[C(OP_PREFETCH)] = {	0,		0	},
+		[C(OP_PREFETCH)] = {	0x634,		0	},
 	},
 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
 		[C(OP_READ)] = {	0,		0x312	},

-- 
2.55.0

[PATCH 3/8] powerpc/perf: mpc7450: Remove the snoop retry alternatives

[Matt Turner]

The alternatives table treats 0x418, 0x50f and 0x60f as one event, but
the manual (MPC7450UM Rev. 5, Tables 11-12 to 11-14) describes three
different events that share the name "snoop retries":

  0x418  load/store snoops retried by the load/store unit
  0x50f  internal requests that are internally retried
  0x60f  snoop responses of "retry" to any access

On a 7448, over the same workload, counting r418, r50f and r60f
together, and then r418 in a group with r41c:

  r418                 1793
  r50f              1546267
  r60f              2266850
  r418 in {r41c,r418}  670562

r418 and r41c both need PMC4, so in the group the scheduler moves r418
to PMC5 or PMC6, which count other events, and reports 374 times the
real count.  Remove the row.

Fixes: 7325927e5a20 ("perf_counter: powerpc: Add processor back-end for MPC7450 family")
Signed-off-by: Matt Turner <mattst88@gmail.com>
---
 arch/powerpc/perf/mpc7450-pmu.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index 5a882d934645..9890c87c58ef 100644
--- a/arch/powerpc/perf/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
@@ -184,7 +184,6 @@ static int mpc7450_get_constraint(u64 event, unsigned long *maskp,
 
 static const unsigned int event_alternatives[][MAX_ALT] = {
 	{ 0x217, 0x317 },		/* PM_L1_DCACHE_MISS */
-	{ 0x418, 0x50f, 0x60f },	/* PM_SNOOP_RETRY */
 	{ 0x502, 0x602 },		/* PM_L2_HIT */
 	{ 0x503, 0x603 },		/* PM_L3_HIT */
 	{ 0x504, 0x604 },		/* PM_L2_ICACHE_MISS */

-- 
2.55.0

[PATCH 4/8] powerpc/perf: mpc7450: Fill in the L1 data cache events

[Matt Turner]

The L1D row of the cache event table has load and store misses but no
accesses, and nothing for prefetches, so L1-dcache-loads,
L1-dcache-stores and L1-dcache-prefetch-misses are not supported.

The MPC7450 has no L1 data cache access event, so approximate the
accesses with PMC2 select 26 (load instructions completed) and select
20 (store instructions completed, PMC1 or PMC2).  These also count
cache-inhibited accesses.  PMC2 select 38 counts dcbt, dcbtst and dst
line fetches that miss in the L1 data cache.

On a 7448, a loop with one store in every 32 instructions counted
645840841 instructions and 19773839 L1-dcache-stores, about one store
per 33 instructions.

Loads and load misses are both PMC2-only events, so perf multiplexes
L1-dcache-loads and L1-dcache-load-misses when both are requested, and
refuses them in one group.

Signed-off-by: Matt Turner <mattst88@gmail.com>
---
 arch/powerpc/perf/mpc7450-pmu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index 9890c87c58ef..27337a03ebde 100644
--- a/arch/powerpc/perf/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
@@ -362,9 +362,9 @@ static int mpc7450_generic_events[] = {
  */
 static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
-		[C(OP_READ)] = {	0,		0x225	},
-		[C(OP_WRITE)] = {	0,		0x227	},
-		[C(OP_PREFETCH)] = {	0,		0	},
+		[C(OP_READ)] = {	0x21a,		0x225	},
+		[C(OP_WRITE)] = {	0x014,		0x227	},
+		[C(OP_PREFETCH)] = {	0,		0x226	},
 	},
 	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
 		[C(OP_READ)] = {	0x129,		0x115	},

-- 
2.55.0

[PATCH 5/8] powerpc/perf: mpc7450: Add the PMC6 L3 events to the alternatives table

[Matt Turner]

PMC6 repeats five L3 events at a second select value that the
alternatives table doesn't list:

  0x61f  L3 hits, also 0x503 and 0x603
  0x620  L3 misses, also 0x514 and 0x61e
  0x621  L3 instruction misses, also 0x505 and 0x605
  0x622  L3 data misses, also 0x507 and 0x607
  0x625  L3 touch hits, also 0x50e and 0x60e

Each is the same event as the PMC5 code, so add them to its row.  The
scheduler can then move them to PMC5 when PMC6 is taken.

Not tested on hardware with an L3; the 7448 has none.

Signed-off-by: Matt Turner <mattst88@gmail.com>
---
 arch/powerpc/perf/mpc7450-pmu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index 27337a03ebde..b2fe977cea16 100644
--- a/arch/powerpc/perf/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
@@ -185,18 +185,18 @@ static int mpc7450_get_constraint(u64 event, unsigned long *maskp,
 static const unsigned int event_alternatives[][MAX_ALT] = {
 	{ 0x217, 0x317 },		/* PM_L1_DCACHE_MISS */
 	{ 0x502, 0x602 },		/* PM_L2_HIT */
-	{ 0x503, 0x603 },		/* PM_L3_HIT */
+	{ 0x503, 0x603, 0x61f },	/* PM_L3_HIT */
 	{ 0x504, 0x604 },		/* PM_L2_ICACHE_MISS */
-	{ 0x505, 0x605 },		/* PM_L3_ICACHE_MISS */
+	{ 0x505, 0x605, 0x621 },	/* PM_L3_ICACHE_MISS */
 	{ 0x506, 0x606 },		/* PM_L2_DCACHE_MISS */
-	{ 0x507, 0x607 },		/* PM_L3_DCACHE_MISS */
+	{ 0x507, 0x607, 0x622 },	/* PM_L3_DCACHE_MISS */
 	{ 0x50a, 0x623 },		/* PM_LD_HIT_L3 */
 	{ 0x50b, 0x624 },		/* PM_ST_HIT_L3 */
 	{ 0x50d, 0x60d },		/* PM_L2_TOUCH_HIT */
-	{ 0x50e, 0x60e },		/* PM_L3_TOUCH_HIT */
+	{ 0x50e, 0x60e, 0x625 },	/* PM_L3_TOUCH_HIT */
 	{ 0x512, 0x612 },		/* PM_INT_LOCAL */
 	{ 0x513, 0x61d },		/* PM_L2_MISS */
-	{ 0x514, 0x61e },		/* PM_L3_MISS */
+	{ 0x514, 0x61e, 0x620 },	/* PM_L3_MISS */
 };
 
 /*

-- 
2.55.0

[PATCH 6/8] powerpc/perf: mpc7450: Export the event format in sysfs

[Matt Turner]

The MPC7450 PMU has no format/ directory, so perf can take its events
only as raw codes, and cannot set the threshold by name.

Describe the fields of the event code: the PMC select (bits 0-6), the
PMC (bits 8-10), the threshold (bits 12-17) and the threshold multiplier
(bit 18).  A threshold event can then be written as, e.g.,
cpu/event=0x12b,thresh=20/.

Signed-off-by: Matt Turner <mattst88@gmail.com>
---
 arch/powerpc/perf/mpc7450-pmu.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index b2fe977cea16..9bed5c238f45 100644
--- a/arch/powerpc/perf/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
@@ -398,6 +398,31 @@ static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 	},
 };
 
+PMU_FORMAT_ATTR(event,		"config:0-18");
+PMU_FORMAT_ATTR(pmcsel,		"config:0-6");
+PMU_FORMAT_ATTR(pmc,		"config:8-10");
+PMU_FORMAT_ATTR(thresh,		"config:12-17");
+PMU_FORMAT_ATTR(thresh_mult,	"config:18");
+
+static struct attribute *mpc7450_pmu_format_attr[] = {
+	&format_attr_event.attr,
+	&format_attr_pmcsel.attr,
+	&format_attr_pmc.attr,
+	&format_attr_thresh.attr,
+	&format_attr_thresh_mult.attr,
+	NULL,
+};
+
+static const struct attribute_group mpc7450_pmu_format_group = {
+	.name = "format",
+	.attrs = mpc7450_pmu_format_attr,
+};
+
+static const struct attribute_group *mpc7450_pmu_attr_groups[] = {
+	&mpc7450_pmu_format_group,
+	NULL,
+};
+
 struct power_pmu mpc7450_pmu = {
 	.name			= "MPC7450 family",
 	.n_counter		= N_COUNTER,
@@ -411,6 +436,7 @@ struct power_pmu mpc7450_pmu = {
 	.n_generic		= ARRAY_SIZE(mpc7450_generic_events),
 	.generic_events		= mpc7450_generic_events,
 	.cache_events		= &mpc7450_cache_events,
+	.attr_groups		= mpc7450_pmu_attr_groups,
 };
 
 static int __init init_mpc7450_pmu(void)

-- 
2.55.0

[PATCH 7/8] powerpc/perf: Use SIAR for sample addresses on 32-bit

[Matt Turner]

On 32-bit, perf_read_regs() sets regs->result to 0, so regs_use_siar()
is always false and every sample is attributed to the interrupted PC.

The MPC7450 family's SIAR holds the address of the last instruction to
complete before the performance monitor exception is generated
(MPC7450UM Rev. 5, section 11.3.7).  The exception can be generated
with MSR[EE] = 0 and is taken once EE is set again (section 11.2), so
when interrupts are disabled the interrupted PC is wherever they are
re-enabled, while SIAR still points into the disabled region.

On a 7448, sampling cycles system-wide with --intr-regs=nip during dd,
perf bench sched pipe and find, 46% of the kernel samples have SIAR and
the interrupted PC in different functions.  13270 samples have their PC
on the instruction after the mtmsr that restores interrupts in
ata_scsi_queuecmd(), and 11661 of those have SIAR in udelay().

With interrupts enabled SIAR helps less.  Sampling a 32-instruction
loop with one store and one branch with -c 10007, 99.8% of the samples
land at:

  event             interrupted PC   SIAR
  r122 (branches)   br + 13          br + 9
  r014 (stores)     stw + 21         stw + 17

siar_valid() already returns true on 32-bit.  Use SIAR for PMU
exceptions, and take the user/kernel flags from it too.  Move
regs_use_siar() above the 32-bit block so that perf_get_misc_flags()
can call it.

Signed-off-by: Matt Turner <mattst88@gmail.com>
---
 arch/powerpc/perf/core-book3s.c | 55 +++++++++++++++++++++++++++--------------
 1 file changed, 36 insertions(+), 19 deletions(-)

diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 10ded865583c..e4c8ecddccbd 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -75,6 +75,20 @@ static struct power_pmu *ppmu;
  */
 static unsigned int freeze_events_kernel = MMCR0_FCS;
 
+static bool regs_use_siar(struct pt_regs *regs)
+{
+	/*
+	 * When we take a performance monitor exception the regs are setup
+	 * using perf_read_regs() which overloads some fields, in particular
+	 * regs->result to tell us whether to use SIAR.
+	 *
+	 * However if the regs are from another exception, eg. a syscall, then
+	 * they have not been setup using perf_read_regs() and so regs->result
+	 * is something random.
+	 */
+	return ((TRAP(regs) == INTERRUPT_PERFMON) && regs->result);
+}
+
 /*
  * 32-bit doesn't have MMCRA but does have an MMCR2,
  * and a few other names are different.
@@ -108,13 +122,30 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
 	return 0;
 }
 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { }
-static inline u32 perf_get_misc_flags(struct pt_regs *regs)
-{
-	return 0;
-}
+
+/*
+ * The MPC7450 family's SIAR holds the address of the last instruction to
+ * complete before the performance monitor exception was generated, so for
+ * a PMU exception it is closer to the event than the interrupted PC.
+ */
 static inline void perf_read_regs(struct pt_regs *regs)
 {
-	regs->result = 0;
+	regs->result = 1;
+}
+
+static inline u32 perf_get_misc_flags(struct pt_regs *regs)
+{
+	unsigned long siar;
+
+	if (!regs_use_siar(regs))
+		return 0;
+
+	siar = mfspr(SPRN_SIAR);
+	if (!siar)
+		return 0;
+
+	return is_kernel_addr(siar) ? PERF_RECORD_MISC_KERNEL :
+				      PERF_RECORD_MISC_USER;
 }
 
 static inline int siar_valid(struct pt_regs *regs)
@@ -163,20 +194,6 @@ unsigned long get_pmcs_ext_regs(int idx)
 	return cpuhw->pmcs[idx];
 }
 
-static bool regs_use_siar(struct pt_regs *regs)
-{
-	/*
-	 * When we take a performance monitor exception the regs are setup
-	 * using perf_read_regs() which overloads some fields, in particular
-	 * regs->result to tell us whether to use SIAR.
-	 *
-	 * However if the regs are from another exception, eg. a syscall, then
-	 * they have not been setup using perf_read_regs() and so regs->result
-	 * is something random.
-	 */
-	return ((TRAP(regs) == INTERRUPT_PERFMON) && regs->result);
-}
-
 /*
  * Things that are specific to 64-bit implementations.
  */

-- 
2.55.0

[PATCH 8/8] powerpc/perf: mpc7450: Export event names in sysfs

[Matt Turner]

perf list shows only the generic events for the MPC7450 family, so every
other event has to be written as a raw code.

Name the events in the manual (MPC7450UM Rev. 5, Tables 11-9 to 11-14)
in mpc7450-events-list.h, as the POWER7 driver does.  An event that
several PMCs implement at the same select value is listed once without
a PMC, so the driver still picks the counter.  An event repeated at
different select values is listed once and reached through the
alternatives table, whose comments now use the same names.  223 names
cover all 279 non-reserved select values.

The 7441, 7445, 7447, 7447A and 7448 have no L3, and their L3 events
are reserved.  Hide the L3 names when CPU_FTR_L3CR is clear, which is
on the 7447A and 7448.  The 7441, 7445 and 7447 share their PVRs with
the 7451, 7455 and 7457 and get CPU_FTR_L3CR, so they keep them.

Signed-off-by: Matt Turner <mattst88@gmail.com>
---
 arch/powerpc/perf/mpc7450-events-list.h | 250 ++++++++++++++++++++++++++++++++
 arch/powerpc/perf/mpc7450-pmu.c         |  68 ++++++++-
 2 files changed, 315 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/perf/mpc7450-events-list.h b/arch/powerpc/perf/mpc7450-events-list.h
new file mode 100644
index 000000000000..b79f2fc675bf
--- /dev/null
+++ b/arch/powerpc/perf/mpc7450-events-list.h
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Performance counter events for MPC7450-family processors, from the
+ * MPC7450 RISC Microprocessor Family Reference Manual, Rev. 5, tables 11-9
+ * to 11-14.
+ *
+ * Codes below 0x100 are the events that several PMCs implement with the
+ * same select value; the driver picks the counter.  Events that exist on
+ * more than one PMC under different select values are listed once, and
+ * the others are found through the alternatives table.
+ *
+ * EVENT_L3() events count only on parts with an L3 cache interface.
+ */
+
+/* Events available on several PMCs */
+EVENT(PM_CYC,				0x001)
+EVENT(PM_INST_CMPL,			0x002)
+EVENT(PM_TBL_BIT_TRANS,			0x003)
+EVENT(PM_INST_DISP,			0x004)
+EVENT(PM_PMEXC,				0x005)
+EVENT(PM_PMON_IN,			0x007)
+EVENT(PM_VPU_CMPL,			0x008)
+EVENT(PM_VFPU_CMPL,			0x009)
+EVENT(PM_VIU1_CMPL,			0x00a)
+EVENT(PM_VIU2_CMPL,			0x00b)
+EVENT(PM_MTVSCR_CMPL,			0x00c)
+EVENT(PM_MTVRSAVE_CMPL,			0x00d)
+EVENT(PM_VPU_OPND_WAIT_CYC,		0x00e)
+EVENT(PM_VFPU_OPND_WAIT_CYC,		0x00f)
+EVENT(PM_VIU1_OPND_WAIT_CYC,		0x010)
+EVENT(PM_VIU2_OPND_WAIT_CYC,		0x011)
+EVENT(PM_MFVSCR_SYNC_CYC,		0x012)
+EVENT(PM_VSCR_SAT_SET,			0x013)
+EVENT(PM_ST_CMPL,			0x014)
+EVENT(PM_L1_ICACHE_MISS,		0x015)
+EVENT(PM_L1_DCACHE_SNOOP,		0x016)
+
+/* PMC1 */
+EVENT(PM_BR_UNRESOLVED,			0x117)
+EVENT(PM_BR_SPEC_BUF1_CYC,		0x118)
+EVENT(PM_BR_UNIT_STALL_CYC,		0x119)
+EVENT(PM_BR_TARGET_HIT,			0x11a)
+EVENT(PM_BR_LINK_STACK_PRED,		0x11b)
+EVENT(PM_GPR_IQ_DISP,			0x11c)
+EVENT(PM_DISP_3_CYC,			0x11d)
+EVENT(PM_INSTQ_EXCEED_CYC,		0x11e)
+EVENT(PM_ALTV_IQ_EXCEED_CYC,		0x11f)
+EVENT(PM_NO_CMPL_CYC,			0x120)
+EVENT(PM_IU2_CMPL,			0x121)
+EVENT(PM_BR_CMPL,			0x122)
+EVENT(PM_EIEIO_CMPL,			0x123)
+EVENT(PM_MTSPR_CMPL,			0x124)
+EVENT(PM_SC_CMPL,			0x125)
+EVENT(PM_LD_STR_MULT_CMPL,		0x126)
+EVENT(PM_ITLB_SEARCH_CYC,		0x127)
+EVENT(PM_DTLB_SEARCH_EXCEED_CYC,	0x128)
+EVENT(PM_L1_ICACHE_ACCESS,		0x129)
+EVENT(PM_IABR_MATCH,			0x12a)
+EVENT(PM_LD_MISS_EXCEED_L1_CYC,		0x12b)
+EVENT(PM_L1_DCACHE_SNOOP_HIT_MOD,	0x12c)
+EVENT(PM_LD_MISS_ALIAS,			0x12d)
+EVENT(PM_LD_MISS_ALIAS_TOUCH,		0x12e)
+EVENT(PM_TOUCH_ALIAS,			0x12f)
+EVENT(PM_L1_DCACHE_SNOOP_HIT_COQ,	0x130)
+EVENT(PM_L1_DCACHE_SNOOP_HIT_CO,	0x131)
+EVENT(PM_L1_DCACHE_SNOOP_HIT,		0x132)
+EVENT(PM_WT_ST,				0x133)
+EVENT(PM_CI_ST,				0x134)
+EVENT(PM_L1_DCACHE_LD_HIT,		0x135)
+EVENT(PM_L1_DCACHE_TOUCH_HIT,		0x136)
+EVENT(PM_L1_DCACHE_ST_HIT,		0x137)
+EVENT(PM_L1_DCACHE_HIT,			0x138)
+EVENT(PM_DST_DISP,			0x139)
+EVENT(PM_DST_REFRESH,			0x13a)
+EVENT(PM_DST_SEARCH,			0x13b)
+EVENT(PM_DSS_CMPL,			0x13c)
+EVENT(PM_DST0_FETCH,			0x13d)
+EVENT(PM_VTQ_SUSPEND,			0x13e)
+EVENT(PM_VTQ_FETCH_HIT,			0x13f)
+EVENT(PM_VEC_LD_CMPL,			0x140)
+EVENT(PM_FP_ST_CMPL,			0x141)
+EVENT(PM_FP_ST_RENORM,			0x142)
+EVENT(PM_FP_ST_DENORM,			0x143)
+EVENT(PM_FP_ST_STALL_CYC,		0x144)
+EVENT(PM_LSU_TRUE_ALIAS_STALL,		0x146)
+EVENT(PM_LSU_INDEX_ALIAS_STALL,		0x147)
+EVENT(PM_LSU_ALIAS_FSQ,			0x148)
+EVENT(PM_LSU_ALIAS_CSQ,			0x149)
+EVENT(PM_LSU_LD_HIT_ALIAS_CSQ0,		0x14a)
+EVENT(PM_LSU_LD_MISS_ALIAS_CSQ0,	0x14b)
+EVENT(PM_LSU_TOUCH_ALIAS_FSQ,		0x14c)
+EVENT(PM_LSU_TOUCH_ALIAS_CSQ,		0x14d)
+EVENT(PM_LSU_LMQ_FULL_STALL,		0x14e)
+EVENT(PM_FP_LD_CMPL,			0x14f)
+EVENT(PM_FP_LD_SINGLE_CMPL,		0x150)
+EVENT(PM_FP_LD_DOUBLE_CMPL,		0x151)
+EVENT(PM_LSU_RA_LATCH_STALL,		0x152)
+EVENT(PM_LSU_LD_ST_ALIAS_STALL,		0x153)
+EVENT(PM_LSU_LMQ_INDEX_ALIAS,		0x154)
+EVENT(PM_LSU_STQ_INDEX_ALIAS,		0x155)
+EVENT(PM_LSU_CSQ_FWD,			0x156)
+EVENT(PM_LSU_MISALIGN_LD_FIN,		0x157)
+EVENT(PM_LSU_MISALIGN_ST_CMPL,		0x158)
+EVENT(PM_LSU_MISALIGN_STALL,		0x159)
+EVENT(PM_FPSCR_RENAME_QTR_BUSY,		0x15a)
+EVENT(PM_FPSCR_RENAME_HALF_BUSY,	0x15b)
+EVENT(PM_FPSCR_RENAME_3QTR_BUSY,	0x15c)
+EVENT(PM_FPSCR_RENAME_FULL,		0x15d)
+EVENT(PM_FP_DENORM_RESULT,		0x15e)
+
+/* PMC2 */
+EVENT(PM_L1_DCACHE_MISS,		0x217)
+EVENT(PM_FPR_IQ_DISP,			0x218)
+EVENT(PM_LSU_CMPL,			0x219)
+EVENT(PM_LD_CMPL,			0x21a)
+EVENT(PM_ST_STR_MULT_CMPL,		0x21b)
+EVENT(PM_TLBIE_CMPL,			0x21c)
+EVENT(PM_LWARX_CMPL,			0x21d)
+EVENT(PM_MFSPR_CMPL,			0x21e)
+EVENT(PM_REFETCH_SERIAL,		0x21f)
+EVENT(PM_CQ_EXCEED_CYC,			0x220)
+EVENT(PM_CMPL_1_CYC,			0x221)
+EVENT(PM_DISP_2_CYC,			0x222)
+EVENT(PM_ITLB_MISS,			0x223)
+EVENT(PM_L1_ICACHE_MISS_CYC,		0x224)
+EVENT(PM_L1_DCACHE_LD_MISS,		0x225)
+EVENT(PM_L1_DCACHE_TOUCH_MISS,		0x226)
+EVENT(PM_L1_DCACHE_ST_MISS,		0x227)
+EVENT(PM_L1_DCACHE_TOUCH_MISS_CYC,	0x228)
+EVENT(PM_L1_DCACHE_BUSY_CYC,		0x229)
+EVENT(PM_DST1_FETCH,			0x22a)
+EVENT(PM_VTQ_CANCEL,			0x22b)
+EVENT(PM_VTQ_RESUME,			0x22c)
+EVENT(PM_VTQ_FETCH_MISS,		0x22d)
+EVENT(PM_VTQ_FETCH,			0x22e)
+EVENT(PM_TLBIE_SNOOP,			0x22f)
+EVENT(PM_L1_ICACHE_RELOAD,		0x230)
+EVENT(PM_L1_DCACHE_RELOAD,		0x231)
+EVENT(PM_L1_DCACHE_CASTOUT,		0x232)
+EVENT(PM_ST_MERGE,			0x233)
+EVENT(PM_ST_MERGE_32B,			0x234)
+EVENT(PM_DABR_MATCH,			0x235)
+EVENT(PM_BR_FALLTHRU,			0x236)
+EVENT(PM_BR_SPEC_BUF1_OK,		0x237)
+EVENT(PM_BR_SPEC_BUF2_CYC,		0x238)
+EVENT(PM_BR_LR_STALL_CYC,		0x239)
+EVENT(PM_BTIC_MISS,			0x23a)
+EVENT(PM_BR_LINK_STACK_OK,		0x23b)
+EVENT(PM_FPR_IQ_STALL,			0x23c)
+EVENT(PM_PR_SWITCH,			0x23d)
+EVENT(PM_FP_ST_SINGLE_CMPL,		0x23e)
+
+/* PMC3 */
+EVENT(PM_CMPL_2_CYC,			0x308)
+EVENT(PM_DISP_1_CYC,			0x309)
+EVENT(PM_VR_IQ_DISP,			0x30a)
+EVENT(PM_VR_IQ_STALL,			0x30b)
+EVENT(PM_GPR_RB_EXCEED_CYC,		0x30c)
+EVENT(PM_FPR_IQ_ENTRIES,		0x30d)
+EVENT(PM_FPU_CMPL,			0x30e)
+EVENT(PM_STWCX_CMPL,			0x30f)
+EVENT(PM_LD_STR_MULT_PIECES,		0x310)
+EVENT(PM_ITLB_SEARCH_EXCEED,		0x311)
+EVENT(PM_DTLB_MISS,			0x312)
+EVENT(PM_L1_ICACHE_MISS_CANCEL,		0x313)
+EVENT(PM_L1_DCACHE_OP_HIT,		0x314)
+EVENT(PM_L1_DCACHE_LD_MISS_CYC,		0x315)
+EVENT(PM_L1_DCACHE_PUSH,		0x316)
+EVENT(PM_VT2_FETCH,			0x318)
+EVENT(PM_BR_TAKEN,			0x319)
+EVENT(PM_BR_FLUSH,			0x31a)
+EVENT(PM_BR_SPEC_BUF2_OK,		0x31b)
+EVENT(PM_BR_SPEC_BUF3_CYC,		0x31c)
+EVENT(PM_BR_CTR_STALL_CYC,		0x31d)
+EVENT(PM_FBTIC_HIT,			0x31e)
+EVENT(PM_BR_LINK_STACK_MPRED,		0x31f)
+
+/* PMC4 */
+EVENT(PM_CMPL_3_CYC,			0x40e)
+EVENT(PM_DISP_0_CYC,			0x40f)
+EVENT(PM_GPR_IQ_EXCEED_CYC,		0x410)
+EVENT(PM_GPR_IQ_STALL_CYC,		0x411)
+EVENT(PM_IU1_CMPL,			0x412)
+EVENT(PM_DSSALL_CMPL,			0x413)
+EVENT(PM_TLBSYNC_CMPL,			0x414)
+EVENT(PM_SYNC_CMPL,			0x415)
+EVENT(PM_ST_STR_MULT_PIECES,		0x416)
+EVENT(PM_DTLB_SEARCH_CYC,		0x417)
+EVENT(PM_LSU_SNOOP_RETRY,		0x418)
+EVENT(PM_STWCX_OK,			0x419)
+EVENT(PM_DST3_FETCH,			0x41a)
+EVENT(PM_BR_SPEC_BUF3_OK,		0x41b)
+EVENT(PM_BR_MPRED,			0x41c)
+EVENT(PM_BR_FOLDED,			0x41d)
+EVENT(PM_FP_ST_DOUBLE_CMPL,		0x41e)
+
+/* PMC5 */
+EVENT(PM_L2_HIT,			0x502)
+EVENT_L3(PM_L3_HIT,			0x503)
+EVENT(PM_L2_ICACHE_MISS,		0x504)
+EVENT_L3(PM_L3_ICACHE_MISS,		0x505)
+EVENT(PM_L2_DCACHE_MISS,		0x506)
+EVENT_L3(PM_L3_DCACHE_MISS,		0x507)
+EVENT(PM_L2_LD_HIT,			0x508)
+EVENT(PM_L2_ST_HIT,			0x509)
+EVENT_L3(PM_L3_LD_HIT,			0x50a)
+EVENT_L3(PM_L3_ST_HIT,			0x50b)
+EVENT(PM_L2_TOUCH_HIT,			0x50d)
+EVENT_L3(PM_L3_TOUCH_HIT,		0x50e)
+EVENT(PM_INT_RETRY,			0x50f)
+EVENT(PM_SNOOP_MOD,			0x510)
+EVENT(PM_SNOOP_VALID,			0x511)
+EVENT(PM_INTV_LOCAL,			0x512)
+EVENT(PM_L2_MISS,			0x513)
+EVENT_L3(PM_L3_MISS,			0x514)
+
+/* PMC6 */
+EVENT(PM_L2_CASTOUT,			0x608)
+EVENT_L3(PM_L3_CASTOUT,			0x609)
+EVENT(PM_L2SQ_FULL_CYC,			0x60a)
+EVENT_L3(PM_L3SQ_FULL_CYC,		0x60b)
+EVENT(PM_SNOOP_RETRY,			0x60f)
+EVENT_L3(PM_L3_RAQ_FULL_CYC,		0x610)
+EVENT_L3(PM_L3_WAQ_FULL_CYC,		0x611)
+EVENT(PM_L1_EXT_INTV,			0x613)
+EVENT(PM_L2_EXT_INTV,			0x614)
+EVENT_L3(PM_L3_EXT_INTV,		0x615)
+EVENT(PM_EXT_INTV,			0x616)
+EVENT(PM_EXT_PUSH,			0x617)
+EVENT(PM_EXT_SNOOP_RETRY,		0x618)
+EVENT(PM_DTQ_FULL_CYC,			0x619)
+EVENT(PM_BUS_RETRY,			0x61a)
+EVENT(PM_L2_VALID_REQ,			0x61b)
+EVENT(PM_BORDQ_FULL_CYC,		0x61c)
+EVENT(PM_BUS_TA_RD,			0x62a)
+EVENT(PM_BUS_TA_WR,			0x62b)
+EVENT(PM_BUS_RD_OK,			0x62c)
+EVENT(PM_BUS_WR_OK,			0x62d)
+EVENT(PM_BUS_RDWR_OK,			0x62e)
+EVENT(PM_BUS_RETRY_L1,			0x62f)
+EVENT(PM_BUS_RETRY_ADJ,			0x630)
+EVENT(PM_BUS_RETRY_COLLISION,		0x631)
+EVENT(PM_BUS_RETRY_INTV_ORDER,		0x632)
+EVENT(PM_SNOOP_REQ,			0x633)
+EVENT(PM_L2_PREF,			0x634)
+EVENT(PM_L2_PREF_LD_COLLISION,		0x635)
+EVENT(PM_L2_PREF_ST_COLLISION,		0x636)
+EVENT(PM_L2_PREF_IFETCH_COLLISION,	0x637)
+EVENT(PM_L2_PREF_LMQ_COLLISION,		0x638)
+EVENT(PM_L2_PREF_FULL,			0x639)
diff --git a/arch/powerpc/perf/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index 9bed5c238f45..4ee7b1a822ea 100644
--- a/arch/powerpc/perf/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
@@ -22,6 +22,18 @@
 #define PM_PMC_MSK	7
 #define PM_PMCSEL_MSK	0x7f
 
+/*
+ * MPC7450 event codes.
+ */
+#define EVENT(_name, _code)	_name = _code,
+#define EVENT_L3(_name, _code)	_name = _code,
+
+enum {
+#include "mpc7450-events-list.h"
+};
+#undef EVENT
+#undef EVENT_L3
+
 /*
  * Classify events according to how specific their PMC requirements are.
  * Result is:
@@ -190,11 +202,11 @@ static const unsigned int event_alternatives[][MAX_ALT] = {
 	{ 0x505, 0x605, 0x621 },	/* PM_L3_ICACHE_MISS */
 	{ 0x506, 0x606 },		/* PM_L2_DCACHE_MISS */
 	{ 0x507, 0x607, 0x622 },	/* PM_L3_DCACHE_MISS */
-	{ 0x50a, 0x623 },		/* PM_LD_HIT_L3 */
-	{ 0x50b, 0x624 },		/* PM_ST_HIT_L3 */
+	{ 0x50a, 0x623 },		/* PM_L3_LD_HIT */
+	{ 0x50b, 0x624 },		/* PM_L3_ST_HIT */
 	{ 0x50d, 0x60d },		/* PM_L2_TOUCH_HIT */
 	{ 0x50e, 0x60e, 0x625 },	/* PM_L3_TOUCH_HIT */
-	{ 0x512, 0x612 },		/* PM_INT_LOCAL */
+	{ 0x512, 0x612 },		/* PM_INTV_LOCAL */
 	{ 0x513, 0x61d },		/* PM_L2_MISS */
 	{ 0x514, 0x61e, 0x620 },	/* PM_L3_MISS */
 };
@@ -398,6 +410,55 @@ static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 	},
 };
 
+#define EVENT(_name, _code)	POWER_EVENT_ATTR(_name, _name);
+#define EVENT_L3(_name, _code)	POWER_EVENT_ATTR(_name, _name);
+#include "mpc7450-events-list.h"
+#undef EVENT
+#undef EVENT_L3
+
+#define EVENT(_name, _code)	POWER_EVENT_PTR(_name),
+#define EVENT_L3(_name, _code)	POWER_EVENT_PTR(_name),
+
+static struct attribute *mpc7450_events_attr[] = {
+#include "mpc7450-events-list.h"
+	NULL
+};
+
+#undef EVENT
+#undef EVENT_L3
+
+static bool mpc7450_is_l3_event(u64 event)
+{
+	switch (event) {
+#define EVENT(_name, _code)
+#define EVENT_L3(_name, _code)	case _code:
+#include "mpc7450-events-list.h"
+#undef EVENT
+#undef EVENT_L3
+		return true;
+	}
+	return false;
+}
+
+/* The L3 events are reserved on parts without an L3 interface. */
+static umode_t mpc7450_events_is_visible(struct kobject *kobj,
+					 struct attribute *attr, int n)
+{
+	struct perf_pmu_events_attr *pmu_attr;
+
+	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
+	if (mpc7450_is_l3_event(pmu_attr->id) && !cpu_has_feature(CPU_FTR_L3CR))
+		return 0;
+
+	return attr->mode;
+}
+
+static const struct attribute_group mpc7450_pmu_events_group = {
+	.name = "events",
+	.attrs = mpc7450_events_attr,
+	.is_visible = mpc7450_events_is_visible,
+};
+
 PMU_FORMAT_ATTR(event,		"config:0-18");
 PMU_FORMAT_ATTR(pmcsel,		"config:0-6");
 PMU_FORMAT_ATTR(pmc,		"config:8-10");
@@ -420,6 +481,7 @@ static const struct attribute_group mpc7450_pmu_format_group = {
 
 static const struct attribute_group *mpc7450_pmu_attr_groups[] = {
 	&mpc7450_pmu_format_group,
+	&mpc7450_pmu_events_group,
 	NULL,
 };
 

-- 
2.55.0

Re: [PATCH 0/8] powerpc/perf: mpc7450: Event fixes, SIAR sampling and sysfs event names

[Matt Turner]

On Mon, Nov 9, 2026 at 8:47 PM Matt Turner <mattst88@gmail.com> wrote:
> Tested on an iMac G4 (MPC7448).  The 7448 has no L3, so patch 5 and the
> L3 half of patch 8 are untested.

I should probably mention that it's an iMac G4 with an upgraded CPU:
https://mattst88.com/computers/imacg4/