[PATCH v2 09/19] cache: andes_llcache: write the full physical address for CCTL

[Mina Hui-Min Chou <minachou@andestech.com>]

The CCTL access line registers are 64 bits wide and hold the physical
address for PA-type CCTL operations, but the driver writes them with
writel(). On RV64, a physical address above 4 GiB loses its upper 32
bits, and the LLC operates on the wrong line.

Write the register with writeq(), using the lo-hi helper on RV32, so
that the whole physical address is always written.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 0aea1389f291..bf49dbcb080b 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -8,6 +8,7 @@
 #include <linux/cacheflush.h>
 #include <linux/cacheinfo.h>
 #include <linux/dma-direction.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/soc/andes/csr.h>
@@ -72,7 +73,8 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 		csr_write(CSR_UCCTLCOMMAND, l1_op);
 
 		pa = virt_to_phys((void *)start);
-		writel(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
+		/* The access line register is 64 bits; written lo-hi on RV32 */
+		writeq(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
 		writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
 		while ((andes_cpu_llc_get_cctl_status() &
 			ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=
-- 
2.34.1