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From: Mina Hui-Min Chou <minachou@andestech.com>
To: <pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<alex@ghiti.fr>, <conor@kernel.org>, <jic23@kernel.org>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<geert+renesas@glider.be>, <magnus.damm@gmail.com>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: <randolph@andestech.com>, <cyyang772@andestech.com>,
	<tim609@andestech.com>, <minachou@andestech.com>,
	<az70021@gmail.com>
Subject: [PATCH v2 01/19] cache: ax45mp_cache: use __initconst for ax45mp_cmo_ops
Date: Fri, 13 Nov 2026 15:11:25 +0800	[thread overview]
Message-ID: <20261113071143.1446167-2-minachou@andestech.com> (raw)
In-Reply-To: <20261113071143.1446167-1-minachou@andestech.com>

ax45mp_cmo_ops is const, but is placed in .init.data with __initdata.
Const init data belongs in .init.rodata, so annotate it with
__initconst instead.

riscv_noncoherent_register_cache_ops() copies the ops into
noncoherent_cache_ops, so the struct is still not used after init.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/ax45mp_cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index 934c5087ec2b..df40dea7b0d9 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -165,7 +165,7 @@ static int ax45mp_get_l2_line_size(struct device_node *np)
 	return 0;
 }
 
-static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initdata = {
+static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initconst = {
 	.wback = &ax45mp_dma_cache_wback,
 	.inv = &ax45mp_dma_cache_inv,
 	.wback_inv = &ax45mp_dma_cache_wback_inv,
-- 
2.34.1


  reply	other threads:[~2026-11-13  7:13 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-13  7:11 [PATCH v2 00/19] riscv: andes: make the LLC driver and cache errata generic Mina Hui-Min Chou
2026-11-13  7:11 ` Mina Hui-Min Chou [this message]
2026-11-13  7:11 ` [PATCH v2 02/19] cache: ax45mp_cache: rename AX45MP-specific identifiers to generic ANDES Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 03/19] cache: ax45mp_cache: rename L2 identifiers to LLC Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 04/19] cache: ax45mp_cache: add shared header for Andes CSRs Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 05/19] cache: ax45mp_cache: standardize macro naming for LLC and L1D registers Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 06/19] cache: ax45mp_cache: rename ax45mp_cache.c to andes_llcache.c Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 07/19] cache: andes_llcache: clean up cache inv/wback functions Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 08/19] cache: andes_llcache: use u32 and fix the cache-line-size error message Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 09/19] cache: andes_llcache: write the full physical address for CCTL Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 10/19] cache: andes_llcache: register cache ops only when the errata needs them Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 11/19] cache: andes_llcache: use the hart ID to index the CCTL registers Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 12/19] dt-bindings: cache: andestech: update schema for generic LLC support Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 13/19] dt-bindings: cache: rename andestech,ax45mp-cache to andestech,llcache Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 14/19] cache: andes_llcache: add generic andestech,llcache compatible Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 15/19] MAINTAINERS: Add maintainer for Andes cache driver Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 16/19] riscv: errata: andes: allow ERRATA_ANDES_CMO on all Andes SoCs Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 17/19] riscv: errata: andes: generalize cache errata for Andes cores Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five Mina Hui-Min Chou

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