From: Mina Hui-Min Chou <minachou@andestech.com>
To: <pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<alex@ghiti.fr>, <conor@kernel.org>, <jic23@kernel.org>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<geert+renesas@glider.be>, <magnus.damm@gmail.com>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-renesas-soc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <randolph@andestech.com>, <cyyang772@andestech.com>,
<tim609@andestech.com>, <minachou@andestech.com>,
<az70021@gmail.com>
Subject: [PATCH v2 13/19] dt-bindings: cache: rename andestech,ax45mp-cache to andestech,llcache
Date: Fri, 13 Nov 2026 15:11:37 +0800 [thread overview]
Message-ID: <20261113071143.1446167-14-minachou@andestech.com> (raw)
In-Reply-To: <20261113071143.1446167-1-minachou@andestech.com>
The binding now covers Andes last level caches beyond AX45MP and uses
andestech,llcache as the generic compatible. Rename the file to match
it.
Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
.../{andestech,ax45mp-cache.yaml => andestech,llcache.yaml} | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,llcache.yaml} (97%)
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,llcache.yaml
similarity index 97%
rename from Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
rename to Documentation/devicetree/bindings/cache/andestech,llcache.yaml
index da9688cc95f7..f97038d39b0e 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,llcache.yaml
@@ -2,7 +2,7 @@
# Copyright (C) 2023 Renesas Electronics Corp.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
+$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Andestech Last Level Cache Controller
--
2.34.1
next prev parent reply other threads:[~2026-11-13 7:13 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 7:11 [PATCH v2 00/19] riscv: andes: make the LLC driver and cache errata generic Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 01/19] cache: ax45mp_cache: use __initconst for ax45mp_cmo_ops Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 02/19] cache: ax45mp_cache: rename AX45MP-specific identifiers to generic ANDES Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 03/19] cache: ax45mp_cache: rename L2 identifiers to LLC Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 04/19] cache: ax45mp_cache: add shared header for Andes CSRs Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 05/19] cache: ax45mp_cache: standardize macro naming for LLC and L1D registers Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 06/19] cache: ax45mp_cache: rename ax45mp_cache.c to andes_llcache.c Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 07/19] cache: andes_llcache: clean up cache inv/wback functions Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 08/19] cache: andes_llcache: use u32 and fix the cache-line-size error message Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 09/19] cache: andes_llcache: write the full physical address for CCTL Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 10/19] cache: andes_llcache: register cache ops only when the errata needs them Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 11/19] cache: andes_llcache: use the hart ID to index the CCTL registers Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 12/19] dt-bindings: cache: andestech: update schema for generic LLC support Mina Hui-Min Chou
2026-11-13 7:11 ` Mina Hui-Min Chou [this message]
2026-11-13 7:11 ` [PATCH v2 14/19] cache: andes_llcache: add generic andestech,llcache compatible Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 15/19] MAINTAINERS: Add maintainer for Andes cache driver Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 16/19] riscv: errata: andes: allow ERRATA_ANDES_CMO on all Andes SoCs Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 17/19] riscv: errata: andes: generalize cache errata for Andes cores Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five Mina Hui-Min Chou
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