From: Mina Hui-Min Chou <minachou@andestech.com>
To: <pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<alex@ghiti.fr>, <conor@kernel.org>, <jic23@kernel.org>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<geert+renesas@glider.be>, <magnus.damm@gmail.com>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-renesas-soc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <randolph@andestech.com>, <cyyang772@andestech.com>,
<tim609@andestech.com>, <minachou@andestech.com>,
<az70021@gmail.com>
Subject: [PATCH v2 07/19] cache: andes_llcache: clean up cache inv/wback functions
Date: Fri, 13 Nov 2026 15:11:31 +0800 [thread overview]
Message-ID: <20261113071143.1446167-8-minachou@andestech.com> (raw)
In-Reply-To: <20261113071143.1446167-1-minachou@andestech.com>
Replace open-coded cache line alignment with ALIGN_DOWN/ALIGN helpers,
initialize line_size at declaration site, and use !size instead of
start == end for the early-out check. Drop redundant blank lines.
Also declare pa in andes_cpu_cache_operation() as phys_addr_t, the type
virt_to_phys() returns.
No functional change intended.
Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
drivers/cache/andes_llcache.c | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 61730e218afa..3c271e1e49bf 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -65,7 +65,7 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
unsigned long line_size = andes_priv.andes_cache_line_size;
void __iomem *base = andes_priv.llc_base;
int mhartid = smp_processor_id();
- unsigned long pa;
+ phys_addr_t pa;
while (end > start) {
csr_write(CSR_UCCTLBEGINADDR, start);
@@ -101,21 +101,17 @@ static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
{
unsigned long start = (unsigned long)phys_to_virt(paddr);
unsigned long end = start + size;
- unsigned long line_size;
+ unsigned long line_size = andes_priv.andes_cache_line_size;
unsigned long flags;
- if (unlikely(start == end))
+ if (unlikely(!size))
return;
- line_size = andes_priv.andes_cache_line_size;
-
- start = start & (~(line_size - 1));
- end = ((end + line_size - 1) & (~(line_size - 1)));
+ start = ALIGN_DOWN(start, line_size);
+ end = ALIGN(end, line_size);
local_irq_save(flags);
-
andes_cpu_dcache_inval_range(start, end);
-
local_irq_restore(flags);
}
@@ -123,15 +119,15 @@ static void andes_dma_cache_wback(phys_addr_t paddr, size_t size)
{
unsigned long start = (unsigned long)phys_to_virt(paddr);
unsigned long end = start + size;
- unsigned long line_size;
+ unsigned long line_size = andes_priv.andes_cache_line_size;
unsigned long flags;
- if (unlikely(start == end))
+ if (unlikely(!size))
return;
- line_size = andes_priv.andes_cache_line_size;
- start = start & (~(line_size - 1));
- end = ((end + line_size - 1) & (~(line_size - 1)));
+ start = ALIGN_DOWN(start, line_size);
+ end = ALIGN(end, line_size);
+
local_irq_save(flags);
andes_cpu_dcache_wb_range(start, end);
local_irq_restore(flags);
--
2.34.1
next prev parent reply other threads:[~2026-11-13 7:13 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 7:11 [PATCH v2 00/19] riscv: andes: make the LLC driver and cache errata generic Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 01/19] cache: ax45mp_cache: use __initconst for ax45mp_cmo_ops Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 02/19] cache: ax45mp_cache: rename AX45MP-specific identifiers to generic ANDES Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 03/19] cache: ax45mp_cache: rename L2 identifiers to LLC Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 04/19] cache: ax45mp_cache: add shared header for Andes CSRs Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 05/19] cache: ax45mp_cache: standardize macro naming for LLC and L1D registers Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 06/19] cache: ax45mp_cache: rename ax45mp_cache.c to andes_llcache.c Mina Hui-Min Chou
2026-11-13 7:11 ` Mina Hui-Min Chou [this message]
2026-11-13 7:11 ` [PATCH v2 08/19] cache: andes_llcache: use u32 and fix the cache-line-size error message Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 09/19] cache: andes_llcache: write the full physical address for CCTL Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 10/19] cache: andes_llcache: register cache ops only when the errata needs them Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 11/19] cache: andes_llcache: use the hart ID to index the CCTL registers Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 12/19] dt-bindings: cache: andestech: update schema for generic LLC support Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 13/19] dt-bindings: cache: rename andestech,ax45mp-cache to andestech,llcache Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 14/19] cache: andes_llcache: add generic andestech,llcache compatible Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 15/19] MAINTAINERS: Add maintainer for Andes cache driver Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 16/19] riscv: errata: andes: allow ERRATA_ANDES_CMO on all Andes SoCs Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 17/19] riscv: errata: andes: generalize cache errata for Andes cores Mina Hui-Min Chou
2026-11-13 7:11 ` [PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five Mina Hui-Min Chou
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