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From: Mina Hui-Min Chou <minachou@andestech.com>
To: <pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<alex@ghiti.fr>, <conor@kernel.org>, <jic23@kernel.org>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<geert+renesas@glider.be>, <magnus.damm@gmail.com>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: <randolph@andestech.com>, <cyyang772@andestech.com>,
	<tim609@andestech.com>, <minachou@andestech.com>,
	<az70021@gmail.com>
Subject: [PATCH v2 08/19] cache: andes_llcache: use u32 and fix the cache-line-size error message
Date: Fri, 13 Nov 2026 15:11:32 +0800	[thread overview]
Message-ID: <20261113071143.1446167-9-minachou@andestech.com> (raw)
In-Reply-To: <20261113071143.1446167-1-minachou@andestech.com>

andes_cpu_llc_get_cctl_status() returns uint32_t, while the rest of the
driver uses u32. Use u32 there as well.

When the cache-line-size property cannot be read, the error message
says the driver defaults to 64 bytes, but the driver returns the error
and does not register its cache ops. Drop the misleading part of the
message.

No functional change intended.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 3c271e1e49bf..0aea1389f291 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -54,7 +54,7 @@ struct andes_priv {
 static struct andes_priv andes_priv;
 
 /* LLC operations */
-static inline uint32_t andes_cpu_llc_get_cctl_status(void)
+static inline u32 andes_cpu_llc_get_cctl_status(void)
 {
 	return readl(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0);
 }
@@ -145,7 +145,7 @@ static int andes_get_llc_line_size(struct device_node *np)
 
 	ret = of_property_read_u32(np, "cache-line-size", &andes_priv.andes_cache_line_size);
 	if (ret) {
-		pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
+		pr_err("Failed to get cache-line-size\n");
 		return ret;
 	}
 
-- 
2.34.1


  parent reply	other threads:[~2026-11-13  7:13 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-13  7:11 [PATCH v2 00/19] riscv: andes: make the LLC driver and cache errata generic Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 01/19] cache: ax45mp_cache: use __initconst for ax45mp_cmo_ops Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 02/19] cache: ax45mp_cache: rename AX45MP-specific identifiers to generic ANDES Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 03/19] cache: ax45mp_cache: rename L2 identifiers to LLC Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 04/19] cache: ax45mp_cache: add shared header for Andes CSRs Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 05/19] cache: ax45mp_cache: standardize macro naming for LLC and L1D registers Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 06/19] cache: ax45mp_cache: rename ax45mp_cache.c to andes_llcache.c Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 07/19] cache: andes_llcache: clean up cache inv/wback functions Mina Hui-Min Chou
2026-11-13  7:11 ` Mina Hui-Min Chou [this message]
2026-11-13  7:11 ` [PATCH v2 09/19] cache: andes_llcache: write the full physical address for CCTL Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 10/19] cache: andes_llcache: register cache ops only when the errata needs them Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 11/19] cache: andes_llcache: use the hart ID to index the CCTL registers Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 12/19] dt-bindings: cache: andestech: update schema for generic LLC support Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 13/19] dt-bindings: cache: rename andestech,ax45mp-cache to andestech,llcache Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 14/19] cache: andes_llcache: add generic andestech,llcache compatible Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 15/19] MAINTAINERS: Add maintainer for Andes cache driver Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 16/19] riscv: errata: andes: allow ERRATA_ANDES_CMO on all Andes SoCs Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 17/19] riscv: errata: andes: generalize cache errata for Andes cores Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five Mina Hui-Min Chou

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