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From: Mina Hui-Min Chou <minachou@andestech.com>
To: <pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<alex@ghiti.fr>, <conor@kernel.org>, <jic23@kernel.org>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<geert+renesas@glider.be>, <magnus.damm@gmail.com>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: <randolph@andestech.com>, <cyyang772@andestech.com>,
	<tim609@andestech.com>, <minachou@andestech.com>,
	<az70021@gmail.com>
Subject: [PATCH v2 10/19] cache: andes_llcache: register cache ops only when the errata needs them
Date: Fri, 13 Nov 2026 15:11:34 +0800	[thread overview]
Message-ID: <20261113071143.1446167-11-minachou@andestech.com> (raw)
In-Reply-To: <20261113071143.1446167-1-minachou@andestech.com>

The driver registers its CCTL-based cache ops whenever
riscv_cbom_block_size is non-zero. On Andes cores with Zicbom, it holds
the Zicbom block size, so the CCTL ops would override the standard
Zicbom CMO.

Only register them when riscv_cbom_block_size is 1, the value the Andes
errata sets when the core needs CCTL-based cache maintenance.

Do this check before looking up the LLC node, so the driver does
nothing on platforms that do not need it. Once the errata has asked for
the CCTL ops, the LLC node is required to provide them, so report a
missing node with an error instead of failing silently.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index bf49dbcb080b..80c55616ab10 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -176,25 +176,25 @@ static int __init andes_cache_init(void)
 	struct resource res;
 	int ret;
 
+	/*
+	 * The Andes errata sets riscv_cbom_block_size to 1 only when the
+	 * core needs CCTL-based cache maintenance. Otherwise this driver is
+	 * not needed, so return without probing it any further.
+	 */
+	if (riscv_cbom_block_size != 1)
+		return 0;
+
 	struct device_node *np __free(device_node) =
 		of_find_matching_node(NULL, andes_cache_ids);
-	if (!of_device_is_available(np))
+	if (!of_device_is_available(np)) {
+		pr_err("No Andes LLC node found, cache ops not registered\n");
 		return -ENODEV;
+	}
 
 	ret = of_address_to_resource(np, 0, &res);
 	if (ret)
 		return ret;
 
-	/*
-	 * If IOCP is present on the Andes core riscv_cbom_block_size
-	 * will be 0 for sure, so we can definitely rely on it. If
-	 * riscv_cbom_block_size = 0 we don't need to handle CMO using SW any
-	 * more so we just return success here and only if its being set we
-	 * continue further in the probe path.
-	 */
-	if (!riscv_cbom_block_size)
-		return 0;
-
 	andes_priv.llc_base = ioremap(res.start, resource_size(&res));
 	if (!andes_priv.llc_base)
 		return -ENOMEM;
-- 
2.34.1


  parent reply	other threads:[~2026-11-13  7:14 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-13  7:11 [PATCH v2 00/19] riscv: andes: make the LLC driver and cache errata generic Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 01/19] cache: ax45mp_cache: use __initconst for ax45mp_cmo_ops Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 02/19] cache: ax45mp_cache: rename AX45MP-specific identifiers to generic ANDES Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 03/19] cache: ax45mp_cache: rename L2 identifiers to LLC Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 04/19] cache: ax45mp_cache: add shared header for Andes CSRs Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 05/19] cache: ax45mp_cache: standardize macro naming for LLC and L1D registers Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 06/19] cache: ax45mp_cache: rename ax45mp_cache.c to andes_llcache.c Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 07/19] cache: andes_llcache: clean up cache inv/wback functions Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 08/19] cache: andes_llcache: use u32 and fix the cache-line-size error message Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 09/19] cache: andes_llcache: write the full physical address for CCTL Mina Hui-Min Chou
2026-11-13  7:11 ` Mina Hui-Min Chou [this message]
2026-11-13  7:11 ` [PATCH v2 11/19] cache: andes_llcache: use the hart ID to index the CCTL registers Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 12/19] dt-bindings: cache: andestech: update schema for generic LLC support Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 13/19] dt-bindings: cache: rename andestech,ax45mp-cache to andestech,llcache Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 14/19] cache: andes_llcache: add generic andestech,llcache compatible Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 15/19] MAINTAINERS: Add maintainer for Andes cache driver Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 16/19] riscv: errata: andes: allow ERRATA_ANDES_CMO on all Andes SoCs Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 17/19] riscv: errata: andes: generalize cache errata for Andes cores Mina Hui-Min Chou
2026-11-13  7:11 ` [PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five Mina Hui-Min Chou

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