[PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five

[Mina Hui-Min Chou <minachou@andestech.com>]

The SBI-based IOCP check was added for Renesas RZ/Five (R9A07G043F),
the only upstream-supported SoC whose AX45MP has no IOCP. It matches
the AX45MP marchid and the mimpid of the RZ/Five core, but it is built
into every kernel with ERRATA_ANDES_CMO, so the SBI call is issued even
when the kernel does not support RZ/Five.

Move the match into soc_is_r9a07g043f() and make it also require
ARCH_R9A07G043. Kernels without RZ/Five support then skip the SBI call
and take the generic Andes cache errata path. No other upstream-
supported SoC uses this AX45MP mimpid, so their behavior does not
change.

While at it, rename ax45mp_iocp_sw_workaround() to
r9a07g043f_iocp_sw_workaround(), as the check is only used for RZ/Five.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 arch/riscv/errata/andes/errata.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
index 530d2df216e0..f2535a81b1e2 100644
--- a/arch/riscv/errata/andes/errata.c
+++ b/arch/riscv/errata/andes/errata.c
@@ -25,7 +25,7 @@
 
 #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND	1
 
-static long ax45mp_iocp_sw_workaround(void)
+static long r9a07g043f_iocp_sw_workaround(void)
 {
 	struct sbiret ret;
 
@@ -39,6 +39,13 @@ static long ax45mp_iocp_sw_workaround(void)
 	return ret.error ? 0 : ret.value;
 }
 
+static bool soc_is_r9a07g043f(unsigned long arch_id, unsigned long impid)
+{
+	return IS_ENABLED(CONFIG_ARCH_R9A07G043) &&
+	       arch_id == ANDES_AX45MP_MARCHID &&
+	       impid == ANDES_AX45MP_MIMPID;
+}
+
 static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id, unsigned long impid)
 {
 	static bool done;
@@ -51,8 +58,8 @@ static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id,
 
 	done = true;
 
-	if (arch_id == ANDES_AX45MP_MARCHID && impid == ANDES_AX45MP_MIMPID) {
-		if (!ax45mp_iocp_sw_workaround())
+	if (soc_is_r9a07g043f(arch_id, impid)) {
+		if (!r9a07g043f_iocp_sw_workaround())
 			return;
 	} else if (riscv_isa_extension_available(NULL, ZICBOM)) {
 		return;
-- 
2.34.1