[PATCH 0/5] Add interconnects to QUPs on SM8250

[PATCH 0/5] Add interconnects to QUPs on SM8250

[Konrad Dybcio]

SM8250 (like SM8150 but unlike all other QUP-equipped SoCs) doesn't
provide a qup-core path. Adjust the bindings and drivers as necessary,
and then describe the icc paths in the device tree. This makes it possible
for interconnect sync_state succeed so long as you don't use UFS.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (5):
      dt-bindings: spi: spi-geni-qcom: Allow no qup-core icc path
      dt-bindings: serial: geni-qcom: Allow no qup-core icc path
      dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path
      soc: qcom: geni-se: Allow any combination of icc paths
      arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs

 .../bindings/i2c/qcom,i2c-geni-qcom.yaml           |  27 ++--
 .../bindings/serial/qcom,serial-geni-qcom.yaml     |  26 ++--
 .../bindings/spi/qcom,spi-geni-qcom.yaml           |  15 ++-
 arch/arm64/boot/dts/qcom/sm8250.dtsi               | 150 +++++++++++++++++++++
 drivers/soc/qcom/qcom-geni-se.c                    |   9 +-
 5 files changed, 204 insertions(+), 23 deletions(-)
---
base-commit: 296d53d8f84ce50ffaee7d575487058c8d437335
change-id: 20230703-topic-8250_qup_icc-61768a34c7ec

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@linaro.org>

[PATCH 1/5] dt-bindings: spi: spi-geni-qcom: Allow no qup-core icc path

[Konrad Dybcio]

Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
Allow such case.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml       | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
index 2e20ca313ec1..2890c4968c2a 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
@@ -49,11 +49,16 @@ properties:
     maxItems: 3
 
   interconnect-names:
-    minItems: 2
-    items:
-      - const: qup-core
-      - const: qup-config
-      - const: qup-memory
+    oneOf:
+      - items:
+          - const: qup-config
+          - const: qup-memory
+
+      - minItems: 2
+        items:
+          - const: qup-core
+          - const: qup-config
+          - const: qup-memory
 
   interrupts:
     maxItems: 1

-- 
2.41.0

Re: [PATCH 1/5] dt-bindings: spi: spi-geni-qcom: Allow no qup-core icc path

[Krzysztof Kozlowski]

On 03/07/2023 15:31, Konrad Dybcio wrote:
> Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
> Allow such case.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  .../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml       | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 2/5] dt-bindings: serial: geni-qcom: Allow no qup-core icc path

[Konrad Dybcio]

Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
Allow such case.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../bindings/serial/qcom,serial-geni-qcom.yaml     | 26 +++++++++++++++-------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
index dd33794b3534..a0acba57bc06 100644
--- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
@@ -25,14 +25,6 @@ properties:
   clock-names:
     const: se
 
-  interconnects:
-    maxItems: 2
-
-  interconnect-names:
-    items:
-      - const: qup-core
-      - const: qup-config
-
   interrupts:
     minItems: 1
     items:
@@ -56,6 +48,24 @@ properties:
   reg:
     maxItems: 1
 
+oneOf:
+  - properties:
+      interconnects:
+        maxItems: 1
+
+      interconnect-names:
+        items:
+          - const: qup-config
+
+  - properties:
+      interconnects:
+        minItems: 2
+
+      interconnect-names:
+        items:
+          - const: qup-core
+          - const: qup-config
+
 required:
   - compatible
   - clocks

-- 
2.41.0

Re: [PATCH 2/5] dt-bindings: serial: geni-qcom: Allow no qup-core icc path

[Krzysztof Kozlowski]

On 03/07/2023 15:31, Konrad Dybcio wrote:
> Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
> Allow such case.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  .../bindings/serial/qcom,serial-geni-qcom.yaml     | 26 +++++++++++++++-------
>  1 file changed, 18 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> index dd33794b3534..a0acba57bc06 100644
> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> @@ -25,14 +25,6 @@ properties:
>    clock-names:
>      const: se
>  
> -  interconnects:
> -    maxItems: 2
> -
> -  interconnect-names:
> -    items:
> -      - const: qup-core
> -      - const: qup-config

Instead please keep the definition of the fields in top-level properties
with the widest constraints, e.g.
interconnects:
  minItems: 1
  maxItems: 2

interconnect-names:
  minItems: 1
  items:
   - const: qup-core
   - const: qup-config

If there was allOf:if:then per variant, this could be further customized.

Best regards,
Krzysztof

Re: [PATCH 2/5] dt-bindings: serial: geni-qcom: Allow no qup-core icc path

[Konrad Dybcio]

On 3.07.2023 16:01, Krzysztof Kozlowski wrote:
> On 03/07/2023 15:31, Konrad Dybcio wrote:
>> Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
>> Allow such case.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>  .../bindings/serial/qcom,serial-geni-qcom.yaml     | 26 +++++++++++++++-------
>>  1 file changed, 18 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> index dd33794b3534..a0acba57bc06 100644
>> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> @@ -25,14 +25,6 @@ properties:
>>    clock-names:
>>      const: se
>>  
>> -  interconnects:
>> -    maxItems: 2
>> -
>> -  interconnect-names:
>> -    items:
>> -      - const: qup-core
>> -      - const: qup-config
> 
> Instead please keep the definition of the fields in top-level properties
> with the widest constraints, e.g.
> interconnects:
>   minItems: 1
>   maxItems: 2
> 
> interconnect-names:
>   minItems: 1
>   items:
>    - const: qup-core
>    - const: qup-config
Sadly the issue here is that the qup-config path exists, but qup-core
doesn't.

Konrad
> 
> If there was allOf:if:then per variant, this could be further customized.
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 2/5] dt-bindings: serial: geni-qcom: Allow no qup-core icc path

[Krzysztof Kozlowski]

On 03/07/2023 16:38, Konrad Dybcio wrote:
> On 3.07.2023 16:01, Krzysztof Kozlowski wrote:
>> On 03/07/2023 15:31, Konrad Dybcio wrote:
>>> Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
>>> Allow such case.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>>>  .../bindings/serial/qcom,serial-geni-qcom.yaml     | 26 +++++++++++++++-------
>>>  1 file changed, 18 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> index dd33794b3534..a0acba57bc06 100644
>>> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> @@ -25,14 +25,6 @@ properties:
>>>    clock-names:
>>>      const: se
>>>  
>>> -  interconnects:
>>> -    maxItems: 2
>>> -
>>> -  interconnect-names:
>>> -    items:
>>> -      - const: qup-core
>>> -      - const: qup-config
>>
>> Instead please keep the definition of the fields in top-level properties
>> with the widest constraints, e.g.
>> interconnects:
>>   minItems: 1
>>   maxItems: 2
>>
>> interconnect-names:
>>   minItems: 1
>>   items:
>>    - const: qup-core
>>    - const: qup-config
> Sadly the issue here is that the qup-config path exists, but qup-core
> doesn't.

Ah, right, then:
interconnect-names:
  oneOf:
    - items:
      ....
    - items:
      ...

Best regards,
Krzysztof

Re: [PATCH 2/5] dt-bindings: serial: geni-qcom: Allow no qup-core icc path

[Rob Herring]

On Mon, 03 Jul 2023 15:31:11 +0200, Konrad Dybcio wrote:
> Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
> Allow such case.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  .../bindings/serial/qcom,serial-geni-qcom.yaml     | 26 +++++++++++++++-------
>  1 file changed, 18 insertions(+), 8 deletions(-)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@8c0000: serial@a88000: More than one condition true in oneOf schema:
	{'$filename': '/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml',
	 '$id': 'http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#',
	 '$schema': 'http://devicetree.org/meta-schemas/core.yaml#',
	 'allOf': [{'$ref': '/schemas/serial/serial.yaml#'},
	           {'oneOf': [{'required': ['interrupts']},
	                      {'required': ['interrupts-extended']}]}],
	 'oneOf': [{'patternProperties': {'pinctrl-[0-9]+': True},
	            'properties': {'$nodename': True,
	                           'bootph-all': True,
	                           'bootph-pre-ram': True,
	                           'bootph-pre-sram': True,
	                           'bootph-some-ram': True,
	                           'bootph-verify': True,
	                           'interconnect-names': {'items': [{'const': 'qup-config'}],
	                                                  'maxItems': 1,
	                                                  'minItems': 1,
	                                                  'type': 'array'},
	                           'interconnects': {'maxItems': 1,
	                                             'minItems': 1},
	                           'phandle': True,
	                           'pinctrl-names': True,
	                           'secure-status': True,
	                           'status': True}},
	           {'patternProperties': {'pinctrl-[0-9]+': True},
	            'properties': {'$nodename': True,
	                           'bootph-all': True,
	                           'bootph-pre-ram': True,
	                           'bootph-pre-sram': True,
	                           'bootph-some-ram': True,
	                           'bootph-verify': True,
	                           'interconnect-names': {'items': [{'const': 'qup-core'},
	                                                            {'const': 'qup-config'}],
	                                                  'maxItems': 2,
	                                                  'minItems': 2,
	                                                  'type': 'array'},
	                           'interconnects': {'maxItems': 2,
	                                             'minItems': 2},
	                           'phandle': True,
	                           'pinctrl-names': True,
	                           'secure-status': True,
	                           'status': True}}],
	 'properties': {'$nodename': True,
	                'assigned-clock-parents': True,
	                'assigned-clock-rates': True,
	                'assigned-clocks': True,
	                'bootph-all': True,
	                'bootph-pre-ram': True,
	                'bootph-pre-sram': True,
	                'bootph-some-ram': True,
	                'bootph-verify': True,
	                'clock-names': {'items': [{'const': 'se'}],
	                                'maxItems': 1,
	                                'minItems': 1,
	                                'type': 'array'},
	                'clocks': {'maxItems': 1, 'minItems': 1},
	                'compatible': {'items': [{'enum': ['qcom,geni-uart',
	                                                   'qcom,geni-debug-uart']}],
	                               'maxItems': 1,
	                               'minItems': 1,
	                               'type': 'array'},
	                'interrupt-parent': True,
	                'interrupts': {'maxItems': 2,
	                               'minItems': 1,
	                               'type': 'array'},
	                'interrupts-extended': {'maxItems': 2,
	                                        'minItems': 1,
	                                        'type': 'array'},
	                'operating-points-v2': True,
	                'phandle': True,
	                'pinctrl-0': True,
	                'pinctrl-1': True,
	                'pinctrl-names': {'items': [{'const': 'default'},
	                                            {'const': 'sleep'}],
	                                  'maxItems': 2,
	                                  'minItems': 1,
	                                  'type': 'array'},
	                'power-domains': {'maxItems': 1, 'minItems': 1},
	                'reg': {'maxItems': 1, 'minItems': 1},
	                'secure-status': True,
	                'status': True},
	 'required': ['compatible', 'clocks', 'clock-names', 'reg'],
	 'select': {'properties': {'compatible': {'contains': {'enum': ['qcom,geni-debug-uart',
	                                                                'qcom,geni-uart']}}},
	            'required': ['compatible']},
	 'title': 'Qualcomm Geni based QUP UART interface',
	 'type': 'object',
	 'unevaluatedProperties': False}
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: serial@a88000: More than one condition true in oneOf schema:
	{'$filename': '/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml',
	 '$id': 'http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#',
	 '$schema': 'http://devicetree.org/meta-schemas/core.yaml#',
	 'allOf': [{'$ref': '/schemas/serial/serial.yaml#'},
	           {'oneOf': [{'required': ['interrupts']},
	                      {'required': ['interrupts-extended']}]}],
	 'oneOf': [{'patternProperties': {'pinctrl-[0-9]+': True},
	            'properties': {'$nodename': True,
	                           'bootph-all': True,
	                           'bootph-pre-ram': True,
	                           'bootph-pre-sram': True,
	                           'bootph-some-ram': True,
	                           'bootph-verify': True,
	                           'interconnect-names': {'items': [{'const': 'qup-config'}],
	                                                  'maxItems': 1,
	                                                  'minItems': 1,
	                                                  'type': 'array'},
	                           'interconnects': {'maxItems': 1,
	                                             'minItems': 1},
	                           'phandle': True,
	                           'pinctrl-names': True,
	                           'secure-status': True,
	                           'status': True}},
	           {'patternProperties': {'pinctrl-[0-9]+': True},
	            'properties': {'$nodename': True,
	                           'bootph-all': True,
	                           'bootph-pre-ram': True,
	                           'bootph-pre-sram': True,
	                           'bootph-some-ram': True,
	                           'bootph-verify': True,
	                           'interconnect-names': {'items': [{'const': 'qup-core'},
	                                                            {'const': 'qup-config'}],
	                                                  'maxItems': 2,
	                                                  'minItems': 2,
	                                                  'type': 'array'},
	                           'interconnects': {'maxItems': 2,
	                                             'minItems': 2},
	                           'phandle': True,
	                           'pinctrl-names': True,
	                           'secure-status': True,
	                           'status': True}}],
	 'properties': {'$nodename': True,
	                'assigned-clock-parents': True,
	                'assigned-clock-rates': True,
	                'assigned-clocks': True,
	                'bootph-all': True,
	                'bootph-pre-ram': True,
	                'bootph-pre-sram': True,
	                'bootph-some-ram': True,
	                'bootph-verify': True,
	                'clock-names': {'items': [{'const': 'se'}],
	                                'maxItems': 1,
	                                'minItems': 1,
	                                'type': 'array'},
	                'clocks': {'maxItems': 1, 'minItems': 1},
	                'compatible': {'items': [{'enum': ['qcom,geni-uart',
	                                                   'qcom,geni-debug-uart']}],
	                               'maxItems': 1,
	                               'minItems': 1,
	                               'type': 'array'},
	                'interrupt-parent': True,
	                'interrupts': {'maxItems': 2,
	                               'minItems': 1,
	                               'type': 'array'},
	                'interrupts-extended': {'maxItems': 2,
	                                        'minItems': 1,
	                                        'type': 'array'},
	                'operating-points-v2': True,
	                'phandle': True,
	                'pinctrl-0': True,
	                'pinctrl-1': True,
	                'pinctrl-names': {'items': [{'const': 'default'},
	                                            {'const': 'sleep'}],
	                                  'maxItems': 2,
	                                  'minItems': 1,
	                                  'type': 'array'},
	                'power-domains': {'maxItems': 1, 'minItems': 1},
	                'reg': {'maxItems': 1, 'minItems': 1},
	                'secure-status': True,
	                'status': True},
	 'required': ['compatible', 'clocks', 'clock-names', 'reg'],
	 'select': {'properties': {'compatible': {'contains': {'enum': ['qcom,geni-debug-uart',
	                                                                'qcom,geni-uart']}}},
	            'required': ['compatible']},
	 'title': 'Qualcomm Geni based QUP UART interface',
	 'type': 'object',
	 'unevaluatedProperties': False}
	from schema $id: http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230703-topic-8250_qup_icc-v1-2-fea39aa07525@linaro.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH 3/5] dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path

[Konrad Dybcio]

Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
Allow such case.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../bindings/i2c/qcom,i2c-geni-qcom.yaml           | 27 +++++++++++++++-------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
index 9f66a3bb1f80..f92b6d7fc7c5 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
@@ -108,14 +108,25 @@ allOf:
         clock-names:
           const: se
 
-        interconnects:
-          minItems: 3
-
-        interconnect-names:
-          items:
-            - const: qup-core
-            - const: qup-config
-            - const: qup-memory
+      oneOf:
+        - properties:
+            interconnects:
+              maxItems: 2
+
+            interconnect-names:
+              items:
+                - const: qup-config
+                - const: qup-memory
+
+        - properties:
+            interconnects:
+              minItems: 3
+
+            interconnect-names:
+              items:
+                - const: qup-core
+                - const: qup-config
+                - const: qup-memory
 
 unevaluatedProperties: false
 

-- 
2.41.0

Re: [PATCH 3/5] dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path

[Krzysztof Kozlowski]

On 03/07/2023 15:31, Konrad Dybcio wrote:
> Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
> Allow such case.
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/5] dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path

[Krzysztof Kozlowski]

On 03/07/2023 16:36, Krzysztof Kozlowski wrote:
> On 03/07/2023 15:31, Konrad Dybcio wrote:
>> Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
>> Allow such case.
>>
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Un-reviewed. Don't define properties in oneOf, instead use the syntax I
pointed out in other patch. If you remove interconnects from this
example, you will reproduce the error.

This should be something like:
          interconnects:


            minItems: 2
            maxItems: 3

          interconnect-names:
            oneOf:
              - items:
                  - const: qup-config
                  - const: qup-memory

              - items:
                  - const: qup-core
                  - const: qup-config
                  - const: qup-memory


Best regards,
Krzysztof

Re: [PATCH 3/5] dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path

[Rob Herring]

On Mon, 03 Jul 2023 15:31:12 +0200, Konrad Dybcio wrote:
> Some SoCs (like SM8150 and SM8250) don't seem to provide a qup-core path.
> Allow such case.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  .../bindings/i2c/qcom,i2c-geni-qcom.yaml           | 27 +++++++++++++++-------
>  1 file changed, 19 insertions(+), 8 deletions(-)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:

/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@8c0000: i2c@a94000: More than one condition true in oneOf schema:
	{'oneOf': [{'patternProperties': {'pinctrl-[0-9]+': True},
	            'properties': {'$nodename': True,
	                           'bootph-all': True,
	                           'bootph-pre-ram': True,
	                           'bootph-pre-sram': True,
	                           'bootph-some-ram': True,
	                           'bootph-verify': True,
	                           'interconnect-names': {'items': [{'const': 'qup-config'},
	                                                            {'const': 'qup-memory'}],
	                                                  'maxItems': 2,
	                                                  'minItems': 2,
	                                                  'type': 'array'},
	                           'interconnects': {'maxItems': 2,
	                                             'minItems': 2},
	                           'phandle': True,
	                           'pinctrl-names': True,
	                           'secure-status': True,
	                           'status': True}},
	           {'patternProperties': {'pinctrl-[0-9]+': True},
	            'properties': {'$nodename': True,
	                           'bootph-all': True,
	                           'bootph-pre-ram': True,
	                           'bootph-pre-sram': True,
	                           'bootph-some-ram': True,
	                           'bootph-verify': True,
	                           'interconnect-names': {'items': [{'const': 'qup-core'},
	                                                            {'const': 'qup-config'},
	                                                            {'const': 'qup-memory'}],
	                                                  'maxItems': 3,
	                                                  'minItems': 3,
	                                                  'type': 'array'},
	                           'interconnects': {'maxItems': 3,
	                                             'minItems': 3},
	                           'phandle': True,
	                           'pinctrl-names': True,
	                           'secure-status': True,
	                           'status': True}}],
	 'properties': {'clock-names': {'items': [{'const': 'se'}],
	                                'maxItems': 1,
	                                'minItems': 1,
	                                'type': 'array'},
	                'clocks': {'maxItems': 1, 'minItems': 1}}}
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: i2c@a94000: More than one condition true in oneOf schema:
	{'oneOf': [{'patternProperties': {'pinctrl-[0-9]+': True},
	            'properties': {'$nodename': True,
	                           'bootph-all': True,
	                           'bootph-pre-ram': True,
	                           'bootph-pre-sram': True,
	                           'bootph-some-ram': True,
	                           'bootph-verify': True,
	                           'interconnect-names': {'items': [{'const': 'qup-config'},
	                                                            {'const': 'qup-memory'}],
	                                                  'maxItems': 2,
	                                                  'minItems': 2,
	                                                  'type': 'array'},
	                           'interconnects': {'maxItems': 2,
	                                             'minItems': 2},
	                           'phandle': True,
	                           'pinctrl-names': True,
	                           'secure-status': True,
	                           'status': True}},
	           {'patternProperties': {'pinctrl-[0-9]+': True},
	            'properties': {'$nodename': True,
	                           'bootph-all': True,
	                           'bootph-pre-ram': True,
	                           'bootph-pre-sram': True,
	                           'bootph-some-ram': True,
	                           'bootph-verify': True,
	                           'interconnect-names': {'items': [{'const': 'qup-core'},
	                                                            {'const': 'qup-config'},
	                                                            {'const': 'qup-memory'}],
	                                                  'maxItems': 3,
	                                                  'minItems': 3,
	                                                  'type': 'array'},
	                           'interconnects': {'maxItems': 3,
	                                             'minItems': 3},
	                           'phandle': True,
	                           'pinctrl-names': True,
	                           'secure-status': True,
	                           'status': True}}],
	 'properties': {'clock-names': {'items': [{'const': 'se'}],
	                                'maxItems': 1,
	                                'minItems': 1,
	                                'type': 'array'},
	                'clocks': {'maxItems': 1, 'minItems': 1}}}
	from schema $id: http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230703-topic-8250_qup_icc-v1-3-fea39aa07525@linaro.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH 4/5] soc: qcom: geni-se: Allow any combination of icc paths

[Konrad Dybcio]

Not all SoCs provide all the usual paths. By the looks of it, at least
SM8150 and SM8250 don't have one that would resemble "qup-core".

Check for the error that icc_get throws and assign a NULL value to each
path that can't be found to effectively allow any combination of icc paths
(which, like previously, includes no icc paths). The ICC APIs gracefully
handle a NULL path by exiting early.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/soc/qcom/qcom-geni-se.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index ba788762835f..a5e2e8925c8e 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -813,8 +813,13 @@ int geni_icc_get(struct geni_se *se, const char *icc_ddr)
 			continue;
 
 		se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);
-		if (IS_ERR(se->icc_paths[i].path))
-			goto err;
+		if (IS_ERR(se->icc_paths[i].path)) {
+			/* Not all SoCs implement all the paths */
+			if (PTR_ERR(se->icc_paths[i].path) == -ENODATA)
+				se->icc_paths[i].path = NULL;
+			else
+				goto err;
+		}
 	}
 
 	return 0;

-- 
2.41.0

Re: [PATCH 4/5] soc: qcom: geni-se: Allow any combination of icc paths

[Dmitry Baryshkov]

On 03/07/2023 16:31, Konrad Dybcio wrote:
> Not all SoCs provide all the usual paths. By the looks of it, at least
> SM8150 and SM8250 don't have one that would resemble "qup-core".
> 
> Check for the error that icc_get throws and assign a NULL value to each
> path that can't be found to effectively allow any combination of icc paths
> (which, like previously, includes no icc paths). The ICC APIs gracefully
> handle a NULL path by exiting early.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/soc/qcom/qcom-geni-se.c | 9 +++++++--
>   1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
> index ba788762835f..a5e2e8925c8e 100644
> --- a/drivers/soc/qcom/qcom-geni-se.c
> +++ b/drivers/soc/qcom/qcom-geni-se.c
> @@ -813,8 +813,13 @@ int geni_icc_get(struct geni_se *se, const char *icc_ddr)
>   			continue;
>   
>   		se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);

Would it make sense to add (devm_)of_icc_get_optional instead?  I think 
we already have several usecases for such API call

For this patch:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> -		if (IS_ERR(se->icc_paths[i].path))
> -			goto err;
> +		if (IS_ERR(se->icc_paths[i].path)) {
> +			/* Not all SoCs implement all the paths */
> +			if (PTR_ERR(se->icc_paths[i].path) == -ENODATA)
> +				se->icc_paths[i].path = NULL;
> +			else
> +				goto err;
> +		}
>   	}
>   
>   	return 0;
> 

-- 
With best wishes
Dmitry

[PATCH 5/5] arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs

[Konrad Dybcio]

Describe the interconnect paths related to QUPs and add the power-domains
powering them.

This is required for icc sync_state, as otherwise QUP access is gated.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 150 +++++++++++++++++++++++++++++++++++
 1 file changed, 150 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 1efa07f2caff..35111fce898a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1022,6 +1022,10 @@ i2c14: i2c@880000 {
 				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1038,6 +1042,9 @@ spi14: spi@880000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1054,6 +1061,10 @@ i2c15: i2c@884000 {
 				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1070,6 +1081,9 @@ spi15: spi@884000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1086,6 +1100,10 @@ i2c16: i2c@888000 {
 				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1102,6 +1120,9 @@ spi16: spi@888000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1118,6 +1139,10 @@ i2c17: i2c@88c000 {
 				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1134,6 +1159,9 @@ spi17: spi@88c000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1149,6 +1177,8 @@ uart17: serial@88c000 {
 				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
+				interconnect-names = "qup-config";
 				status = "disabled";
 			};
 
@@ -1163,6 +1193,10 @@ i2c18: i2c@890000 {
 				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1179,6 +1213,9 @@ spi18: spi@890000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1194,6 +1231,8 @@ uart18: serial@890000 {
 				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
+				interconnect-names = "qup-config";
 				status = "disabled";
 			};
 
@@ -1208,6 +1247,10 @@ i2c19: i2c@894000 {
 				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1224,6 +1267,9 @@ spi19: spi@894000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+						<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1276,6 +1322,10 @@ i2c0: i2c@980000 {
 				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1292,6 +1342,9 @@ spi0: spi@980000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1308,6 +1361,10 @@ i2c1: i2c@984000 {
 				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1324,6 +1381,9 @@ spi1: spi@984000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1340,6 +1400,10 @@ i2c2: i2c@988000 {
 				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1356,6 +1420,9 @@ spi2: spi@988000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1371,6 +1438,8 @@ uart2: serial@988000 {
 				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
+				interconnect-names = "qup-config";
 				status = "disabled";
 			};
 
@@ -1385,6 +1454,10 @@ i2c3: i2c@98c000 {
 				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1401,6 +1474,9 @@ spi3: spi@98c000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1417,6 +1493,10 @@ i2c4: i2c@990000 {
 				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1433,6 +1513,9 @@ spi4: spi@990000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1449,6 +1532,10 @@ i2c5: i2c@994000 {
 				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1465,6 +1552,9 @@ spi5: spi@994000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1481,6 +1571,10 @@ i2c6: i2c@998000 {
 				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1497,6 +1591,9 @@ spi6: spi@998000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1512,6 +1609,8 @@ uart6: serial@998000 {
 				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
+				interconnect-names = "qup-config";
 				status = "disabled";
 			};
 
@@ -1526,6 +1625,10 @@ i2c7: i2c@99c000 {
 				dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1542,6 +1645,9 @@ spi7: spi@99c000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1591,6 +1697,10 @@ i2c8: i2c@a80000 {
 				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1607,6 +1717,9 @@ spi8: spi@a80000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1623,6 +1736,10 @@ i2c9: i2c@a84000 {
 				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1639,6 +1756,9 @@ spi9: spi@a84000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1655,6 +1775,10 @@ i2c10: i2c@a88000 {
 				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1671,6 +1795,9 @@ spi10: spi@a88000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1687,6 +1814,10 @@ i2c11: i2c@a8c000 {
 				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1703,6 +1834,9 @@ spi11: spi@a8c000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1719,6 +1853,10 @@ i2c12: i2c@a90000 {
 				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1735,6 +1873,9 @@ spi12: spi@a90000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1750,6 +1891,8 @@ uart12: serial@a90000 {
 				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
+				interconnect-names = "qup-config";
 				status = "disabled";
 			};
 
@@ -1764,6 +1907,10 @@ i2c13: i2c@a94000 {
 				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx", "rx";
+				power-domains = <&rpmhpd SM8250_CX>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";
@@ -1780,6 +1927,9 @@ spi13: spi@a94000 {
 				dma-names = "tx", "rx";
 				power-domains = <&rpmhpd SM8250_CX>;
 				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+						<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+				interconnect-names = "qup-config", "qup-memory";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				status = "disabled";

-- 
2.41.0

Re: [PATCH 5/5] arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs

[Dmitry Baryshkov]

On 03/07/2023 16:31, Konrad Dybcio wrote:
> Describe the interconnect paths related to QUPs and add the power-domains
> powering them.
> 
> This is required for icc sync_state, as otherwise QUP access is gated.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8250.dtsi | 150 +++++++++++++++++++++++++++++++++++
>   1 file changed, 150 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 0/5] Add interconnects to QUPs on SM8250

[Bjorn Andersson]

On Mon, Jul 03, 2023 at 03:31:09PM +0200, Konrad Dybcio wrote:
> SM8250 (like SM8150 but unlike all other QUP-equipped SoCs) doesn't
> provide a qup-core path. Adjust the bindings and drivers as necessary,
> and then describe the icc paths in the device tree. This makes it possible
> for interconnect sync_state succeed so long as you don't use UFS.
> 

The "qup-core" path is a vote between two nodes on the QUP0 BCM, to
provide a frequency vote on the QUP core(s). Both SM8150 and SM8250 has
this BCM, but as you point out it's not exposed through the interconnect
provider.

I don't know why this is, but I think it would be preferable to amend
the provider.

Regards,
Bjorn

> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> Konrad Dybcio (5):
>       dt-bindings: spi: spi-geni-qcom: Allow no qup-core icc path
>       dt-bindings: serial: geni-qcom: Allow no qup-core icc path
>       dt-bindings: i2c: qcom,i2c-geni: Allow no qup-core icc path
>       soc: qcom: geni-se: Allow any combination of icc paths
>       arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs
> 
>  .../bindings/i2c/qcom,i2c-geni-qcom.yaml           |  27 ++--
>  .../bindings/serial/qcom,serial-geni-qcom.yaml     |  26 ++--
>  .../bindings/spi/qcom,spi-geni-qcom.yaml           |  15 ++-
>  arch/arm64/boot/dts/qcom/sm8250.dtsi               | 150 +++++++++++++++++++++
>  drivers/soc/qcom/qcom-geni-se.c                    |   9 +-
>  5 files changed, 204 insertions(+), 23 deletions(-)
> ---
> base-commit: 296d53d8f84ce50ffaee7d575487058c8d437335
> change-id: 20230703-topic-8250_qup_icc-61768a34c7ec
> 
> Best regards,
> -- 
> Konrad Dybcio <konrad.dybcio@linaro.org>
>