* [PATCH v5 0/3] add sysfs nodes to configure TPDA's registers
@ 2025-12-19 10:04 Jie Gan
2025-12-19 10:04 ` [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration Jie Gan
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Jie Gan @ 2025-12-19 10:04 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Tingwei Zhang
Cc: coresight, linux-arm-kernel, linux-kernel, Jie Gan, Tao Zhang
Patchset 1 introduces configuration of the global control register with
appropriate values to enable proper generation of cross-trigger packets.
Patchset 2 introduces a logic to configure the TPDA_SYNCR register,
which determines the frequency of ASYNC packet generation. These packets
assist userspace tools in accurately identifying each valid packet.
Patchset 3 introduces a sysfs node to initiate a flush request for the
specific port, forcing the data to synchronize and be transmitted to the
sink device.
Chnages in V5:
1. Optimizing the solution to creat sysfs nodes.
2. Optimizing the logic for configuring bits of the global control
register.
Link to V4 - https://lore.kernel.org/all/20251028-configure_tpda_reg-v4-0-23000805d21d@oss.qualcomm.com/
Changes in V4:
1. Document sysfs nodes with correct kernel version and date.
Link to V3 - https://lore.kernel.org/linux-arm-kernel/20250827105545.7140-1-jie.gan@oss.qualcomm.com/
Changes in V3:
1. Optimizing codes according to James's comment.
Link to V2 - https://lore.kernel.org/all/20250827042042.6786-1-jie.gan@oss.qualcomm.com/
Changes in V2:
1. Refactoring the code based on James's comment for optimization.
Link to V1 - https://lore.kernel.org/all/20250826070150.5603-1-jie.gan@oss.qualcomm.com/
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Tao Zhang (3):
coresight: tpda: add sysfs nodes for tpda cross-trigger configuration
coresight: tpda: add logic to configure TPDA_SYNCR register
coresight: tpda: add sysfs node to flush specific port
.../ABI/testing/sysfs-bus-coresight-devices-tpda | 50 ++++++
drivers/hwtracing/coresight/coresight-tpda.c | 194 ++++++++++++++++++++-
drivers/hwtracing/coresight/coresight-tpda.h | 75 +++++++-
3 files changed, 312 insertions(+), 7 deletions(-)
---
base-commit: 12b95d29eb979e5c4f4f31bb05817bc935c52050
change-id: 20251219-add_sysfs_nodes_to_configure_tpda-f54636512817
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration 2025-12-19 10:04 [PATCH v5 0/3] add sysfs nodes to configure TPDA's registers Jie Gan @ 2025-12-19 10:04 ` Jie Gan 2025-12-19 10:22 ` Suzuki K Poulose 2025-12-19 10:04 ` [PATCH v5 2/3] coresight: tpda: add logic to configure TPDA_SYNCR register Jie Gan 2025-12-19 10:04 ` [PATCH v5 3/3] coresight: tpda: add sysfs node to flush specific port Jie Gan 2 siblings, 1 reply; 11+ messages in thread From: Jie Gan @ 2025-12-19 10:04 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Jie Gan, Tao Zhang From: Tao Zhang <tao.zhang@oss.qualcomm.com> Introduce sysfs nodes to configure cross-trigger parameters for TPDA. These registers define the characteristics of cross-trigger packets, including generation frequency and flag values. Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> Reviewed-by: James Clark <james.clark@linaro.org> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> --- .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 +++++++ drivers/hwtracing/coresight/coresight-tpda.c | 138 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpda.h | 69 ++++++++++- 3 files changed, 243 insertions(+), 7 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda new file mode 100644 index 000000000000..a7855922328e --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -0,0 +1,43 @@ +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/trig_async_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> +Description: + (RW) Enable/disable cross trigger synchronization sequence interface. + +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/trig_flag_ts_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> +Description: + (RW) Enable/disable cross trigger FLAG packet request interface. + +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/trig_freq_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> +Description: + (RW) Enable/disable cross trigger FREQ packet request interface. + +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/freq_ts_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> +Description: + (RW) Enable/disable the timestamp for all FREQ packets. + +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/global_flush_req +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> +Description: + (RW) Set global (all ports) flush request bit. The bit remains set until a + global flush request sequence completes. + +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/cmbchan_mode +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> +Description: + (RW) Configure the CMB/MCMB channel mode for all enabled ports. + Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 3a3825d27f86..d25a8bcfb3d4 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -137,12 +137,32 @@ static int tpda_get_element_size(struct tpda_drvdata *drvdata, /* Settings pre enabling port control register */ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) { - u32 val; + u32 val = 0; - val = readl_relaxed(drvdata->base + TPDA_CR); - val &= ~TPDA_CR_ATID; val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); + if (drvdata->trig_async) + val |= TPDA_CR_SRIE; + + if (drvdata->trig_flag_ts) + val |= TPDA_CR_FLRIE; + + if (drvdata->trig_freq) + val |= TPDA_CR_FRIE; + + if (drvdata->freq_ts) + val |= TPDA_CR_FREQTS; + + if (drvdata->cmbchan_mode) + val |= TPDA_CR_CMBCHANMODE; + writel_relaxed(val, drvdata->base + TPDA_CR); + + /* + * If FLRIE bit is set, set the master and channel + * id as zero + */ + if (drvdata->trig_flag_ts) + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); } static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) @@ -258,6 +278,116 @@ static const struct coresight_ops tpda_cs_ops = { .link_ops = &tpda_link_ops, }; +/* Read cross-trigger register member */ +static ssize_t tpda_trig_sysfs_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_trig_sysfs_attribute *tpda_attr = + container_of(attr, struct tpda_trig_sysfs_attribute, attr); + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + guard(spinlock)(&drvdata->spinlock); + switch (tpda_attr->mem) { + case FLREQ: + if (!drvdata->csdev->refcnt) + return -EINVAL; + + val = readl_relaxed(drvdata->base + TPDA_CR); + /* read global flush request bit only */ + val &= TPDA_CR_FLREQ; + return sysfs_emit(buf, "%lu\n", val); + case FREQTS: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); + case FRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq); + case FLRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts); + case SRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); + case CMBCHANMODE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode); + + } + return -EINVAL; +} + +static ssize_t tpda_trig_sysfs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_trig_sysfs_attribute *tpda_attr = + container_of(attr, struct tpda_trig_sysfs_attribute, attr); + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t ret = -EINVAL; + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return ret; + + guard(spinlock)(&drvdata->spinlock); + switch (tpda_attr->mem) { + case FLREQ: + if (!drvdata->csdev->refcnt || !val) + return ret; + + val = readl_relaxed(drvdata->base + TPDA_CR); + /* set global flush request bit */ + val |= TPDA_CR_FLREQ; + CS_UNLOCK(drvdata->base); + writel_relaxed(val, drvdata->base + TPDA_CR); + CS_LOCK(drvdata->base); + ret = size; + break; + case FREQTS: + drvdata->freq_ts = !!val; + ret = size; + break; + case FRIE: + drvdata->trig_freq = !!val; + ret = size; + break; + case FLRIE: + drvdata->trig_flag_ts = !!val; + ret = size; + break; + case SRIE: + drvdata->trig_async = !!val; + ret = size; + break; + case CMBCHANMODE: + drvdata->cmbchan_mode = !!val; + ret = size; + break; + default: + break; + } + + return ret; +} + +static struct attribute *tpda_global_cr_attrs[] = { + tpda_trig_sysfs_rw(global_flush_req, FLREQ), + tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), + tpda_trig_sysfs_rw(trig_freq_enable, FRIE), + tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), + tpda_trig_sysfs_rw(trig_async_enable, SRIE), + tpda_trig_sysfs_rw(cmbchan_mode, CMBCHANMODE), + NULL, +}; + +static struct attribute_group tpda_global_cr_attr_grp = { + .attrs = tpda_global_cr_attrs, + .name = "global_cr", +}; + +static const struct attribute_group *tpda_attr_grps[] = { + &tpda_global_cr_attr_grp, + NULL, +}; + static int tpda_init_default_data(struct tpda_drvdata *drvdata) { int atid; @@ -273,6 +403,7 @@ static int tpda_init_default_data(struct tpda_drvdata *drvdata) return atid; drvdata->atid = atid; + drvdata->freq_ts = true; return 0; } @@ -316,6 +447,7 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id) desc.ops = &tpda_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; + desc.groups = tpda_attr_grps; desc.access = CSDEV_ACCESS_IOMEM(base); drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index c6af3d2da3ef..8a075cfbc3cc 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CORESIGHT_CORESIGHT_TPDA_H @@ -8,6 +8,30 @@ #define TPDA_CR (0x000) #define TPDA_Pn_CR(n) (0x004 + (n * 4)) +#define TPDA_FPID_CR (0x084) + +/* Cross trigger Global (all ports) flush request bit */ +#define TPDA_CR_FLREQ BIT(0) +/* Cross trigger FREQ packets timestamp bit */ +#define TPDA_CR_FREQTS BIT(2) +/* Cross trigger FREQ packet request bit */ +#define TPDA_CR_FRIE BIT(3) +/* Cross trigger FLAG packet request interface bit */ +#define TPDA_CR_FLRIE BIT(4) +/* Cross trigger synchronization bit */ +#define TPDA_CR_SRIE BIT(5) +/* Bits 6 ~ 12 is for atid value */ +#define TPDA_CR_ATID GENMASK(12, 6) +/* Bits 13 ~ 19 is for mid value */ +/* Assign a unique master ID to identify the TPDA device */ +#define TPDA_CR_MID GENMASK(19, 13) +/* + * Channel mode bit of the packetization of CMB/MCB traffic + * 0 - raw channel mapping mode + * 1 - channel pair marking mode + */ +#define TPDA_CR_CMBCHANMODE BIT(20) + /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) /* Aggregator port CMB data set element size bit */ @@ -17,9 +41,6 @@ #define TPDA_MAX_INPORTS 32 -/* Bits 6 ~ 12 is for atid value */ -#define TPDA_CR_ATID GENMASK(12, 6) - /** * struct tpda_drvdata - specifics associated to an TPDA component * @base: memory mapped base address for this component. @@ -29,6 +50,11 @@ * @enable: enable status of the component. * @dsb_esize Record the DSB element size. * @cmb_esize Record the CMB element size. + * @trig_async: Enable/disable cross trigger synchronization sequence interface. + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interface. + * @trig_freq: Enable/disable cross trigger FREQ packet request interface. + * @freq_ts: Enable/disable the timestamp for all FREQ packets. + * @cmbchan_mode: Configure the CMB/MCMB channel mode. */ struct tpda_drvdata { void __iomem *base; @@ -38,6 +64,41 @@ struct tpda_drvdata { u8 atid; u32 dsb_esize; u32 cmb_esize; + bool trig_async; + bool trig_flag_ts; + bool trig_freq; + bool freq_ts; + bool cmbchan_mode; +}; + +/* Enumerate members of global control register(cr) */ +enum tpda_cr_mem { + FLREQ, + FREQTS, + FRIE, + FLRIE, + SRIE, + CMBCHANMODE +}; + +/** + * struct tpda_trig_sysfs_attribute - Record the member variables of cross + * trigger register that need to be operated by sysfs file + * @attr: The device attribute + * @mem: The member in the control register data structure + */ +struct tpda_trig_sysfs_attribute { + struct device_attribute attr; + enum tpda_cr_mem mem; }; +#define tpda_trig_sysfs_rw(name, mem) \ + (&((struct tpda_trig_sysfs_attribute[]) { \ + { \ + __ATTR(name, 0644, tpda_trig_sysfs_show, \ + tpda_trig_sysfs_store), \ + mem, \ + } \ + })[0].attr.attr) + #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration 2025-12-19 10:04 ` [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration Jie Gan @ 2025-12-19 10:22 ` Suzuki K Poulose 2025-12-19 12:19 ` Jie Gan 0 siblings, 1 reply; 11+ messages in thread From: Suzuki K Poulose @ 2025-12-19 10:22 UTC (permalink / raw) To: Jie Gan, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Tao Zhang On 19/12/2025 10:04, Jie Gan wrote: > From: Tao Zhang <tao.zhang@oss.qualcomm.com> > > Introduce sysfs nodes to configure cross-trigger parameters for TPDA. > These registers define the characteristics of cross-trigger packets, > including generation frequency and flag values. > > Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> > Reviewed-by: James Clark <james.clark@linaro.org> > Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 +++++++ > drivers/hwtracing/coresight/coresight-tpda.c | 138 ++++++++++++++++++++- > drivers/hwtracing/coresight/coresight-tpda.h | 69 ++++++++++- > 3 files changed, 243 insertions(+), 7 deletions(-) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > new file mode 100644 > index 000000000000..a7855922328e > --- /dev/null > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > @@ -0,0 +1,43 @@ > +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/trig_async_enable > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> > +Description: > + (RW) Enable/disable cross trigger synchronization sequence interface. > + > +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/trig_flag_ts_enable > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> > +Description: > + (RW) Enable/disable cross trigger FLAG packet request interface. > + > +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/trig_freq_enable > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> > +Description: > + (RW) Enable/disable cross trigger FREQ packet request interface. > + > +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/freq_ts_enable > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> > +Description: > + (RW) Enable/disable the timestamp for all FREQ packets. > + > +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/global_flush_req > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> > +Description: > + (RW) Set global (all ports) flush request bit. The bit remains set until a > + global flush request sequence completes. > + > +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/cmbchan_mode > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> > +Description: > + (RW) Configure the CMB/MCMB channel mode for all enabled ports. > + Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode. > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 3a3825d27f86..d25a8bcfb3d4 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -137,12 +137,32 @@ static int tpda_get_element_size(struct tpda_drvdata *drvdata, > /* Settings pre enabling port control register */ > static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) > { > - u32 val; > + u32 val = 0; > > - val = readl_relaxed(drvdata->base + TPDA_CR); > - val &= ~TPDA_CR_ATID; > val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); > + if (drvdata->trig_async) > + val |= TPDA_CR_SRIE; > + > + if (drvdata->trig_flag_ts) > + val |= TPDA_CR_FLRIE; > + > + if (drvdata->trig_freq) > + val |= TPDA_CR_FRIE; > + > + if (drvdata->freq_ts) > + val |= TPDA_CR_FREQTS; > + > + if (drvdata->cmbchan_mode) > + val |= TPDA_CR_CMBCHANMODE; > + > writel_relaxed(val, drvdata->base + TPDA_CR); > + > + /* > + * If FLRIE bit is set, set the master and channel > + * id as zero > + */ > + if (drvdata->trig_flag_ts) > + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); > } > > static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) > @@ -258,6 +278,116 @@ static const struct coresight_ops tpda_cs_ops = { > .link_ops = &tpda_link_ops, > }; > > +/* Read cross-trigger register member */ > +static ssize_t tpda_trig_sysfs_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_trig_sysfs_attribute *tpda_attr = > + container_of(attr, struct tpda_trig_sysfs_attribute, attr); > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + guard(spinlock)(&drvdata->spinlock); > + switch (tpda_attr->mem) { > + case FLREQ: > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + val = readl_relaxed(drvdata->base + TPDA_CR); > + /* read global flush request bit only */ > + val &= TPDA_CR_FLREQ; > + return sysfs_emit(buf, "%lu\n", val); > + case FREQTS: > + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); > + case FRIE: > + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq); > + case FLRIE: > + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts); > + case SRIE: > + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); > + case CMBCHANMODE: > + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode); > + > + } > + return -EINVAL; > +} > + > +static ssize_t tpda_trig_sysfs_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_trig_sysfs_attribute *tpda_attr = > + container_of(attr, struct tpda_trig_sysfs_attribute, attr); > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + ssize_t ret = -EINVAL; + unsigned long val; > + > + if (kstrtoul(buf, 0, &val)) > + return ret; return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + switch (tpda_attr->mem) { > + case FLREQ: > + if (!drvdata->csdev->refcnt || !val) > + return ret; return -EINVAL; > + > + val = readl_relaxed(drvdata->base + TPDA_CR); CS_UNLOCK before readl ? I didn't mean the global_flush_req to be unified with the rest. Obviously it has different access semantics. > + /* set global flush request bit */ > + val |= TPDA_CR_FLREQ; > + CS_UNLOCK(drvdata->base); > + writel_relaxed(val, drvdata->base + TPDA_CR); > + CS_LOCK(drvdata->base); > + ret = size; Please remove this from all the cases and explicitly return -EINVAL in the error cases. > + break; > + case FREQTS: > + drvdata->freq_ts = !!val; > + ret = size; > + break; > + case FRIE: > + drvdata->trig_freq = !!val; > + ret = size; > + break; > + case FLRIE: > + drvdata->trig_flag_ts = !!val; > + ret = size; > + break; > + case SRIE: > + drvdata->trig_async = !!val; > + ret = size; > + break; > + case CMBCHANMODE: > + drvdata->cmbchan_mode = !!val; > + ret = size; > + break; > + default: return -EINVAL; > + break; > + } > + > + return ret; return size; > +} > + > +static struct attribute *tpda_global_cr_attrs[] = { > + tpda_trig_sysfs_rw(global_flush_req, FLREQ), > + tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), > + tpda_trig_sysfs_rw(trig_freq_enable, FRIE), > + tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), > + tpda_trig_sysfs_rw(trig_async_enable, SRIE), > + tpda_trig_sysfs_rw(cmbchan_mode, CMBCHANMODE), > + NULL, > +}; > + > +static struct attribute_group tpda_global_cr_attr_grp = { > + .attrs = tpda_global_cr_attrs, > + .name = "global_cr", > +}; > + > +static const struct attribute_group *tpda_attr_grps[] = { > + &tpda_global_cr_attr_grp, > + NULL, > +}; > + > static int tpda_init_default_data(struct tpda_drvdata *drvdata) > { > int atid; > @@ -273,6 +403,7 @@ static int tpda_init_default_data(struct tpda_drvdata *drvdata) > return atid; > > drvdata->atid = atid; > + drvdata->freq_ts = true; > return 0; > } > > @@ -316,6 +447,7 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id) > desc.ops = &tpda_cs_ops; > desc.pdata = adev->dev.platform_data; > desc.dev = &adev->dev; > + desc.groups = tpda_attr_grps; > desc.access = CSDEV_ACCESS_IOMEM(base); > drvdata->csdev = coresight_register(&desc); > if (IS_ERR(drvdata->csdev)) > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index c6af3d2da3ef..8a075cfbc3cc 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #ifndef _CORESIGHT_CORESIGHT_TPDA_H > @@ -8,6 +8,30 @@ > > #define TPDA_CR (0x000) > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > +#define TPDA_FPID_CR (0x084) > + > +/* Cross trigger Global (all ports) flush request bit */ > +#define TPDA_CR_FLREQ BIT(0) > +/* Cross trigger FREQ packets timestamp bit */ > +#define TPDA_CR_FREQTS BIT(2) > +/* Cross trigger FREQ packet request bit */ > +#define TPDA_CR_FRIE BIT(3) > +/* Cross trigger FLAG packet request interface bit */ > +#define TPDA_CR_FLRIE BIT(4) > +/* Cross trigger synchronization bit */ > +#define TPDA_CR_SRIE BIT(5) > +/* Bits 6 ~ 12 is for atid value */ > +#define TPDA_CR_ATID GENMASK(12, 6) > +/* Bits 13 ~ 19 is for mid value */ > +/* Assign a unique master ID to identify the TPDA device */ > +#define TPDA_CR_MID GENMASK(19, 13) Where do we use this ? Does this need to be preserved ? Is this programmable ? Suzuki > +/* > + * Channel mode bit of the packetization of CMB/MCB traffic > + * 0 - raw channel mapping mode > + * 1 - channel pair marking mode > + */ > +#define TPDA_CR_CMBCHANMODE BIT(20) > + > /* Aggregator port enable bit */ > #define TPDA_Pn_CR_ENA BIT(0) > /* Aggregator port CMB data set element size bit */ > @@ -17,9 +41,6 @@ > > #define TPDA_MAX_INPORTS 32 > > -/* Bits 6 ~ 12 is for atid value */ > -#define TPDA_CR_ATID GENMASK(12, 6) > - > /** > * struct tpda_drvdata - specifics associated to an TPDA component > * @base: memory mapped base address for this component. > @@ -29,6 +50,11 @@ > * @enable: enable status of the component. > * @dsb_esize Record the DSB element size. > * @cmb_esize Record the CMB element size. > + * @trig_async: Enable/disable cross trigger synchronization sequence interface. > + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interface. > + * @trig_freq: Enable/disable cross trigger FREQ packet request interface. > + * @freq_ts: Enable/disable the timestamp for all FREQ packets. > + * @cmbchan_mode: Configure the CMB/MCMB channel mode. > */ > struct tpda_drvdata { > void __iomem *base; > @@ -38,6 +64,41 @@ struct tpda_drvdata { > u8 atid; > u32 dsb_esize; > u32 cmb_esize; > + bool trig_async; > + bool trig_flag_ts; > + bool trig_freq; > + bool freq_ts; > + bool cmbchan_mode; > +}; > + > +/* Enumerate members of global control register(cr) */ > +enum tpda_cr_mem { > + FLREQ, > + FREQTS, > + FRIE, > + FLRIE, > + SRIE, > + CMBCHANMODE > +}; > + > +/** > + * struct tpda_trig_sysfs_attribute - Record the member variables of cross > + * trigger register that need to be operated by sysfs file > + * @attr: The device attribute > + * @mem: The member in the control register data structure > + */ > +struct tpda_trig_sysfs_attribute { > + struct device_attribute attr; > + enum tpda_cr_mem mem; > }; > > +#define tpda_trig_sysfs_rw(name, mem) \ > + (&((struct tpda_trig_sysfs_attribute[]) { \ > + { \ > + __ATTR(name, 0644, tpda_trig_sysfs_show, \ > + tpda_trig_sysfs_store), \ > + mem, \ > + } \ > + })[0].attr.attr) > + > #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration 2025-12-19 10:22 ` Suzuki K Poulose @ 2025-12-19 12:19 ` Jie Gan 0 siblings, 0 replies; 11+ messages in thread From: Jie Gan @ 2025-12-19 12:19 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Tao Zhang On 12/19/2025 6:22 PM, Suzuki K Poulose wrote: > On 19/12/2025 10:04, Jie Gan wrote: >> From: Tao Zhang <tao.zhang@oss.qualcomm.com> >> >> Introduce sysfs nodes to configure cross-trigger parameters for TPDA. >> These registers define the characteristics of cross-trigger packets, >> including generation frequency and flag values. >> >> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> >> Reviewed-by: James Clark <james.clark@linaro.org> >> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> >> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> >> --- >> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 +++++++ >> drivers/hwtracing/coresight/coresight-tpda.c | 138 +++++++++++ >> +++++++++- >> drivers/hwtracing/coresight/coresight-tpda.h | 69 ++++++++++- >> 3 files changed, 243 insertions(+), 7 deletions(-) >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> new file mode 100644 >> index 000000000000..a7855922328e >> --- /dev/null >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> @@ -0,0 +1,43 @@ >> +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/ >> trig_async_enable >> +Date: December 2025 >> +KernelVersion: 6.19 >> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang >> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> >> +Description: >> + (RW) Enable/disable cross trigger synchronization sequence >> interface. >> + >> +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/ >> trig_flag_ts_enable >> +Date: December 2025 >> +KernelVersion: 6.19 >> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang >> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> >> +Description: >> + (RW) Enable/disable cross trigger FLAG packet request interface. >> + >> +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/ >> trig_freq_enable >> +Date: December 2025 >> +KernelVersion: 6.19 >> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang >> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> >> +Description: >> + (RW) Enable/disable cross trigger FREQ packet request interface. >> + >> +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/ >> freq_ts_enable >> +Date: December 2025 >> +KernelVersion: 6.19 >> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang >> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> >> +Description: >> + (RW) Enable/disable the timestamp for all FREQ packets. >> + >> +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/ >> global_flush_req >> +Date: December 2025 >> +KernelVersion: 6.19 >> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang >> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> >> +Description: >> + (RW) Set global (all ports) flush request bit. The bit >> remains set until a >> + global flush request sequence completes. >> + >> +What: /sys/bus/coresight/devices/<tpda-name>/global_cr/ >> cmbchan_mode >> +Date: December 2025 >> +KernelVersion: 6.19 >> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang >> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> >> +Description: >> + (RW) Configure the CMB/MCMB channel mode for all enabled ports. >> + Value 0 means raw channel mapping mode. Value 1 means channel >> pair marking mode. >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >> hwtracing/coresight/coresight-tpda.c >> index 3a3825d27f86..d25a8bcfb3d4 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.c >> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >> @@ -137,12 +137,32 @@ static int tpda_get_element_size(struct >> tpda_drvdata *drvdata, >> /* Settings pre enabling port control register */ >> static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) >> { >> - u32 val; >> + u32 val = 0; >> - val = readl_relaxed(drvdata->base + TPDA_CR); >> - val &= ~TPDA_CR_ATID; >> val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); >> + if (drvdata->trig_async) >> + val |= TPDA_CR_SRIE; >> + >> + if (drvdata->trig_flag_ts) >> + val |= TPDA_CR_FLRIE; >> + >> + if (drvdata->trig_freq) >> + val |= TPDA_CR_FRIE; >> + >> + if (drvdata->freq_ts) >> + val |= TPDA_CR_FREQTS; >> + >> + if (drvdata->cmbchan_mode) >> + val |= TPDA_CR_CMBCHANMODE; >> + >> writel_relaxed(val, drvdata->base + TPDA_CR); >> + >> + /* >> + * If FLRIE bit is set, set the master and channel >> + * id as zero >> + */ >> + if (drvdata->trig_flag_ts) >> + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); >> } >> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) >> @@ -258,6 +278,116 @@ static const struct coresight_ops tpda_cs_ops = { >> .link_ops = &tpda_link_ops, >> }; >> +/* Read cross-trigger register member */ >> +static ssize_t tpda_trig_sysfs_show(struct device *dev, >> + struct device_attribute *attr, >> + char *buf) >> +{ >> + struct tpda_trig_sysfs_attribute *tpda_attr = >> + container_of(attr, struct tpda_trig_sysfs_attribute, attr); >> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + unsigned long val; >> + >> + guard(spinlock)(&drvdata->spinlock); >> + switch (tpda_attr->mem) { >> + case FLREQ: >> + if (!drvdata->csdev->refcnt) >> + return -EINVAL; >> + >> + val = readl_relaxed(drvdata->base + TPDA_CR); >> + /* read global flush request bit only */ >> + val &= TPDA_CR_FLREQ; >> + return sysfs_emit(buf, "%lu\n", val); >> + case FREQTS: >> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); >> + case FRIE: >> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata- >> >trig_freq); >> + case FLRIE: >> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata- >> >trig_flag_ts); >> + case SRIE: >> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata- >> >trig_async); >> + case CMBCHANMODE: >> + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata- >> >cmbchan_mode); >> + >> + } >> + return -EINVAL; >> +} >> + >> +static ssize_t tpda_trig_sysfs_store(struct device *dev, >> + struct device_attribute *attr, >> + const char *buf, >> + size_t size) >> +{ >> + struct tpda_trig_sysfs_attribute *tpda_attr = >> + container_of(attr, struct tpda_trig_sysfs_attribute, attr); >> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + ssize_t ret = -EINVAL; > + unsigned long val; >> + >> + if (kstrtoul(buf, 0, &val)) >> + return ret; > > return -EINVAL; > >> + >> + guard(spinlock)(&drvdata->spinlock); >> + switch (tpda_attr->mem) { >> + case FLREQ: >> + if (!drvdata->csdev->refcnt || !val) >> + return ret; > return -EINVAL; > >> + >> + val = readl_relaxed(drvdata->base + TPDA_CR); > > CS_UNLOCK before readl ? I didn't mean the global_flush_req to be > unified with the rest. Obviously it has different access semantics. We dont need CS_UNLOCK for reading a register. The global_flush_req is supposing access when the tpda is enabled. I will put it in a separate patch with detail description. > > >> + /* set global flush request bit */ >> + val |= TPDA_CR_FLREQ; >> + CS_UNLOCK(drvdata->base); >> + writel_relaxed(val, drvdata->base + TPDA_CR); >> + CS_LOCK(drvdata->base); >> + ret = size; > > Please remove this from all the cases and explicitly return -EINVAL in > the error cases. Will fix it. > >> + break; >> + case FREQTS: >> + drvdata->freq_ts = !!val; >> + ret = size; >> + break; >> + case FRIE: >> + drvdata->trig_freq = !!val; >> + ret = size; >> + break; >> + case FLRIE: >> + drvdata->trig_flag_ts = !!val; >> + ret = size; >> + break; >> + case SRIE: >> + drvdata->trig_async = !!val; >> + ret = size; >> + break; >> + case CMBCHANMODE: >> + drvdata->cmbchan_mode = !!val; >> + ret = size; >> + break; >> + default: > return -EINVAL; > >> + break; >> + } >> + > > >> + return ret; > > return size; > >> +} >> + >> +static struct attribute *tpda_global_cr_attrs[] = { >> + tpda_trig_sysfs_rw(global_flush_req, FLREQ), >> + tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), >> + tpda_trig_sysfs_rw(trig_freq_enable, FRIE), >> + tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), >> + tpda_trig_sysfs_rw(trig_async_enable, SRIE), >> + tpda_trig_sysfs_rw(cmbchan_mode, CMBCHANMODE), >> + NULL, >> +}; >> + >> +static struct attribute_group tpda_global_cr_attr_grp = { >> + .attrs = tpda_global_cr_attrs, >> + .name = "global_cr", >> +}; >> + >> +static const struct attribute_group *tpda_attr_grps[] = { >> + &tpda_global_cr_attr_grp, >> + NULL, >> +}; >> + >> static int tpda_init_default_data(struct tpda_drvdata *drvdata) >> { >> int atid; >> @@ -273,6 +403,7 @@ static int tpda_init_default_data(struct >> tpda_drvdata *drvdata) >> return atid; >> drvdata->atid = atid; >> + drvdata->freq_ts = true; >> return 0; >> } >> @@ -316,6 +447,7 @@ static int tpda_probe(struct amba_device *adev, >> const struct amba_id *id) >> desc.ops = &tpda_cs_ops; >> desc.pdata = adev->dev.platform_data; >> desc.dev = &adev->dev; >> + desc.groups = tpda_attr_grps; >> desc.access = CSDEV_ACCESS_IOMEM(base); >> drvdata->csdev = coresight_register(&desc); >> if (IS_ERR(drvdata->csdev)) >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >> hwtracing/coresight/coresight-tpda.h >> index c6af3d2da3ef..8a075cfbc3cc 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.h >> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >> @@ -1,6 +1,6 @@ >> /* SPDX-License-Identifier: GPL-2.0 */ >> /* >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights >> reserved. >> + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All >> rights reserved. >> */ >> #ifndef _CORESIGHT_CORESIGHT_TPDA_H >> @@ -8,6 +8,30 @@ >> #define TPDA_CR (0x000) >> #define TPDA_Pn_CR(n) (0x004 + (n * 4)) >> +#define TPDA_FPID_CR (0x084) >> + >> +/* Cross trigger Global (all ports) flush request bit */ >> +#define TPDA_CR_FLREQ BIT(0) >> +/* Cross trigger FREQ packets timestamp bit */ >> +#define TPDA_CR_FREQTS BIT(2) >> +/* Cross trigger FREQ packet request bit */ >> +#define TPDA_CR_FRIE BIT(3) >> +/* Cross trigger FLAG packet request interface bit */ >> +#define TPDA_CR_FLRIE BIT(4) >> +/* Cross trigger synchronization bit */ >> +#define TPDA_CR_SRIE BIT(5) >> +/* Bits 6 ~ 12 is for atid value */ >> +#define TPDA_CR_ATID GENMASK(12, 6) >> +/* Bits 13 ~ 19 is for mid value */ >> +/* Assign a unique master ID to identify the TPDA device */ >> +#define TPDA_CR_MID GENMASK(19, 13) > > Where do we use this ? Does this need to be preserved ? > Is this programmable ? > We havent usage of this field. I will remove it in next version. Thanks, Jie > Suzuki > >> +/* >> + * Channel mode bit of the packetization of CMB/MCB traffic >> + * 0 - raw channel mapping mode >> + * 1 - channel pair marking mode >> + */ >> +#define TPDA_CR_CMBCHANMODE BIT(20) >> + >> /* Aggregator port enable bit */ >> #define TPDA_Pn_CR_ENA BIT(0) >> /* Aggregator port CMB data set element size bit */ >> @@ -17,9 +41,6 @@ >> #define TPDA_MAX_INPORTS 32 >> -/* Bits 6 ~ 12 is for atid value */ >> -#define TPDA_CR_ATID GENMASK(12, 6) >> - >> /** >> * struct tpda_drvdata - specifics associated to an TPDA component >> * @base: memory mapped base address for this component. >> @@ -29,6 +50,11 @@ >> * @enable: enable status of the component. >> * @dsb_esize Record the DSB element size. >> * @cmb_esize Record the CMB element size. >> + * @trig_async: Enable/disable cross trigger synchronization >> sequence interface. >> + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request >> interface. >> + * @trig_freq: Enable/disable cross trigger FREQ packet request >> interface. >> + * @freq_ts: Enable/disable the timestamp for all FREQ packets. >> + * @cmbchan_mode: Configure the CMB/MCMB channel mode. >> */ >> struct tpda_drvdata { >> void __iomem *base; >> @@ -38,6 +64,41 @@ struct tpda_drvdata { >> u8 atid; >> u32 dsb_esize; >> u32 cmb_esize; >> + bool trig_async; >> + bool trig_flag_ts; >> + bool trig_freq; >> + bool freq_ts; >> + bool cmbchan_mode; >> +}; >> + >> +/* Enumerate members of global control register(cr) */ >> +enum tpda_cr_mem { >> + FLREQ, >> + FREQTS, >> + FRIE, >> + FLRIE, >> + SRIE, >> + CMBCHANMODE >> +}; >> + >> +/** >> + * struct tpda_trig_sysfs_attribute - Record the member variables of >> cross >> + * trigger register that need to be operated by sysfs file >> + * @attr: The device attribute >> + * @mem: The member in the control register data structure >> + */ >> +struct tpda_trig_sysfs_attribute { >> + struct device_attribute attr; >> + enum tpda_cr_mem mem; >> }; >> +#define tpda_trig_sysfs_rw(name, mem) \ >> + (&((struct tpda_trig_sysfs_attribute[]) { \ >> + { \ >> + __ATTR(name, 0644, tpda_trig_sysfs_show, \ >> + tpda_trig_sysfs_store), \ >> + mem, \ >> + } \ >> + })[0].attr.attr) >> + >> #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ >> > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 2/3] coresight: tpda: add logic to configure TPDA_SYNCR register 2025-12-19 10:04 [PATCH v5 0/3] add sysfs nodes to configure TPDA's registers Jie Gan 2025-12-19 10:04 ` [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration Jie Gan @ 2025-12-19 10:04 ` Jie Gan 2025-12-19 10:24 ` Suzuki K Poulose 2025-12-19 10:04 ` [PATCH v5 3/3] coresight: tpda: add sysfs node to flush specific port Jie Gan 2 siblings, 1 reply; 11+ messages in thread From: Jie Gan @ 2025-12-19 10:04 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Jie Gan, Tao Zhang From: Tao Zhang <tao.zhang@oss.qualcomm.com> The TPDA_SYNC counter tracks the number of bytes transferred from the aggregator. When this count reaches the value programmed in the TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace tools to accurately parse each valid packet. Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> Reviewed-by: James Clark <james.clark@linaro.org> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> --- drivers/hwtracing/coresight/coresight-tpda.c | 7 +++++++ drivers/hwtracing/coresight/coresight-tpda.h | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index d25a8bcfb3d4..d378ff8ad77d 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -163,6 +163,13 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) */ if (drvdata->trig_flag_ts) writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); + + val = readl_relaxed(drvdata->base + TPDA_SYNCR); + /* Reset the mode ctrl */ + val &= ~TPDA_SYNCR_MODE_CTRL; + /* Program the counter value for TPDA_SYNCR */ + val |= TPDA_SYNCR_COUNTER_MASK; + writel_relaxed(val, drvdata->base + TPDA_SYNCR); } static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 8a075cfbc3cc..97e2729c15c9 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -9,6 +9,7 @@ #define TPDA_CR (0x000) #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) +#define TPDA_SYNCR (0x08C) /* Cross trigger Global (all ports) flush request bit */ #define TPDA_CR_FLREQ BIT(0) @@ -38,6 +39,10 @@ #define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) /* Aggregator port DSB data set element size bit */ #define TPDA_Pn_CR_DSBSIZE BIT(8) +/* TPDA_SYNCR mode control bit */ +#define TPDA_SYNCR_MODE_CTRL BIT(12) +/* TPDA_SYNCR counter mask */ +#define TPDA_SYNCR_COUNTER_MASK GENMASK(11, 0) #define TPDA_MAX_INPORTS 32 -- 2.34.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/3] coresight: tpda: add logic to configure TPDA_SYNCR register 2025-12-19 10:04 ` [PATCH v5 2/3] coresight: tpda: add logic to configure TPDA_SYNCR register Jie Gan @ 2025-12-19 10:24 ` Suzuki K Poulose 2025-12-19 12:31 ` Jie Gan 0 siblings, 1 reply; 11+ messages in thread From: Suzuki K Poulose @ 2025-12-19 10:24 UTC (permalink / raw) To: Jie Gan, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Tao Zhang On 19/12/2025 10:04, Jie Gan wrote: > From: Tao Zhang <tao.zhang@oss.qualcomm.com> > > The TPDA_SYNC counter tracks the number of bytes transferred from the > aggregator. When this count reaches the value programmed in the > TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace > tools to accurately parse each valid packet. > > Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> > Reviewed-by: James Clark <james.clark@linaro.org> > Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 7 +++++++ > drivers/hwtracing/coresight/coresight-tpda.h | 5 +++++ > 2 files changed, 12 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index d25a8bcfb3d4..d378ff8ad77d 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -163,6 +163,13 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) > */ > if (drvdata->trig_flag_ts) > writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); > + > + val = readl_relaxed(drvdata->base + TPDA_SYNCR); > + /* Reset the mode ctrl */ > + val &= ~TPDA_SYNCR_MODE_CTRL; > + /* Program the counter value for TPDA_SYNCR */ > + val |= TPDA_SYNCR_COUNTER_MASK; Do we plan to change this value via sysfs ? If not whats the point of clearing the field. Why not simply set it (as it is all 1s anyways). > + writel_relaxed(val, drvdata->base + TPDA_SYNCR); > } > > static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index 8a075cfbc3cc..97e2729c15c9 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -9,6 +9,7 @@ > #define TPDA_CR (0x000) > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > #define TPDA_FPID_CR (0x084) > +#define TPDA_SYNCR (0x08C) > > /* Cross trigger Global (all ports) flush request bit */ > #define TPDA_CR_FLREQ BIT(0) > @@ -38,6 +39,10 @@ > #define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) > /* Aggregator port DSB data set element size bit */ > #define TPDA_Pn_CR_DSBSIZE BIT(8) Newline to separate the defintions of different registers, please. > +/* TPDA_SYNCR mode control bit */ > +#define TPDA_SYNCR_MODE_CTRL BIT(12) > +/* TPDA_SYNCR counter mask */ > +#define TPDA_SYNCR_COUNTER_MASK GENMASK(11, 0) > > #define TPDA_MAX_INPORTS 32 > Suzuki > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/3] coresight: tpda: add logic to configure TPDA_SYNCR register 2025-12-19 10:24 ` Suzuki K Poulose @ 2025-12-19 12:31 ` Jie Gan 2025-12-19 13:00 ` Jie Gan 0 siblings, 1 reply; 11+ messages in thread From: Jie Gan @ 2025-12-19 12:31 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Tao Zhang On 12/19/2025 6:24 PM, Suzuki K Poulose wrote: > On 19/12/2025 10:04, Jie Gan wrote: >> From: Tao Zhang <tao.zhang@oss.qualcomm.com> >> >> The TPDA_SYNC counter tracks the number of bytes transferred from the >> aggregator. When this count reaches the value programmed in the >> TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace >> tools to accurately parse each valid packet. >> >> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> >> Reviewed-by: James Clark <james.clark@linaro.org> >> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> >> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> >> --- >> drivers/hwtracing/coresight/coresight-tpda.c | 7 +++++++ >> drivers/hwtracing/coresight/coresight-tpda.h | 5 +++++ >> 2 files changed, 12 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >> hwtracing/coresight/coresight-tpda.c >> index d25a8bcfb3d4..d378ff8ad77d 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.c >> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >> @@ -163,6 +163,13 @@ static void tpda_enable_pre_port(struct >> tpda_drvdata *drvdata) >> */ >> if (drvdata->trig_flag_ts) >> writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); >> + >> + val = readl_relaxed(drvdata->base + TPDA_SYNCR); >> + /* Reset the mode ctrl */ >> + val &= ~TPDA_SYNCR_MODE_CTRL; >> + /* Program the counter value for TPDA_SYNCR */ >> + val |= TPDA_SYNCR_COUNTER_MASK; > > Do we plan to change this value via sysfs ? If not whats the point of > clearing the field. Why not simply set it (as it is all 1s anyways). We configure the value only once during enablement and do not intend to modify it through sysfs. The mode_ctrl is reset to reinitialize the counter. For example, if the TPDA device has been enabled and then disabled, the counter may have already counted some packets. This could result in an async packet being triggered with an unexpected data size. > >> + writel_relaxed(val, drvdata->base + TPDA_SYNCR); >> } >> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >> hwtracing/coresight/coresight-tpda.h >> index 8a075cfbc3cc..97e2729c15c9 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.h >> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >> @@ -9,6 +9,7 @@ >> #define TPDA_CR (0x000) >> #define TPDA_Pn_CR(n) (0x004 + (n * 4)) >> #define TPDA_FPID_CR (0x084) >> +#define TPDA_SYNCR (0x08C) >> /* Cross trigger Global (all ports) flush request bit */ >> #define TPDA_CR_FLREQ BIT(0) >> @@ -38,6 +39,10 @@ >> #define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) >> /* Aggregator port DSB data set element size bit */ >> #define TPDA_Pn_CR_DSBSIZE BIT(8) > > Newline to separate the defintions of different registers, please. will fix it. Thanks, Jie > >> +/* TPDA_SYNCR mode control bit */ >> +#define TPDA_SYNCR_MODE_CTRL BIT(12) >> +/* TPDA_SYNCR counter mask */ >> +#define TPDA_SYNCR_COUNTER_MASK GENMASK(11, 0) >> #define TPDA_MAX_INPORTS 32 > > Suzuki > > >> > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/3] coresight: tpda: add logic to configure TPDA_SYNCR register 2025-12-19 12:31 ` Jie Gan @ 2025-12-19 13:00 ` Jie Gan 0 siblings, 0 replies; 11+ messages in thread From: Jie Gan @ 2025-12-19 13:00 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Tao Zhang On 12/19/2025 8:31 PM, Jie Gan wrote: > > > On 12/19/2025 6:24 PM, Suzuki K Poulose wrote: >> On 19/12/2025 10:04, Jie Gan wrote: >>> From: Tao Zhang <tao.zhang@oss.qualcomm.com> >>> >>> The TPDA_SYNC counter tracks the number of bytes transferred from the >>> aggregator. When this count reaches the value programmed in the >>> TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace >>> tools to accurately parse each valid packet. >>> >>> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> >>> Reviewed-by: James Clark <james.clark@linaro.org> >>> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> >>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> >>> --- >>> drivers/hwtracing/coresight/coresight-tpda.c | 7 +++++++ >>> drivers/hwtracing/coresight/coresight-tpda.h | 5 +++++ >>> 2 files changed, 12 insertions(+) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >>> hwtracing/coresight/coresight-tpda.c >>> index d25a8bcfb3d4..d378ff8ad77d 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpda.c >>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >>> @@ -163,6 +163,13 @@ static void tpda_enable_pre_port(struct >>> tpda_drvdata *drvdata) >>> */ >>> if (drvdata->trig_flag_ts) >>> writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); >>> + >>> + val = readl_relaxed(drvdata->base + TPDA_SYNCR); >>> + /* Reset the mode ctrl */ >>> + val &= ~TPDA_SYNCR_MODE_CTRL; >>> + /* Program the counter value for TPDA_SYNCR */ >>> + val |= TPDA_SYNCR_COUNTER_MASK; >> >> Do we plan to change this value via sysfs ? If not whats the point of >> clearing the field. Why not simply set it (as it is all 1s anyways). > > We configure the value only once during enablement and do not intend to > modify it through sysfs. The mode_ctrl is reset to reinitialize the > counter. > For example, if the TPDA device has been enabled and then disabled, the > counter may have already counted some packets. This could result in an > async packet being triggered with an unexpected data size. > Missed for explaining the mode_ctrl bit. Set value 0 to the mode_ctrl means reset the counter and set the mode to 0. We have two modes: mode = 0: COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests mode = 1: the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K data by writing a value 13 to the COUNT[11:7] field. Thanks, Jie >> >>> + writel_relaxed(val, drvdata->base + TPDA_SYNCR); >>> } >>> static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) >>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >>> hwtracing/coresight/coresight-tpda.h >>> index 8a075cfbc3cc..97e2729c15c9 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpda.h >>> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >>> @@ -9,6 +9,7 @@ >>> #define TPDA_CR (0x000) >>> #define TPDA_Pn_CR(n) (0x004 + (n * 4)) >>> #define TPDA_FPID_CR (0x084) >>> +#define TPDA_SYNCR (0x08C) >>> /* Cross trigger Global (all ports) flush request bit */ >>> #define TPDA_CR_FLREQ BIT(0) >>> @@ -38,6 +39,10 @@ >>> #define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) >>> /* Aggregator port DSB data set element size bit */ >>> #define TPDA_Pn_CR_DSBSIZE BIT(8) >> >> Newline to separate the defintions of different registers, please. > > will fix it. > > Thanks, > Jie > >> >>> +/* TPDA_SYNCR mode control bit */ >>> +#define TPDA_SYNCR_MODE_CTRL BIT(12) >>> +/* TPDA_SYNCR counter mask */ >>> +#define TPDA_SYNCR_COUNTER_MASK GENMASK(11, 0) >>> #define TPDA_MAX_INPORTS 32 >> >> Suzuki >> >> >>> >> > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 3/3] coresight: tpda: add sysfs node to flush specific port 2025-12-19 10:04 [PATCH v5 0/3] add sysfs nodes to configure TPDA's registers Jie Gan 2025-12-19 10:04 ` [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration Jie Gan 2025-12-19 10:04 ` [PATCH v5 2/3] coresight: tpda: add logic to configure TPDA_SYNCR register Jie Gan @ 2025-12-19 10:04 ` Jie Gan 2025-12-19 10:33 ` Suzuki K Poulose 2 siblings, 1 reply; 11+ messages in thread From: Jie Gan @ 2025-12-19 10:04 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Jie Gan, Tao Zhang From: Tao Zhang <tao.zhang@oss.qualcomm.com> Setting bit i in the TPDA_FLUSH_CR register initiates a flush request for port i, forcing the data to synchronize and be transmitted to the sink device. Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> Reviewed-by: James Clark <james.clark@linaro.org> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> --- .../ABI/testing/sysfs-bus-coresight-devices-tpda | 7 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 49 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 1 + 3 files changed, 57 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda index a7855922328e..ef2804f87d1e 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -41,3 +41,10 @@ Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qu Description: (RW) Configure the CMB/MCMB channel mode for all enabled ports. Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode. + +What: /sys/bus/coresight/devices/<tpda-name>/port_flush_req +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> +Description: + (RW) Configure the bit i to requests a flush operation of port i on the TPDA. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index d378ff8ad77d..5b4a9e41b067 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -375,6 +375,45 @@ static ssize_t tpda_trig_sysfs_store(struct device *dev, return ret; } +static ssize_t port_flush_req_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (!drvdata->csdev->refcnt) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); + + return sysfs_emit(buf, "0x%lx\n", val); +} + +static ssize_t port_flush_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + u32 val; + + if (kstrtou32(buf, 0, &val)) + return -EINVAL; + + if (!drvdata->csdev->refcnt || !val) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + CS_UNLOCK(drvdata->base); + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); + CS_LOCK(drvdata->base); + + return size; +} +static DEVICE_ATTR_RW(port_flush_req); + static struct attribute *tpda_global_cr_attrs[] = { tpda_trig_sysfs_rw(global_flush_req, FLREQ), tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), @@ -385,13 +424,23 @@ static struct attribute *tpda_global_cr_attrs[] = { NULL, }; +static struct attribute *tpda_attrs[] = { + &dev_attr_port_flush_req.attr, + NULL, +}; + static struct attribute_group tpda_global_cr_attr_grp = { .attrs = tpda_global_cr_attrs, .name = "global_cr", }; +static struct attribute_group tpda_attr_grp = { + .attrs = tpda_attrs, +}; + static const struct attribute_group *tpda_attr_grps[] = { &tpda_global_cr_attr_grp, + &tpda_attr_grp, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 97e2729c15c9..ec93f9cb9648 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,7 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) #define TPDA_SYNCR (0x08C) +#define TPDA_FLUSH_CR (0x090) /* Cross trigger Global (all ports) flush request bit */ #define TPDA_CR_FLREQ BIT(0) -- 2.34.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 3/3] coresight: tpda: add sysfs node to flush specific port 2025-12-19 10:04 ` [PATCH v5 3/3] coresight: tpda: add sysfs node to flush specific port Jie Gan @ 2025-12-19 10:33 ` Suzuki K Poulose 2025-12-19 12:32 ` Jie Gan 0 siblings, 1 reply; 11+ messages in thread From: Suzuki K Poulose @ 2025-12-19 10:33 UTC (permalink / raw) To: Jie Gan, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Tao Zhang On 19/12/2025 10:04, Jie Gan wrote: > From: Tao Zhang <tao.zhang@oss.qualcomm.com> > > Setting bit i in the TPDA_FLUSH_CR register initiates a flush request > for port i, forcing the data to synchronize and be transmitted to the > sink device. > > Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> > Reviewed-by: James Clark <james.clark@linaro.org> > Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpda | 7 ++++ > drivers/hwtracing/coresight/coresight-tpda.c | 49 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpda.h | 1 + > 3 files changed, 57 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > index a7855922328e..ef2804f87d1e 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > @@ -41,3 +41,10 @@ Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qu > Description: > (RW) Configure the CMB/MCMB channel mode for all enabled ports. > Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode. > + > +What: /sys/bus/coresight/devices/<tpda-name>/port_flush_req > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> > +Description: > + (RW) Configure the bit i to requests a flush operation of port i on the TPDA. > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index d378ff8ad77d..5b4a9e41b067 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -375,6 +375,45 @@ static ssize_t tpda_trig_sysfs_store(struct device *dev, > return ret; > } > > +static ssize_t port_flush_req_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); > + > + return sysfs_emit(buf, "0x%lx\n", val); > +} > + > +static ssize_t port_flush_req_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + u32 val; > + > + if (kstrtou32(buf, 0, &val)) > + return -EINVAL; > + > + if (!drvdata->csdev->refcnt || !val) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + CS_UNLOCK(drvdata->base); > + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); > + CS_LOCK(drvdata->base); > + > + return size; > +} > +static DEVICE_ATTR_RW(port_flush_req); > + > static struct attribute *tpda_global_cr_attrs[] = { > tpda_trig_sysfs_rw(global_flush_req, FLREQ), > tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), > @@ -385,13 +424,23 @@ static struct attribute *tpda_global_cr_attrs[] = { > NULL, > }; > > +static struct attribute *tpda_attrs[] = { > + &dev_attr_port_flush_req.attr, > + NULL, > +}; > + But why ? Why can't this be a part of the tpda_global_cr_attrs[] ? For that matter, why is tpda_global_cr_attrs named as such and why not tpda_attrs ? Suzuki > static struct attribute_group tpda_global_cr_attr_grp = { > .attrs = tpda_global_cr_attrs, > .name = "global_cr", > }; > > +static struct attribute_group tpda_attr_grp = { > + .attrs = tpda_attrs, > +}; > + > static const struct attribute_group *tpda_attr_grps[] = { > &tpda_global_cr_attr_grp, > + &tpda_attr_grp, > NULL, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index 97e2729c15c9..ec93f9cb9648 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -10,6 +10,7 @@ > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > #define TPDA_FPID_CR (0x084) > #define TPDA_SYNCR (0x08C) > +#define TPDA_FLUSH_CR (0x090) > > /* Cross trigger Global (all ports) flush request bit */ > #define TPDA_CR_FLREQ BIT(0) > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 3/3] coresight: tpda: add sysfs node to flush specific port 2025-12-19 10:33 ` Suzuki K Poulose @ 2025-12-19 12:32 ` Jie Gan 0 siblings, 0 replies; 11+ messages in thread From: Jie Gan @ 2025-12-19 12:32 UTC (permalink / raw) To: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin, Tingwei Zhang Cc: coresight, linux-arm-kernel, linux-kernel, Tao Zhang On 12/19/2025 6:33 PM, Suzuki K Poulose wrote: > On 19/12/2025 10:04, Jie Gan wrote: >> From: Tao Zhang <tao.zhang@oss.qualcomm.com> >> >> Setting bit i in the TPDA_FLUSH_CR register initiates a flush request >> for port i, forcing the data to synchronize and be transmitted to the >> sink device. >> >> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com> >> Reviewed-by: James Clark <james.clark@linaro.org> >> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com> >> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> >> --- >> .../ABI/testing/sysfs-bus-coresight-devices-tpda | 7 ++++ >> drivers/hwtracing/coresight/coresight-tpda.c | 49 ++++++++++++ >> ++++++++++ >> drivers/hwtracing/coresight/coresight-tpda.h | 1 + >> 3 files changed, 57 insertions(+) >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> index a7855922328e..ef2804f87d1e 100644 >> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> @@ -41,3 +41,10 @@ Contact: Jinlong Mao >> <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qu >> Description: >> (RW) Configure the CMB/MCMB channel mode for all enabled ports. >> Value 0 means raw channel mapping mode. Value 1 means >> channel pair marking mode. >> + >> +What: /sys/bus/coresight/devices/<tpda-name>/port_flush_req >> +Date: December 2025 >> +KernelVersion: 6.19 >> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang >> <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com> >> +Description: >> + (RW) Configure the bit i to requests a flush operation of >> port i on the TPDA. >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >> hwtracing/coresight/coresight-tpda.c >> index d378ff8ad77d..5b4a9e41b067 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.c >> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >> @@ -375,6 +375,45 @@ static ssize_t tpda_trig_sysfs_store(struct >> device *dev, >> return ret; >> } >> +static ssize_t port_flush_req_show(struct device *dev, >> + struct device_attribute *attr, >> + char *buf) >> +{ >> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + unsigned long val; >> + >> + if (!drvdata->csdev->refcnt) >> + return -EINVAL; >> + >> + guard(spinlock)(&drvdata->spinlock); >> + val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); >> + >> + return sysfs_emit(buf, "0x%lx\n", val); >> +} >> + >> +static ssize_t port_flush_req_store(struct device *dev, >> + struct device_attribute *attr, >> + const char *buf, >> + size_t size) >> +{ >> + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + u32 val; >> + >> + if (kstrtou32(buf, 0, &val)) >> + return -EINVAL; >> + >> + if (!drvdata->csdev->refcnt || !val) >> + return -EINVAL; >> + >> + guard(spinlock)(&drvdata->spinlock); >> + CS_UNLOCK(drvdata->base); >> + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); >> + CS_LOCK(drvdata->base); >> + >> + return size; >> +} >> +static DEVICE_ATTR_RW(port_flush_req); >> + >> static struct attribute *tpda_global_cr_attrs[] = { >> tpda_trig_sysfs_rw(global_flush_req, FLREQ), >> tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), >> @@ -385,13 +424,23 @@ static struct attribute *tpda_global_cr_attrs[] = { >> NULL, >> }; >> +static struct attribute *tpda_attrs[] = { >> + &dev_attr_port_flush_req.attr, >> + NULL, >> +}; >> + > > But why ? Why can't this be a part of the tpda_global_cr_attrs[] ? > For that matter, why is tpda_global_cr_attrs named as such and why not > tpda_attrs ? > will move all attributes to tpda_attrs[]. Thanks, Jie > Suzuki > >> static struct attribute_group tpda_global_cr_attr_grp = { >> .attrs = tpda_global_cr_attrs, >> .name = "global_cr", >> }; >> +static struct attribute_group tpda_attr_grp = { >> + .attrs = tpda_attrs, >> +}; >> + >> static const struct attribute_group *tpda_attr_grps[] = { >> &tpda_global_cr_attr_grp, >> + &tpda_attr_grp, >> NULL, >> }; >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >> hwtracing/coresight/coresight-tpda.h >> index 97e2729c15c9..ec93f9cb9648 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.h >> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >> @@ -10,6 +10,7 @@ >> #define TPDA_Pn_CR(n) (0x004 + (n * 4)) >> #define TPDA_FPID_CR (0x084) >> #define TPDA_SYNCR (0x08C) >> +#define TPDA_FLUSH_CR (0x090) >> /* Cross trigger Global (all ports) flush request bit */ >> #define TPDA_CR_FLREQ BIT(0) >> > ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-12-19 13:00 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-12-19 10:04 [PATCH v5 0/3] add sysfs nodes to configure TPDA's registers Jie Gan 2025-12-19 10:04 ` [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration Jie Gan 2025-12-19 10:22 ` Suzuki K Poulose 2025-12-19 12:19 ` Jie Gan 2025-12-19 10:04 ` [PATCH v5 2/3] coresight: tpda: add logic to configure TPDA_SYNCR register Jie Gan 2025-12-19 10:24 ` Suzuki K Poulose 2025-12-19 12:31 ` Jie Gan 2025-12-19 13:00 ` Jie Gan 2025-12-19 10:04 ` [PATCH v5 3/3] coresight: tpda: add sysfs node to flush specific port Jie Gan 2025-12-19 10:33 ` Suzuki K Poulose 2025-12-19 12:32 ` Jie Gan
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