* [PATCH 0/4] media: qcom: camss: Add SM8150 CAMSS support
@ 2026-11-04 20:54 Andrew Gigena via B4 Relay
2026-11-04 20:54 ` [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible Andrew Gigena via B4 Relay
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Andrew Gigena via B4 Relay @ 2026-11-04 20:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Andrew Gigena
This series adds SoC-level CAMSS support for the Qualcomm SM8150
(Snapdragon 855), based on v7.4-rc1.
SM8150 contains four CSIPHY, four CSID (two full and two lite), two
VFE and two VFE-Lite instances. The blocks are close to the existing
SDM845/SM8250/SC8280XP implementations, so the driver change only adds
platform data and hooks the SoC into the existing Gen2 CSIPHY, Gen2
CSID and VFE 17x code paths. No new register programming sequences are
introduced.
The series documents the SM8150 CCI compatible, which the CCI nodes use
with qcom,msm8996-cci as the fallback. The patches are ordered bindings
first, then driver data, then the DT description. The series is
intentionally SoC-level only: it does not add a board DTS, camera
sensor drivers, or board-specific camera wiring.
Testing: with a local Pixel 4 (google-flame) board port and
out-of-tree IMX363, IMX481 and IMX520 sensor drivers, the rear wide
(IMX363) and rear tele (IMX481) cameras stream, and the front (IMX520)
path has produced frames. The board port itself is not part of this
series.
checkpatch reports no errors. The only warning is the new-binding
"MAINTAINERS needs updating" prompt, which is a false positive because
the existing CAMSS entry already covers qcom,*camss* bindings.
Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
---
Andrew Gigena (4):
dt-bindings: i2c: qcom-cci: Document SM8150 compatible
dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS
media: qcom: camss: Add support for SM8150
arm64: dts: qcom: sm8150: Add CAMSS and CCI nodes
.../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 1 +
.../bindings/media/qcom,sm8150-camss.yaml | 477 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 350 +++++++++++++++
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 262 +++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
7 files changed, 1095 insertions(+)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261104-sm8150-v7-4-rc1-camss-d3dd5e02a170
Best regards,
--
Andrew Gigena <mail@andrewgigena.dev>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible
2026-11-04 20:54 [PATCH 0/4] media: qcom: camss: Add SM8150 CAMSS support Andrew Gigena via B4 Relay
@ 2026-11-04 20:54 ` Andrew Gigena via B4 Relay
2026-11-04 22:41 ` Bryan O'Donoghue
2026-11-04 23:12 ` Vladimir Zapolskiy
2026-11-04 20:54 ` [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS Andrew Gigena via B4 Relay
` (2 subsequent siblings)
3 siblings, 2 replies; 13+ messages in thread
From: Andrew Gigena via B4 Relay @ 2026-11-04 20:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Andrew Gigena
From: Andrew Gigena <mail@andrewgigena.dev>
Add qcom,sm8150-cci as a CCI v2 compatible, with qcom,msm8996-cci as
the fallback.
Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 1e8def25ec0e..b545fd2378da 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -39,6 +39,7 @@ properties:
- qcom,shikra-cci
- qcom,sm6150-cci
- qcom,sm6350-cci
+ - qcom,sm8150-cci
- qcom,sm8250-cci
- qcom,sm8450-cci
- qcom,sm8550-cci
--
2.56.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS
2026-11-04 20:54 [PATCH 0/4] media: qcom: camss: Add SM8150 CAMSS support Andrew Gigena via B4 Relay
2026-11-04 20:54 ` [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible Andrew Gigena via B4 Relay
@ 2026-11-04 20:54 ` Andrew Gigena via B4 Relay
2026-11-04 22:44 ` Bryan O'Donoghue
2026-11-04 23:16 ` Vladimir Zapolskiy
2026-11-04 20:54 ` [PATCH 3/4] media: qcom: camss: Add support for SM8150 Andrew Gigena via B4 Relay
2026-11-04 20:54 ` [PATCH 4/4] arm64: dts: qcom: sm8150: Add CAMSS and CCI nodes Andrew Gigena via B4 Relay
3 siblings, 2 replies; 13+ messages in thread
From: Andrew Gigena via B4 Relay @ 2026-11-04 20:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Andrew Gigena
From: Andrew Gigena <mail@andrewgigena.dev>
Document the Qualcomm SM8150 Camera Subsystem. The IP integrates four
CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite
instances, with 42 clocks, 12 interrupts, eight IOMMU streams, four
interconnect paths and three power domains.
SM8150 has a different register layout, clock tree and power domain
topology from SM8250, so describe it in a dedicated schema instead of
using qcom,sm8250-camss as a fallback.
Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
---
.../bindings/media/qcom,sm8150-camss.yaml | 477 +++++++++++++++++++++
1 file changed, 477 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml
new file mode 100644
index 000000000000..a65067352b58
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml
@@ -0,0 +1,477 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8150-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8150 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Andrew Gigena <mail@andrewgigena.dev>
+
+description: |
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sm8150-camss
+
+ clocks:
+ minItems: 42
+ maxItems: 42
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: camnoc_axi_src
+ - const: cpas_ahb
+ - const: cphy_rx_src
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy0_timer_src
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy1_timer_src
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy2_timer_src
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy3_timer_src
+ - const: vfe0_axi
+ - const: vfe0
+ - const: vfe0_src
+ - const: vfe0_cphy_rx
+ - const: vfe0_csid
+ - const: vfe0_csid_src
+ - const: vfe1_axi
+ - const: vfe1
+ - const: vfe1_src
+ - const: vfe1_cphy_rx
+ - const: vfe1_csid
+ - const: vfe1_csid_src
+ - const: vfe_lite0
+ - const: vfe_lite0_src
+ - const: vfe_lite0_cphy_rx
+ - const: vfe_lite0_csid
+ - const: vfe_lite0_csid_src
+ - const: vfe_lite1
+ - const: vfe_lite1_src
+ - const: vfe_lite1_cphy_rx
+ - const: vfe_lite1_csid
+ - const: vfe_lite1_csid_src
+ - const: slow_ahb_src
+ - const: gcc_ahb
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+
+ interrupts:
+ minItems: 12
+ maxItems: 12
+
+ interrupt-names:
+ items:
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: vfe0
+ - const: csid0
+ - const: vfe1
+ - const: csid1
+ - const: vfe_lite0
+ - const: csid_lite0
+ - const: vfe_lite1
+ - const: csid_lite1
+
+ iommus:
+ maxItems: 8
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: cam_ahb
+ - const: cam_hf_0_mnoc
+ - const: cam_hf_1_mnoc
+ - const: cam_sf_0_mnoc
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: top
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data from CSIPHY0.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data from CSIPHY1.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data from CSIPHY2.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data from CSIPHY3.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ reg:
+ minItems: 12
+ maxItems: 12
+
+ reg-names:
+ items:
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: vfe0
+ - const: csid0
+ - const: vfe1
+ - const: csid1
+ - const: vfe_lite0
+ - const: csid_lite0
+ - const: vfe_lite1
+ - const: csid_lite1
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - interrupt-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - reg
+ - reg-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-sm8150.h>
+ #include <dt-bindings/clock/qcom,sm8150-camcc.h>
+ #include <dt-bindings/interconnect/qcom,sm8150.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: camss@ac65000 {
+ compatible = "qcom,sm8150-camss";
+
+ reg = <0 0xac65000 0 0x1000>,
+ <0 0xac66000 0 0x1000>,
+ <0 0xac67000 0 0x1000>,
+ <0 0xac68000 0 0x1000>,
+ <0 0xacaf000 0 0x4000>,
+ <0 0xacb3000 0 0x1000>,
+ <0 0xacb6000 0 0x4000>,
+ <0 0xacba000 0 0x1000>,
+ <0 0xacc4000 0 0x4000>,
+ <0 0xacc8000 0 0x1000>,
+ <0 0xaccb000 0 0x4000>,
+ <0 0xaccf000 0 0x1000>;
+
+ reg-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe_lite0",
+ "csid_lite0",
+ "vfe_lite1",
+ "csid_lite1";
+
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe_lite0",
+ "csid_lite0",
+ "vfe_lite1",
+ "csid_lite1";
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc TITAN_TOP_GDSC>;
+
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_0_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_1_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CSID_CLK_SRC>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>;
+
+ clock-names = "camnoc_axi",
+ "camnoc_axi_src",
+ "cpas_ahb",
+ "cphy_rx_src",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy0_timer_src",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy1_timer_src",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy2_timer_src",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy3_timer_src",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_src",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe0_csid_src",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_src",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe1_csid_src",
+ "vfe_lite0",
+ "vfe_lite0_src",
+ "vfe_lite0_cphy_rx",
+ "vfe_lite0_csid",
+ "vfe_lite0_csid_src",
+ "vfe_lite1",
+ "vfe_lite1_src",
+ "vfe_lite1_cphy_rx",
+ "vfe_lite1_csid",
+ "vfe_lite1_csid_src",
+ "slow_ahb_src",
+ "gcc_ahb",
+ "gcc_axi_hf",
+ "gcc_axi_sf";
+
+ iommus = <&apps_smmu 0x840 0x620>,
+ <&apps_smmu 0x860 0x620>,
+ <&apps_smmu 0xA40 0x620>,
+ <&apps_smmu 0xA60 0x620>,
+ <&apps_smmu 0xC40 0x620>,
+ <&apps_smmu 0xC60 0x620>,
+ <&apps_smmu 0xE40 0x620>,
+ <&apps_smmu 0xE60 0x620>;
+
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF0 0 &mc_virt SLAVE_EBI_CH0 0>,
+ <&mmss_noc MASTER_CAMNOC_HF1 0 &mc_virt SLAVE_EBI_CH0 0>,
+ <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>;
+
+ interconnect-names = "cam_ahb",
+ "cam_hf_0_mnoc",
+ "cam_hf_1_mnoc",
+ "cam_sf_0_mnoc";
+
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l3c_1p2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csiphy_ep0: endpoint@0 {
+ reg = <0>;
+ clock-lanes = <7>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.56.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/4] media: qcom: camss: Add support for SM8150
2026-11-04 20:54 [PATCH 0/4] media: qcom: camss: Add SM8150 CAMSS support Andrew Gigena via B4 Relay
2026-11-04 20:54 ` [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible Andrew Gigena via B4 Relay
2026-11-04 20:54 ` [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS Andrew Gigena via B4 Relay
@ 2026-11-04 20:54 ` Andrew Gigena via B4 Relay
2026-11-04 21:19 ` Val Packett
2026-11-05 9:44 ` Bryan O'Donoghue
2026-11-04 20:54 ` [PATCH 4/4] arm64: dts: qcom: sm8150: Add CAMSS and CCI nodes Andrew Gigena via B4 Relay
3 siblings, 2 replies; 13+ messages in thread
From: Andrew Gigena via B4 Relay @ 2026-11-04 20:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Andrew Gigena
From: Andrew Gigena <mail@andrewgigena.dev>
Add CAMSS platform data for the Qualcomm SM8150 SoC. The camera
subsystem contains four CSIPHY, four CSID (two full and two lite), two
VFE and two VFE-Lite instances.
The hardware reuses the existing 3-phase 1.0 CSIPHY, Gen2 CSID and
VFE 17x implementations; the CSIPHY uses the SC8280XP lane register
layout. Add CAMSS_8150 to the version enum and to the shared code
paths, then add the per-block clock, regulator, power domain,
interrupt and interconnect resources.
Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 262 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
4 files changed, 267 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index dac8d2ecf799..851decb0691e 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1141,6 +1141,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
+ case CAMSS_8150:
ret = true;
break;
}
@@ -1236,6 +1237,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
break;
case CAMSS_8280XP:
+ case CAMSS_8150:
regs->lane_regs = &lane_regs_sc8280xp[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
break;
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 2680a9914765..dd28058e98a7 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -354,6 +354,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
+ case CAMSS_8150:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
{
@@ -2010,6 +2011,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_8280XP:
case CAMSS_8300:
case CAMSS_845:
+ case CAMSS_8150:
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index c54185c93a8a..7035f5b333ff 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -1940,6 +1940,254 @@ static const struct resources_icc icc_res_sm6350[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_sm8150[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {},
+ .clock = { "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = {},
+ .clock = { "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = {},
+ .clock = { "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = {},
+ .clock = { "csiphy3", "csiphy3_timer" },
+ .clock_rate = { { 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_sm8150[] = {
+ /* CSID0 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 0 },
+ { .supply = "vdda-pll", .init_load_uA = 0 }
+ },
+ .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" },
+ .clock_rate = { { 400000000, 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 0 },
+ { .supply = "vdda-pll", .init_load_uA = 0 }
+ },
+ .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" },
+ .clock_rate = { { 400000000, 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 0 },
+ { .supply = "vdda-pll", .init_load_uA = 0 }
+ },
+ .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
+ .clock_rate = { { 400000000, 480000000, 600000000 },
+ { 0 },
+ { 0 }, },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 0 },
+ { .supply = "vdda-pll", .init_load_uA = 0 }
+ },
+ .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
+ .clock_rate = { { 400000000, 480000000, 600000000 },
+ { 0 },
+ { 0 }, },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
+static const struct camss_subdev_resources vfe_res_sm8150[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi",
+ "vfe0", "vfe0_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 19200000, 80000000},
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 400000000, 558000000, 637000000, 847000000, 950000000 },
+ { 0 }, },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi",
+ "vfe1", "vfe1_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 19200000, 80000000},
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 400000000, 558000000, 637000000, 847000000, 950000000 },
+ { 0 }, },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE_0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite0" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 19200000, 80000000},
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 320000000, 400000000, 480000000, 600000000 }, },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE_1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite1" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 19200000, 80000000},
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 320000000, 400000000, 480000000, 600000000 }, },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ }
+};
+
+static const struct resources_icc icc_res_sm8150[] = {
+ {
+ .name = "cam_ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "cam_hf_0_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+ {
+ .name = "cam_hf_1_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+ {
+ .name = "cam_sf_0_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8250[] = {
/* CSIPHY0 */
{
@@ -5725,6 +5973,19 @@ static const struct camss_resources sm6350_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm6350),
};
+static const struct camss_resources sm8150_resources = {
+ .version = CAMSS_8150,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_sm8150,
+ .csid_res = csid_res_sm8150,
+ .vfe_res = vfe_res_sm8150,
+ .icc_res = icc_res_sm8150,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8150),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_sm8150),
+ .csid_num = ARRAY_SIZE(csid_res_sm8150),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm8150),
+};
+
static const struct camss_resources sm8250_resources = {
.version = CAMSS_8250,
.pd_name = "top",
@@ -5824,6 +6085,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
{ .compatible = "qcom,sm6350-camss", .data = &sm6350_resources },
+ { .compatible = "qcom,sm8150-camss", .data = &sm8150_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 7dc2fd9f03e0..74d8cc2921be 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -89,6 +89,7 @@ enum camss_version {
CAMSS_8x39,
CAMSS_8x53,
CAMSS_8x96,
+ CAMSS_8150,
CAMSS_8250,
CAMSS_8280XP,
CAMSS_8300,
--
2.56.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/4] arm64: dts: qcom: sm8150: Add CAMSS and CCI nodes
2026-11-04 20:54 [PATCH 0/4] media: qcom: camss: Add SM8150 CAMSS support Andrew Gigena via B4 Relay
` (2 preceding siblings ...)
2026-11-04 20:54 ` [PATCH 3/4] media: qcom: camss: Add support for SM8150 Andrew Gigena via B4 Relay
@ 2026-11-04 20:54 ` Andrew Gigena via B4 Relay
3 siblings, 0 replies; 13+ messages in thread
From: Andrew Gigena via B4 Relay @ 2026-11-04 20:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media,
Andrew Gigena
From: Andrew Gigena <mail@andrewgigena.dev>
Describe the SM8150 CAMSS block and its CSIPHY, CSID, VFE and
VFE-Lite instances, together with the two CCI controllers and their
I2C buses.
The CAMSS node exposes four CSI input ports and references the CAMCC
clocks and GDSCs, the interconnects and the IOMMU streams. The CCI
nodes describe the CCI0/CCI1 I2C buses, and the TLMM pinctrl states
for their clock and data lines are added to the existing pin
controller node.
All new nodes are left disabled. The CAMSS supplies and the sensor
wiring are board-specific, so they belong in the board DTS that
enables the controller.
Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 350 +++++++++++++++++++++++++++++++++++
1 file changed, 350 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 293fcbacff34..72bfcaea8cf8 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2736,6 +2736,86 @@ wake-pins {
bias-pull-up;
};
};
+
+ cci0_default: cci0-default-state {
+ cci0_i2c0_default: cci0-i2c0-default-pins {
+ /* CLK, DATA */
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci0_i2c1_default: cci0-i2c1-default-pins {
+ /* CLK, DATA */
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
+ /* CLK, DATA */
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ };
+
+ cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
+ /* CLK, DATA */
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ };
+ };
+
+ cci1_default: cci1-default-state {
+ cci1_i2c0_default: cci1-i2c0-default-pins {
+ /* CLK, DATA */
+ pins = "gpio31", "gpio32";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci1_i2c1_default: cci1-i2c1-default-pins {
+ /* CLK, DATA */
+ pins = "gpio33", "gpio34";
+ function = "cci_i2c";
+
+ bias-pull-up;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
+ /* CLK, DATA */
+ pins = "gpio31", "gpio32";
+ function = "cci_i2c";
+
+ bias-pull-down;
+ drive-strength = <2>; /* 2 mA */
+ };
+
+ cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
+ /* CLK, DATA */
+ pins = "gpio33", "gpio34";
+ function = "cci_i2c";
+
+ bias-pull-down;
+ drive-strength = <2>; /* 2 mA */
+ };
+ };
};
remoteproc_mpss: remoteproc@4080000 {
@@ -3782,6 +3862,276 @@ camnoc_virt: interconnect@ac00000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ cci0: cci@ac4a000 {
+ compatible = "qcom,sm8150-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0xac4a000 0 0x1000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ pinctrl-0 = <&cci0_default>;
+ pinctrl-1 = <&cci0_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac4b000 {
+ compatible = "qcom,sm8150-cci", "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0xac4b000 0 0x1000>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ pinctrl-0 = <&cci1_default>;
+ pinctrl-1 = <&cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ camss: camss@ac65000 {
+ compatible = "qcom,sm8150-camss";
+ status = "disabled";
+
+ reg = <0 0xac65000 0 0x1000>,
+ <0 0xac66000 0 0x1000>,
+ <0 0xac67000 0 0x1000>,
+ <0 0xac68000 0 0x1000>,
+ <0 0xacaf000 0 0x4000>,
+ <0 0xacb3000 0 0x1000>,
+ <0 0xacb6000 0 0x4000>,
+ <0 0xacba000 0 0x1000>,
+ <0 0xacc4000 0 0x4000>,
+ <0 0xacc8000 0 0x1000>,
+ <0 0xaccb000 0 0x4000>,
+ <0 0xaccf000 0 0x1000>;
+
+ reg-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe_lite0",
+ "csid_lite0",
+ "vfe_lite1",
+ "csid_lite1";
+
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "csid0",
+ "vfe1",
+ "csid1",
+ "vfe_lite0",
+ "csid_lite0",
+ "vfe_lite1",
+ "csid_lite1";
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_0_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_0_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_1_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_1_CSID_CLK_SRC>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>;
+ clock-names = "camnoc_axi",
+ "camnoc_axi_src",
+ "cpas_ahb",
+ "cphy_rx_src",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy0_timer_src",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy1_timer_src",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy2_timer_src",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy3_timer_src",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_src",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe0_csid_src",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_src",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe1_csid_src",
+ "vfe_lite0",
+ "vfe_lite0_src",
+ "vfe_lite0_cphy_rx",
+ "vfe_lite0_csid",
+ "vfe_lite0_csid_src",
+ "vfe_lite1",
+ "vfe_lite1_src",
+ "vfe_lite1_cphy_rx",
+ "vfe_lite1_csid",
+ "vfe_lite1_csid_src",
+ "slow_ahb_src",
+ "gcc_ahb",
+ "gcc_axi_hf",
+ "gcc_axi_sf";
+
+ iommus = <&apps_smmu 0x840 0x620>,
+ <&apps_smmu 0x860 0x620>,
+ <&apps_smmu 0xA40 0x620>,
+ <&apps_smmu 0xA60 0x620>,
+ <&apps_smmu 0xC40 0x620>,
+ <&apps_smmu 0xC60 0x620>,
+ <&apps_smmu 0xE40 0x620>,
+ <&apps_smmu 0xE60 0x620>;
+
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF0 0 &mc_virt SLAVE_EBI_CH0 0>,
+ <&mmss_noc MASTER_CAMNOC_HF1 0 &mc_virt SLAVE_EBI_CH0 0>,
+ <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "cam_ahb",
+ "cam_hf_0_mnoc",
+ "cam_hf_1_mnoc",
+ "cam_sf_0_mnoc";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sm8150-camcc";
reg = <0 0x0ad00000 0 0x10000>;
--
2.56.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] media: qcom: camss: Add support for SM8150
2026-11-04 20:54 ` [PATCH 3/4] media: qcom: camss: Add support for SM8150 Andrew Gigena via B4 Relay
@ 2026-11-04 21:19 ` Val Packett
2026-11-04 23:12 ` Andrew Gigena
2026-11-05 9:44 ` Bryan O'Donoghue
1 sibling, 1 reply; 13+ messages in thread
From: Val Packett @ 2026-11-04 21:19 UTC (permalink / raw)
To: mail, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media
Hi,
On 11/4/26 5:54 PM, Andrew Gigena via B4 Relay wrote:
> From: Andrew Gigena <mail@andrewgigena.dev>
>
> Add CAMSS platform data for the Qualcomm SM8150 SoC. The camera
> subsystem contains four CSIPHY, four CSID (two full and two lite), two
> VFE and two VFE-Lite instances.
>
> The hardware reuses the existing 3-phase 1.0 CSIPHY, Gen2 CSID and
> VFE 17x implementations; the CSIPHY uses the SC8280XP lane register
> layout. Add CAMSS_8150 to the version enum and to the shared code
> paths, then add the per-block clock, regulator, power domain,
> interrupt and interconnect resources.
>
> Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
> ---
Wow, what an unbelievable coincidence — I just went looking for this and
found these patches on gitlab in order to test on the similar sc8180x,
and half an hour later you've submitted it to the lists! :D
> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +
> drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
> drivers/media/platform/qcom/camss/camss.c | 262 +++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 4 files changed, 267 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index dac8d2ecf799..851decb0691e 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -1141,6 +1141,7 @@ static bool csiphy_is_gen2(u32 version)
> case CAMSS_8650:
> case CAMSS_8775P:
> case CAMSS_X1E80100:
> + case CAMSS_8150:
It should probably go higher in the sort order, before 8250?
> ret = true;
> break;
> }
> @@ -1236,6 +1237,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
> regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
> break;
> case CAMSS_8280XP:
> + case CAMSS_8150:
> regs->lane_regs = &lane_regs_sc8280xp[0];
> regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
> break;
Interesting, why do these match 8280xp and not, say, 8250?
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index 2680a9914765..dd28058e98a7 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -354,6 +354,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> case CAMSS_8650:
> case CAMSS_8775P:
> case CAMSS_X1E80100:
> + case CAMSS_8150:
Sort order here too
> switch (sink_code) {
> case MEDIA_BUS_FMT_YUYV8_1X16:
> {
> @@ -2010,6 +2011,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
> case CAMSS_8280XP:
> case CAMSS_8300:
> case CAMSS_845:
> + case CAMSS_8150:
> case CAMSS_8550:
> case CAMSS_8650:
> case CAMSS_8775P:
> [..]
Thanks,
~val
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible
2026-11-04 20:54 ` [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible Andrew Gigena via B4 Relay
@ 2026-11-04 22:41 ` Bryan O'Donoghue
2026-11-04 23:12 ` Vladimir Zapolskiy
1 sibling, 0 replies; 13+ messages in thread
From: Bryan O'Donoghue @ 2026-11-04 22:41 UTC (permalink / raw)
To: mail, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media
On 04/11/2026 20:54, Andrew Gigena via B4 Relay wrote:
> From: Andrew Gigena <mail@andrewgigena.dev>
>
> Add qcom,sm8150-cci as a CCI v2 compatible, with qcom,msm8996-cci as
> the fallback.
>
> Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
> ---
> Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> index 1e8def25ec0e..b545fd2378da 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> @@ -39,6 +39,7 @@ properties:
> - qcom,shikra-cci
> - qcom,sm6150-cci
> - qcom,sm6350-cci
> + - qcom,sm8150-cci
> - qcom,sm8250-cci
> - qcom,sm8450-cci
> - qcom,sm8550-cci
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS
2026-11-04 20:54 ` [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS Andrew Gigena via B4 Relay
@ 2026-11-04 22:44 ` Bryan O'Donoghue
2026-11-04 23:16 ` Vladimir Zapolskiy
1 sibling, 0 replies; 13+ messages in thread
From: Bryan O'Donoghue @ 2026-11-04 22:44 UTC (permalink / raw)
To: mail, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media
On 04/11/2026 20:54, Andrew Gigena via B4 Relay wrote:
> From: Andrew Gigena <mail@andrewgigena.dev>
>
> Document the Qualcomm SM8150 Camera Subsystem. The IP integrates four
> CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite
> instances, with 42 clocks, 12 interrupts, eight IOMMU streams, four
> interconnect paths and three power domains.
>
> SM8150 has a different register layout, clock tree and power domain
> topology from SM8250, so describe it in a dedicated schema instead of
> using qcom,sm8250-camss as a fallback.
>
> Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
> ---
> .../bindings/media/qcom,sm8150-camss.yaml | 477 +++++++++++++++++++++
> 1 file changed, 477 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml
> new file mode 100644
> index 000000000000..a65067352b58
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml
> @@ -0,0 +1,477 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sm8150-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8150 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Andrew Gigena <mail@andrewgigena.dev>
> +
> +description: |
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,sm8150-camss
> +
> + clocks:
> + minItems: 42
> + maxItems: 42
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: camnoc_axi_src
> + - const: cpas_ahb
> + - const: cphy_rx_src
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy0_timer_src
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy1_timer_src
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy2_timer_src
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy3_timer_src
> + - const: vfe0_axi
> + - const: vfe0
> + - const: vfe0_src
> + - const: vfe0_cphy_rx
> + - const: vfe0_csid
> + - const: vfe0_csid_src
> + - const: vfe1_axi
> + - const: vfe1
> + - const: vfe1_src
> + - const: vfe1_cphy_rx
> + - const: vfe1_csid
> + - const: vfe1_csid_src
> + - const: vfe_lite0
> + - const: vfe_lite0_src
> + - const: vfe_lite0_cphy_rx
> + - const: vfe_lite0_csid
> + - const: vfe_lite0_csid_src
> + - const: vfe_lite1
> + - const: vfe_lite1_src
> + - const: vfe_lite1_cphy_rx
> + - const: vfe_lite1_csid
> + - const: vfe_lite1_csid_src
> + - const: slow_ahb_src
> + - const: gcc_ahb
> + - const: gcc_axi_hf
> + - const: gcc_axi_sf
> +
> + interrupts:
> + minItems: 12
> + maxItems: 12
> +
> + interrupt-names:
> + items:
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: vfe0
> + - const: csid0
> + - const: vfe1
> + - const: csid1
> + - const: vfe_lite0
> + - const: csid_lite0
> + - const: vfe_lite1
> + - const: csid_lite1
> +
> + iommus:
> + maxItems: 8
> +
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: cam_ahb
> + - const: cam_hf_0_mnoc
> + - const: cam_hf_1_mnoc
> + - const: cam_sf_0_mnoc
> +
> + power-domains:
> + items:
> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: ife0
> + - const: ife1
> + - const: top
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data from CSIPHY0.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data from CSIPHY1.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data from CSIPHY2.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data from CSIPHY3.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + reg:
> + minItems: 12
> + maxItems: 12
> +
> + reg-names:
> + items:
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: vfe0
> + - const: csid0
> + - const: vfe1
> + - const: csid1
> + - const: vfe_lite0
> + - const: csid_lite0
> + - const: vfe_lite1
> + - const: csid_lite1
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +required:
> + - clock-names
> + - clocks
> + - compatible
> + - interconnects
> + - interconnect-names
> + - interrupts
> + - interrupt-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - reg
> + - reg-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,gcc-sm8150.h>
> + #include <dt-bindings/clock/qcom,sm8150-camcc.h>
> + #include <dt-bindings/interconnect/qcom,sm8150.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: camss@ac65000 {
> + compatible = "qcom,sm8150-camss";
> +
> + reg = <0 0xac65000 0 0x1000>,
> + <0 0xac66000 0 0x1000>,
> + <0 0xac67000 0 0x1000>,
> + <0 0xac68000 0 0x1000>,
> + <0 0xacaf000 0 0x4000>,
> + <0 0xacb3000 0 0x1000>,
> + <0 0xacb6000 0 0x4000>,
> + <0 0xacba000 0 0x1000>,
> + <0 0xacc4000 0 0x4000>,
> + <0 0xacc8000 0 0x1000>,
> + <0 0xaccb000 0 0x4000>,
> + <0 0xaccf000 0 0x1000>;
> +
> + reg-names = "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "vfe0",
> + "csid0",
> + "vfe1",
> + "csid1",
> + "vfe_lite0",
> + "csid_lite0",
> + "vfe_lite1",
> + "csid_lite1";
> +
> + interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>;
> +
> + interrupt-names = "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "vfe0",
> + "csid0",
> + "vfe1",
> + "csid1",
> + "vfe_lite0",
> + "csid_lite0",
> + "vfe_lite1",
> + "csid_lite1";
> +
> + power-domains = <&camcc IFE_0_GDSC>,
> + <&camcc IFE_1_GDSC>,
> + <&camcc TITAN_TOP_GDSC>;
> +
> + power-domain-names = "ife0",
> + "ife1",
> + "top";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
> + <&camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK_SRC>,
> + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
> + <&camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK_SRC>,
> + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
> + <&camcc CAM_CC_IFE_LITE_0_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CLK_SRC>,
> + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK_SRC>,
> + <&camcc CAM_CC_IFE_LITE_1_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CLK_SRC>,
> + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK_SRC>,
> + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>;
> +
> + clock-names = "camnoc_axi",
> + "camnoc_axi_src",
> + "cpas_ahb",
> + "cphy_rx_src",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy0_timer_src",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy1_timer_src",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy2_timer_src",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy3_timer_src",
> + "vfe0_axi",
> + "vfe0",
> + "vfe0_src",
> + "vfe0_cphy_rx",
> + "vfe0_csid",
> + "vfe0_csid_src",
> + "vfe1_axi",
> + "vfe1",
> + "vfe1_src",
> + "vfe1_cphy_rx",
> + "vfe1_csid",
> + "vfe1_csid_src",
> + "vfe_lite0",
> + "vfe_lite0_src",
> + "vfe_lite0_cphy_rx",
> + "vfe_lite0_csid",
> + "vfe_lite0_csid_src",
> + "vfe_lite1",
> + "vfe_lite1_src",
> + "vfe_lite1_cphy_rx",
> + "vfe_lite1_csid",
> + "vfe_lite1_csid_src",
> + "slow_ahb_src",
> + "gcc_ahb",
> + "gcc_axi_hf",
> + "gcc_axi_sf";
42 is ofc a sacred number so its a pity BUT you almost certainly don't
need the _src clocks here.
> +
> + iommus = <&apps_smmu 0x840 0x620>,
> + <&apps_smmu 0x860 0x620>,
> + <&apps_smmu 0xA40 0x620>,
> + <&apps_smmu 0xA60 0x620>,
> + <&apps_smmu 0xC40 0x620>,
> + <&apps_smmu 0xC60 0x620>,
> + <&apps_smmu 0xE40 0x620>,
> + <&apps_smmu 0xE60 0x620>;
> +
> + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
> + <&mmss_noc MASTER_CAMNOC_HF0 0 &mc_virt SLAVE_EBI_CH0 0>,
> + <&mmss_noc MASTER_CAMNOC_HF1 0 &mc_virt SLAVE_EBI_CH0 0>,
> + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>;
> +
> + interconnect-names = "cam_ahb",
> + "cam_hf_0_mnoc",
> + "cam_hf_1_mnoc",
> + "cam_sf_0_mnoc";
> +
> + vdda-phy-supply = <&vreg_l5a_0p88>;
> + vdda-pll-supply = <&vreg_l3c_1p2>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + csiphy_ep0: endpoint@0 {
> + reg = <0>;
> + clock-lanes = <7>;
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&sensor_ep>;
> + };
> + };
> + };
> + };
> + };
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] media: qcom: camss: Add support for SM8150
2026-11-04 21:19 ` Val Packett
@ 2026-11-04 23:12 ` Andrew Gigena
0 siblings, 0 replies; 13+ messages in thread
From: Andrew Gigena @ 2026-11-04 23:12 UTC (permalink / raw)
To: Val Packett
Cc: mail, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Abel Vesa, linux-arm-msm,
linux-i2c, devicetree, linux-kernel, linux-media
Hi Val,
Thanks for the review, and great timing on the SC8180X work.
> It should probably go higher in the sort order, before 8250?
Agreed. I’ve moved them for the next version.
> Interesting, why do these match 8280xp and not, say, 8250?
SM8150’s downstream DT describes the PHY as qcom,csiphy-v1.1, and the
v1.1 2PH (D-PHY) lane sequence in cam_csiphy_1_1_hwreg.h matches the
2PH entries in lane_regs_sc8280xp offset-for-offset:
- 0x0004, 0x002C, 0x0034, 0x001C, 0x0014, 0x0028, 0x003C, 0x0000,
0x0008, 0x000C, 0x0010, 0x0038, 0x0060, 0x0064
- lane blocks at 0x0704, 0x0204, 0x0404, 0x0604
- with 0x0728 = 0x04, 0x0700 = 0x80, 0x070C = 0xA5, 0x0738 = 0x1F
The SM8250 lane_regs_sm8250 table is a different sequence (0x0030,
0x0900/0x0908, 0x0034 = 0x07, 0x0010 = 0x02, etc.), so it doesn’t fit
the v1.1 PHY. If SC8180X uses the same v1.1 CSIPHY, the SC8280XP lane
table should be the right starting point there too.
See https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-coral-4.14-android13/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h
El mié, 4 nov 2026 a la(s) 6:19 p.m., Val Packett (val@packett.cool) escribió:
>
> Hi,
>
> On 11/4/26 5:54 PM, Andrew Gigena via B4 Relay wrote:
> > From: Andrew Gigena <mail@andrewgigena.dev>
> >
> > Add CAMSS platform data for the Qualcomm SM8150 SoC. The camera
> > subsystem contains four CSIPHY, four CSID (two full and two lite), two
> > VFE and two VFE-Lite instances.
> >
> > The hardware reuses the existing 3-phase 1.0 CSIPHY, Gen2 CSID and
> > VFE 17x implementations; the CSIPHY uses the SC8280XP lane register
> > layout. Add CAMSS_8150 to the version enum and to the shared code
> > paths, then add the per-block clock, regulator, power domain,
> > interrupt and interconnect resources.
> >
> > Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
> > ---
> Wow, what an unbelievable coincidence — I just went looking for this and
> found these patches on gitlab in order to test on the similar sc8180x,
> and half an hour later you've submitted it to the lists! :D
> > .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +
> > drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
> > drivers/media/platform/qcom/camss/camss.c | 262 +++++++++++++++++++++
> > drivers/media/platform/qcom/camss/camss.h | 1 +
> > 4 files changed, 267 insertions(+)
> >
> > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> > index dac8d2ecf799..851decb0691e 100644
> > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> > @@ -1141,6 +1141,7 @@ static bool csiphy_is_gen2(u32 version)
> > case CAMSS_8650:
> > case CAMSS_8775P:
> > case CAMSS_X1E80100:
> > + case CAMSS_8150:
> It should probably go higher in the sort order, before 8250?
> > ret = true;
> > break;
> > }
> > @@ -1236,6 +1237,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
> > regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
> > break;
> > case CAMSS_8280XP:
> > + case CAMSS_8150:
> > regs->lane_regs = &lane_regs_sc8280xp[0];
> > regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
> > break;
> Interesting, why do these match 8280xp and not, say, 8250?
> > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> > index 2680a9914765..dd28058e98a7 100644
> > --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> > +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> > @@ -354,6 +354,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> > case CAMSS_8650:
> > case CAMSS_8775P:
> > case CAMSS_X1E80100:
> > + case CAMSS_8150:
> Sort order here too
> > switch (sink_code) {
> > case MEDIA_BUS_FMT_YUYV8_1X16:
> > {
> > @@ -2010,6 +2011,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
> > case CAMSS_8280XP:
> > case CAMSS_8300:
> > case CAMSS_845:
> > + case CAMSS_8150:
> > case CAMSS_8550:
> > case CAMSS_8650:
> > case CAMSS_8775P:
> > [..]
>
>
> Thanks,
> ~val
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible
2026-11-04 20:54 ` [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible Andrew Gigena via B4 Relay
2026-11-04 22:41 ` Bryan O'Donoghue
@ 2026-11-04 23:12 ` Vladimir Zapolskiy
1 sibling, 0 replies; 13+ messages in thread
From: Vladimir Zapolskiy @ 2026-11-04 23:12 UTC (permalink / raw)
To: mail, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bryan O'Donoghue, Bjorn Andersson,
Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media
On 11/4/26 22:54, Andrew Gigena via B4 Relay wrote:
> From: Andrew Gigena <mail@andrewgigena.dev>
>
> Add qcom,sm8150-cci as a CCI v2 compatible, with qcom,msm8996-cci as
> the fallback.
>
> Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
> ---
> Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> index 1e8def25ec0e..b545fd2378da 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> @@ -39,6 +39,7 @@ properties:
> - qcom,shikra-cci
> - qcom,sm6150-cci
> - qcom,sm6350-cci
> + - qcom,sm8150-cci
> - qcom,sm8250-cci
> - qcom,sm8450-cci
> - qcom,sm8550-cci
>
Apart of the update to the list of compatibles it's expected to document
the clocks.
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS
2026-11-04 20:54 ` [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS Andrew Gigena via B4 Relay
2026-11-04 22:44 ` Bryan O'Donoghue
@ 2026-11-04 23:16 ` Vladimir Zapolskiy
2026-11-05 9:47 ` Bryan O'Donoghue
1 sibling, 1 reply; 13+ messages in thread
From: Vladimir Zapolskiy @ 2026-11-04 23:16 UTC (permalink / raw)
To: mail, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bryan O'Donoghue, Bjorn Andersson,
Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media
On 11/4/26 22:54, Andrew Gigena via B4 Relay wrote:
> From: Andrew Gigena <mail@andrewgigena.dev>
>
> Document the Qualcomm SM8150 Camera Subsystem. The IP integrates four
> CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite
> instances, with 42 clocks, 12 interrupts, eight IOMMU streams, four
> interconnect paths and three power domains.
>
> SM8150 has a different register layout, clock tree and power domain
> topology from SM8250, so describe it in a dedicated schema instead of
> using qcom,sm8250-camss as a fallback.
>
> Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
> ---
> .../bindings/media/qcom,sm8150-camss.yaml | 477 +++++++++++++++++++++
> 1 file changed, 477 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml
> new file mode 100644
> index 000000000000..a65067352b58
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml
> @@ -0,0 +1,477 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sm8150-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8150 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Andrew Gigena <mail@andrewgigena.dev>
> +
> +description: |
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,sm8150-camss
> +
> + clocks:
> + minItems: 42
> + maxItems: 42
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: camnoc_axi_src
> + - const: cpas_ahb
> + - const: cphy_rx_src
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy0_timer_src
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy1_timer_src
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy2_timer_src
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy3_timer_src
Please switch to the new model of describing and exploiting
the stand-alone CSI2 PHY devices.
Any CAMSS drivers based on the legacy description of CSIPHYs
should not be accepted into the upstream.
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] media: qcom: camss: Add support for SM8150
2026-11-04 20:54 ` [PATCH 3/4] media: qcom: camss: Add support for SM8150 Andrew Gigena via B4 Relay
2026-11-04 21:19 ` Val Packett
@ 2026-11-05 9:44 ` Bryan O'Donoghue
1 sibling, 0 replies; 13+ messages in thread
From: Bryan O'Donoghue @ 2026-11-05 9:44 UTC (permalink / raw)
To: mail, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media
On 04/11/2026 20:54, Andrew Gigena via B4 Relay wrote:
> The hardware reuses the existing 3-phase 1.0 CSIPHY, Gen2 CSID and
> VFE 17x implementations; the CSIPHY uses the SC8280XP lane register
> layout. Add CAMSS_8150 to the version enum and to the shared code
> paths, then add the per-block clock, regulator, power domain,
> interrupt and interconnect resources.
That's odd. sm8150 and sm8250 are proximate both seven nanometers
sc8280xp is five nanometers.
PHYs are about converting the analog to the digital domain and so
process geometery - ends up making a difference.
You can get the PHY init sequences here:
drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/
├── cam_csiphy_core.c
├── cam_csiphy_soc.c
├── cam_csiphy_dev.h
└── include/
├── cam_csiphy_1_0_hwreg.h sdm845
├── cam_csiphy_1_1_hwreg.h sm8150
├── cam_csiphy_1_2_hwreg.h sm7150
└── cam_csiphy_1_2_1_hwreg.h kona/sm8250
https://git.codelinaro.org/clo/la/platform/vendor/opensource/camera-kernel/-/blob/LA.AU.1.3.7-02900-gen3_gvmgh.0/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h?ref_type=tags
So yeah going by the name that's CSIPHY 1_1 same for sc8280xp and sm8150.
Hmm so much for my understanding of how dependant on process node these
sequences really are.. perhaps the PHYs area fully synthesizable in RTL,
probably.
Anyway.
The one thing to do here is to please _verify_ what's upstream now
against the tag provided there.
If there is a divergence then we need to upstream a 8150 compliant version.
...
Actually its fine, did the verification for you, the 1.1 init sequence
as is upstream is fine.
Just please tidy up the ordering of the 8150 switches.
---
bod
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS
2026-11-04 23:16 ` Vladimir Zapolskiy
@ 2026-11-05 9:47 ` Bryan O'Donoghue
0 siblings, 0 replies; 13+ messages in thread
From: Bryan O'Donoghue @ 2026-11-05 9:47 UTC (permalink / raw)
To: Vladimir Zapolskiy, mail, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Abel Vesa
Cc: linux-arm-msm, linux-i2c, devicetree, linux-kernel, linux-media
On 04/11/2026 23:16, Vladimir Zapolskiy wrote:
>> +maintainers:
>> + - Andrew Gigena <mail@andrewgigena.dev>
>> +
>> +description: |
>> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,sm8150-camss
>> +
>> + clocks:
>> + minItems: 42
>> + maxItems: 42
>> +
>> + clock-names:
>> + items:
>> + - const: camnoc_axi
>> + - const: camnoc_axi_src
>> + - const: cpas_ahb
>> + - const: cphy_rx_src
>> + - const: csiphy0
>> + - const: csiphy0_timer
>> + - const: csiphy0_timer_src
>> + - const: csiphy1
>> + - const: csiphy1_timer
>> + - const: csiphy1_timer_src
>> + - const: csiphy2
>> + - const: csiphy2_timer
>> + - const: csiphy2_timer_src
>> + - const: csiphy3
>> + - const: csiphy3_timer
>> + - const: csiphy3_timer_src
>
> Please switch to the new model of describing and exploiting
> the stand-alone CSI2 PHY devices.
>
> Any CAMSS drivers based on the legacy description of CSIPHYs
> should not be accepted into the upstream.
I mean we are just adding a new define for a SoC here - not a new init
sequence.
We could move all of sc8280xp, sm8150 and sm8250 to a new driver
topology but, I don't think that's a reasonable ask for a small change
like this from a new contributor.
Certainly would welcome the transition given above as a defined and neat
series but, I don't think there's a need for that to include this SoC in
100% existing infrastructure.
---
bod
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-11-05 9:47 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-11-04 20:54 [PATCH 0/4] media: qcom: camss: Add SM8150 CAMSS support Andrew Gigena via B4 Relay
2026-11-04 20:54 ` [PATCH 1/4] dt-bindings: i2c: qcom-cci: Document SM8150 compatible Andrew Gigena via B4 Relay
2026-11-04 22:41 ` Bryan O'Donoghue
2026-11-04 23:12 ` Vladimir Zapolskiy
2026-11-04 20:54 ` [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS Andrew Gigena via B4 Relay
2026-11-04 22:44 ` Bryan O'Donoghue
2026-11-04 23:16 ` Vladimir Zapolskiy
2026-11-05 9:47 ` Bryan O'Donoghue
2026-11-04 20:54 ` [PATCH 3/4] media: qcom: camss: Add support for SM8150 Andrew Gigena via B4 Relay
2026-11-04 21:19 ` Val Packett
2026-11-04 23:12 ` Andrew Gigena
2026-11-05 9:44 ` Bryan O'Donoghue
2026-11-04 20:54 ` [PATCH 4/4] arm64: dts: qcom: sm8150: Add CAMSS and CCI nodes Andrew Gigena via B4 Relay
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®