[PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms

[PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms

[David Heidelberg via B4 Relay]

Note: WIP tag added, as not everything from the previous review round has
been addressed.

# Short summary

This patch series extends the Qualcomm CAMSS (Camera Subsystem),
including CSID and CSIPHY components, to support C-PHY mode configuration.

# Background and motivation

Modern smartphone cameras increasingly rely on MIPI C-PHY rather than 
D-PHY, thanks to its higher data throughput and signal efficiency.
As a result, many OEMs adopt C-PHY interfaces for main (rear) cameras on
Qualcomm-based devices.

Until now, mainline Linux lacked C-PHY configuration support for Qualcomm
chipsets, preventing bring-up of primary camera sensors on several
Snapdragon platforms. This series closes that gap.

 - Introduces C-PHY configuration support for the CAMSS driver stack,
   covering both CSID and CSIPHY blocks.
 - Successfully enables C-PHY operation on the Snapdragon 845 platform.
 - Tested on OnePlus 6 and 6T phones running mainline Linux,
   using the Sony IMX519 main camera sensor.
 - The new configuration allows other chipsets versionsto enable C-PHY by
   simply adding corresponding sensor driver support and csiphy
   initialization data, following the example set for sdm845.

With this patch series, mainline Linux gains working C-PHY support for
Snapdragon 845, paving the way for improved main camera functionality
across many Qualcomm-based devices. The groundwork also simplifies
future enablement efforts for additional SoCs and sensors.

Until merged, the series will be also available at:
  https://codeberg.org/sdm845/linux/commits/branch/b4/qcom-cphy

Signed-off-by: David Heidelberg <david@ixit.cz>
---
Changes in v5:
- Split first patch enabling C-PHY part into last patch. (Bryan)
- Fix the camss_get_link_freq crash. (Cory)
- Dropped patch whitelisting C-PHY, instead use nullptr check. (Bryan)
- Dropped A-b/R-b from
 "media: qcom: camss: Initialize lanes after lane configuration is available"
 and changed Petr to Co-developed by and owned the patch.
- Link to v4: https://lore.kernel.org/r/20260301-qcom-cphy-v4-0-e53316d2cc65@ixit.cz

Changes in v4:
- Documented cphy parametr to camss_get_link_freq.
- Use BIT() macro for lane_mask. (Bryan)
- Correct lane_mask calculation. (Kieran + me)
- Removed comment for the D/C-PHY sequences init. (Bryan)
- Pass &csid->phy for calculate freq. (Bryan)
- Added missing cphy description to camss_get_link_freq. (kernel test robot)
- Gen2 v1.1 MIPI CSI-2 CPHY init hex to lowercase.
- Added back missed commit with improved electrical for sdm845 3ph.
- NOT addressed yet:
  - Proliferating special cases in switch statements on a per-SoC basis is verboten. 
  - is it possible to set clock_lane to say 0xff in DT ? 
- Link to v3: https://lore.kernel.org/r/20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz

Changes in v3:
- Make lanes_enable return sucess or error, since I couldn't move the
  configuration to the _init.
- Dropped R-b tags on
  "media: qcom: camss: Initialize lanes after lane configuration is available"
  as I changed formatting.
- Link to v2: https://lore.kernel.org/r/20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz

Changes in v2:
- This is still WIP patch series, thus I wanted to publish already
  changed parts to get feedback regarding to the direction of patchset.
- When switch to using odd bits, zeroed val which was left unitialized in v1.
- Accidentally missed archs added back in the commit moving lane regs to
  new location.
- Remove commit with reverting check for only D-PHY is supported and
  adjusted the check to also account for C-PHY.
- Documented link frequency calculation with defines. (Casey)
- Changed the cphy boolean to phy_cfg enum in the camss/camss-csiphy.
  (Brian)
- Added patch for csiphy-3ph enablement for sm7280 from Luca as I'm
  meanwhile trying to bring up the C-PHY sensor on FairPhone 5.
- Merged these two commits together
    csiphy-3ph: Enable sdm845 C-PHY sequence
    csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init
  merged R-b.
- Link to v1: https://lore.kernel.org/r/20251109-qcom-cphy-v1-0-165f7e79b0e1@ixit.cz

---
Casey Connolly (1):
      media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init

David Heidelberg (7):
      media: qcom: camss: csiphy: Introduce PHY configuration
      media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes
      media: qcom: camss: Prepare CSID for C-PHY support
      media: qcom: camss: Initialize lanes after lane configuration is available
      media: qcom: camss: csiphy-3ph: Update Gen2 v1.1 MIPI CSI-2 C-PHY init
      media: qcom: camss: Account for C-PHY when calculating link frequency
      media: qcom: camss: Enable C-PHY where available

Luca Weiss (1):
      media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 MIPI CSI-2 C-PHY init

 .../media/platform/qcom/camss/camss-csid-gen2.c    |   1 +
 drivers/media/platform/qcom/camss/camss-csid.c     |   8 +-
 drivers/media/platform/qcom/camss/camss-csid.h     |   1 +
 .../platform/qcom/camss/camss-csiphy-2ph-1-0.c     |   8 +-
 .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 355 ++++++++++++++++++---
 drivers/media/platform/qcom/camss/camss-csiphy.c   |  11 +-
 drivers/media/platform/qcom/camss/camss-csiphy.h   |   8 +-
 drivers/media/platform/qcom/camss/camss.c          |  36 ++-
 drivers/media/platform/qcom/camss/camss.h          |   2 +-
 9 files changed, 355 insertions(+), 75 deletions(-)
---
base-commit: e7d700e14934e68f86338c5610cf2ae76798b663
change-id: 20251109-qcom-cphy-bb8cbda1c644

Best regards,
-- 
David Heidelberg <david@ixit.cz>

[PATCH WIP v5 1/9] media: qcom: camss: csiphy: Introduce PHY configuration

[David Heidelberg via B4 Relay]

From: David Heidelberg <david@ixit.cz>

Read PHY configuration from the device-tree bus-type and save it into
the csiphy structure for later use.

For C-PHY, skip clock line configuration, as there is none.

Acked-by: Cory Keitz <ckeitz@amazon.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 drivers/media/platform/qcom/camss/camss-csiphy.h | 2 ++
 drivers/media/platform/qcom/camss/camss.c        | 8 ++++++--
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
index 9d9657b82f748..2ebb307be18ba 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.h
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
@@ -25,21 +25,23 @@
 
 struct csiphy_lane {
 	u8 pos;
 	u8 pol;
 };
 
 /**
  * struct csiphy_lanes_cfg - CSIPHY lanes configuration
+ * @phy_cfg:  interface selection (C-PHY or D-PHY)
  * @num_data: number of data lanes
  * @data:     data lanes configuration
  * @clk:      clock lane configuration (only for D-PHY)
  */
 struct csiphy_lanes_cfg {
+	enum v4l2_mbus_type phy_cfg;
 	int num_data;
 	struct csiphy_lane *data;
 	struct csiphy_lane clk;
 };
 
 struct csiphy_csi2_cfg {
 	struct csiphy_lanes_cfg lane_cfg;
 };
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 2123f6388e3d7..072c428e25166 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4761,19 +4761,23 @@ static int camss_parse_endpoint_node(struct device *dev,
 	if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) {
 		dev_err(dev, "Unsupported bus type %d\n", vep.bus_type);
 		return -EINVAL;
 	}
 
 	csd->interface.csiphy_id = vep.base.port;
 
 	mipi_csi2 = &vep.bus.mipi_csi2;
-	lncfg->clk.pos = mipi_csi2->clock_lane;
-	lncfg->clk.pol = mipi_csi2->lane_polarities[0];
 	lncfg->num_data = mipi_csi2->num_data_lanes;
+	lncfg->phy_cfg = vep.bus_type;
+
+	if (lncfg->phy_cfg != V4L2_MBUS_CSI2_CPHY) {
+		lncfg->clk.pos = mipi_csi2->clock_lane;
+		lncfg->clk.pol = mipi_csi2->lane_polarities[0];
+	}
 
 	lncfg->data = devm_kcalloc(dev,
 				   lncfg->num_data, sizeof(*lncfg->data),
 				   GFP_KERNEL);
 	if (!lncfg->data)
 		return -ENOMEM;
 
 	for (i = 0; i < lncfg->num_data; i++) {

-- 
2.53.0

[PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes

[David Heidelberg via B4 Relay]

From: David Heidelberg <david@ixit.cz>

So far, only D-PHY mode was supported, which uses even bits when enabling
or masking lanes. For C-PHY configuration, the hardware instead requires
using the odd bits.

Since there can be unrecognized configuration allow returning failure.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Cory Keitz <ckeitz@amazon.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 .../platform/qcom/camss/camss-csiphy-2ph-1-0.c     |  8 ++--
 .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 49 +++++++++++++++++-----
 drivers/media/platform/qcom/camss/camss-csiphy.c   |  5 +--
 drivers/media/platform/qcom/camss/camss-csiphy.h   |  6 +--
 4 files changed, 48 insertions(+), 20 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
index 9d67e7fa6366a..bb4b91f69616b 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
@@ -89,19 +89,19 @@ static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)
 	t_hs_settle = (t_hs_prepare_max + t_hs_prepare_zero_min) / 2;
 
 	timer_period = div_u64(1000000000000LL, timer_clk_rate);
 	settle_cnt = t_hs_settle / timer_period - 1;
 
 	return settle_cnt;
 }
 
-static void csiphy_lanes_enable(struct csiphy_device *csiphy,
-				struct csiphy_config *cfg,
-				s64 link_freq, u8 lane_mask)
+static int csiphy_lanes_enable(struct csiphy_device *csiphy,
+			       struct csiphy_config *cfg,
+			       s64 link_freq, u8 lane_mask)
 {
 	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
 	u8 settle_cnt;
 	u8 val, l = 0;
 	int i = 0;
 
 	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
 
@@ -127,16 +127,18 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
 			       CAMSS_CSI_PHY_LNn_CFG2(l));
 		writel_relaxed(settle_cnt, csiphy->base +
 			       CAMSS_CSI_PHY_LNn_CFG3(l));
 		writel_relaxed(0x3f, csiphy->base +
 			       CAMSS_CSI_PHY_INTERRUPT_MASKn(l));
 		writel_relaxed(0x3f, csiphy->base +
 			       CAMSS_CSI_PHY_INTERRUPT_CLEARn(l));
 	}
+
+	return 0;
 }
 
 static void csiphy_lanes_disable(struct csiphy_device *csiphy,
 				 struct csiphy_config *cfg)
 {
 	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
 	u8 l = 0;
 	int i = 0;
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index dac8d2ecf7995..d4624417a7424 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -9,16 +9,17 @@
  */
 
 #include "camss.h"
 #include "camss-csiphy.h"
 
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/media-bus-format.h>
 
 #define CSIPHY_3PH_LNn_CFG1(n)			(0x000 + 0x100 * (n))
 #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG	(BIT(7) | BIT(6))
 #define CSIPHY_3PH_LNn_CFG2(n)			(0x004 + 0x100 * (n))
 #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT	BIT(3)
 #define CSIPHY_3PH_LNn_CFG3(n)			(0x008 + 0x100 * (n))
 #define CSIPHY_3PH_LNn_CFG4(n)			(0x00c + 0x100 * (n))
 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS	0xa4
@@ -1108,23 +1109,32 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
 		writel_relaxed(val, csiphy->base + r->reg_addr);
 		if (r->delay_us)
 			udelay(r->delay_us);
 	}
 }
 
 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
 {
-	u8 lane_mask;
-	int i;
+	u8 lane_mask = 0;
 
-	lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
+	switch (lane_cfg->phy_cfg) {
+	case V4L2_MBUS_CSI2_CPHY:
+		for (int i = 0; i < lane_cfg->num_data; i++)
+			lane_mask |= BIT(lane_cfg->data[i].pos + 1);
+		break;
+	case V4L2_MBUS_CSI2_DPHY:
+		lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
 
-	for (i = 0; i < lane_cfg->num_data; i++)
-		lane_mask |= 1 << lane_cfg->data[i].pos;
+		for (int i = 0; i < lane_cfg->num_data; i++)
+			lane_mask |= BIT(lane_cfg->data[i].pos);
+		break;
+	default:
+		break;
+	}
 
 	return lane_mask;
 }
 
 static bool csiphy_is_gen2(u32 version)
 {
 	bool ret = false;
 
@@ -1143,31 +1153,46 @@ static bool csiphy_is_gen2(u32 version)
 	case CAMSS_X1E80100:
 		ret = true;
 		break;
 	}
 
 	return ret;
 }
 
-static void csiphy_lanes_enable(struct csiphy_device *csiphy,
-				struct csiphy_config *cfg,
-				s64 link_freq, u8 lane_mask)
+static int csiphy_lanes_enable(struct csiphy_device *csiphy,
+			       struct csiphy_config *cfg,
+			       s64 link_freq, u8 lane_mask)
 {
+	struct device *dev = csiphy->camss->dev;
 	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
 	struct csiphy_device_regs *regs = csiphy->regs;
 	u8 settle_cnt;
 	u8 val;
 	int i;
 
 	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
 
-	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
-	for (i = 0; i < c->num_data; i++)
-		val |= BIT(c->data[i].pos * 2);
+	val = 0;
+
+	switch (c->phy_cfg) {
+	case V4L2_MBUS_CSI2_CPHY:
+		for (i = 0; i < c->num_data; i++)
+			val |= BIT((c->data[i].pos * 2) + 1);
+		break;
+	case V4L2_MBUS_CSI2_DPHY:
+		val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
+
+		for (i = 0; i < c->num_data; i++)
+			val |= BIT(c->data[i].pos * 2);
+		break;
+	default:
+		dev_err(dev, "Unsupported bus type %d\n", c->phy_cfg);
+		return -EINVAL;
+	}
 
 	writel_relaxed(val, csiphy->base +
 		       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5));
 
 	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
 	writel_relaxed(val, csiphy->base +
 		       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6));
 
@@ -1184,16 +1209,18 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
 	else
 		csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt);
 
 	/* IRQ_MASK registers - disable all interrupts */
 	for (i = 11; i < 22; i++) {
 		writel_relaxed(0, csiphy->base +
 			       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i));
 	}
+
+	return 0;
 }
 
 static void csiphy_lanes_disable(struct csiphy_device *csiphy,
 				 struct csiphy_config *cfg)
 {
 	struct csiphy_device_regs *regs = csiphy->regs;
 
 	writel_relaxed(0, csiphy->base +
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
index 539ac4888b608..ec0dc9d31b585 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
@@ -260,16 +260,17 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on)
  * Helper function to enable streaming on CSIPHY module.
  * Main configuration of CSIPHY module is also done here.
  *
  * Return 0 on success or a negative error code otherwise
  */
 static int csiphy_stream_on(struct csiphy_device *csiphy)
 {
 	struct csiphy_config *cfg = &csiphy->cfg;
+	const struct csiphy_hw_ops *ops = csiphy->res->hw_ops;
 	s64 link_freq;
 	u8 lane_mask = csiphy->res->hw_ops->get_lane_mask(&cfg->csi2->lane_cfg);
 	u8 bpp = csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->formats->nformats,
 				csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
 	u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
 	u8 val;
 
 	link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
@@ -290,19 +291,17 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
 			val |= cfg->csid_id;
 		}
 		writel_relaxed(val, csiphy->base_clk_mux);
 
 		/* Enforce reg write ordering between clk mux & lane enabling */
 		wmb();
 	}
 
-	csiphy->res->hw_ops->lanes_enable(csiphy, cfg, link_freq, lane_mask);
-
-	return 0;
+	return ops->lanes_enable(csiphy, cfg, link_freq, lane_mask);
 }
 
 /*
  * csiphy_stream_off - Disable streaming on CSIPHY module
  * @csiphy: CSIPHY device
  *
  * Helper function to disable streaming on CSIPHY module
  */
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
index 2ebb307be18ba..42f0134635316 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.h
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
@@ -70,19 +70,19 @@ struct csiphy_hw_ops {
 	 * @lane_cfg - CSI2 lane configuration
 	 *
 	 * Return lane mask
 	 */
 	u8 (*get_lane_mask)(struct csiphy_lanes_cfg *lane_cfg);
 	void (*hw_version_read)(struct csiphy_device *csiphy,
 				struct device *dev);
 	void (*reset)(struct csiphy_device *csiphy);
-	void (*lanes_enable)(struct csiphy_device *csiphy,
-			     struct csiphy_config *cfg,
-			     s64 link_freq, u8 lane_mask);
+	int (*lanes_enable)(struct csiphy_device *csiphy,
+			    struct csiphy_config *cfg,
+			    s64 link_freq, u8 lane_mask);
 	void (*lanes_disable)(struct csiphy_device *csiphy,
 			      struct csiphy_config *cfg);
 	irqreturn_t (*isr)(int irq, void *dev);
 	int (*init)(struct csiphy_device *csiphy);
 };
 
 struct csiphy_subdev_resources {
 	u8 id;

-- 
2.53.0

[PATCH WIP v5 3/9] media: qcom: camss: Prepare CSID for C-PHY support

[David Heidelberg via B4 Relay]

From: David Heidelberg <david@ixit.cz>

Inherit C-PHY information from CSIPHY, so we can configure CSID
properly.

CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Cory Keitz <ckeitz@amazon.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 +
 drivers/media/platform/qcom/camss/camss-csid.c      | 1 +
 drivers/media/platform/qcom/camss/camss-csid.h      | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
index eadcb2f7e3aaa..52ef730b10553 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
@@ -178,16 +178,17 @@ static void __csid_configure_rx(struct csid_device *csid,
 	int val;
 
 	if (!lane_cnt)
 		lane_cnt = 4;
 
 	val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
 	val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
 	val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
+	val |= csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL;
 	writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
 
 	val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
 	if (vc > 3)
 		val |= 1 << CSI2_RX_CFG1_VC_MODE;
 	val |= 1 << CSI2_RX_CFG1_MISR_EN;
 	writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
 }
diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index 48459b46a981b..8d5c872f84ed5 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -1286,16 +1286,17 @@ static int csid_link_setup(struct media_entity *entity,
 			/* do no allow a link from CSIPHY to CSID */
 			if (!csiphy->cfg.csi2)
 				return -EPERM;
 
 			csid->phy.csiphy_id = csiphy->id;
 
 			lane_cfg = &csiphy->cfg.csi2->lane_cfg;
 			csid->phy.lane_cnt = lane_cfg->num_data;
+			csid->phy.cphy = (lane_cfg->phy_cfg == V4L2_MBUS_CSI2_CPHY);
 			csid->phy.lane_assign = csid_get_lane_assign(lane_cfg, lane_cfg->num_data);
 			csid->tpg_linked = false;
 		}
 	}
 	/* Decide which virtual channels to enable based on which source pads are enabled */
 	if (local->flags & MEDIA_PAD_FL_SOURCE) {
 		struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
 		struct csid_device *csid = v4l2_get_subdevdata(sd);
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index 5296b10f6bac8..00e2669db64c9 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -65,16 +65,17 @@ struct csid_testgen_config {
 };
 
 struct csid_phy_config {
 	u8 csiphy_id;
 	u8 lane_cnt;
 	u32 lane_assign;
 	u32 en_vc;
 	u8 need_vc_update;
+	bool cphy;
 };
 
 struct csid_device;
 
 struct csid_hw_ops {
 	/*
 	 * configure_stream - Configures and starts CSID input stream
 	 * @csid: CSID device

-- 
2.53.0

[PATCH WIP v5 4/9] media: qcom: camss: Initialize lanes after lane configuration is available

[David Heidelberg via B4 Relay]

From: David Heidelberg <david@ixit.cz>

The lanes must not be initialized before the driver has access to
the lane configuration, as it depends on whether D-PHY or C-PHY mode
is in use. Move the lane initialization to csiphy_lanes_enable which is
called when the configuration structures are available.

Co-developed-by: Petr Hodina <phodina@protonmail.com>
Signed-off-by: Petr Hodina <phodina@protonmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 133 +++++++++++++++------
 1 file changed, 95 insertions(+), 38 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index d4624417a7424..8bcba6107471f 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1164,16 +1164,110 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
 {
 	struct device *dev = csiphy->camss->dev;
 	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
 	struct csiphy_device_regs *regs = csiphy->regs;
 	u8 settle_cnt;
 	u8 val;
 	int i;
 
+	switch (csiphy->camss->res->version) {
+	case CAMSS_845:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_sdm845[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
+		}
+		break;
+	case CAMSS_2290:
+	case CAMSS_6150:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_qcm2290[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
+		}
+		break;
+	case CAMSS_6350:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_sm6350[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
+		}
+		break;
+	case CAMSS_7280:
+	case CAMSS_8250:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_sm8250[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
+		}
+		break;
+	case CAMSS_8280XP:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_sc8280xp[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
+		}
+		break;
+	case CAMSS_X1E80100:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_x1e80100[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
+		}
+		break;
+	case CAMSS_8550:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_sm8550[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
+		}
+		break;
+	case CAMSS_8650:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_sm8650[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
+		}
+		break;
+	case CAMSS_8300:
+	case CAMSS_8775P:
+		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+			regs->lane_regs = NULL;
+			regs->lane_array_size = 0;
+		} else {
+			regs->lane_regs = &lane_regs_sa8775p[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
+		}
+		break;
+	default:
+		break;
+	}
+
+	if (!regs->lane_regs && c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+		dev_err(dev, "Missing lane_regs definition for C-PHY\n");
+		return -EINVAL;
+	}
+
 	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
 
 	val = 0;
 
 	switch (c->phy_cfg) {
 	case V4L2_MBUS_CSI2_CPHY:
 		for (i = 0; i < c->num_data; i++)
 			val |= BIT((c->data[i].pos * 2) + 1);
@@ -1235,63 +1329,26 @@ static int csiphy_init(struct csiphy_device *csiphy)
 	struct device *dev = csiphy->camss->dev;
 	struct csiphy_device_regs *regs;
 
 	regs = devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL);
 	if (!regs)
 		return -ENOMEM;
 
 	csiphy->regs = regs;
-	regs->offset = 0x800;
 	regs->common_status_offset = 0xb0;
 
 	switch (csiphy->camss->res->version) {
-	case CAMSS_845:
-		regs->lane_regs = &lane_regs_sdm845[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
-		break;
-	case CAMSS_2290:
-	case CAMSS_6150:
-		regs->lane_regs = &lane_regs_qcm2290[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
-		break;
-	case CAMSS_6350:
-		regs->lane_regs = &lane_regs_sm6350[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
-		break;
-	case CAMSS_7280:
-	case CAMSS_8250:
-		regs->lane_regs = &lane_regs_sm8250[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
-		break;
-	case CAMSS_8280XP:
-		regs->lane_regs = &lane_regs_sc8280xp[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
-		break;
 	case CAMSS_X1E80100:
-		regs->lane_regs = &lane_regs_x1e80100[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
-		regs->offset = 0x1000;
-		break;
 	case CAMSS_8550:
-		regs->lane_regs = &lane_regs_sm8550[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
-		regs->offset = 0x1000;
-		break;
 	case CAMSS_8650:
-		regs->lane_regs = &lane_regs_sm8650[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
 		regs->offset = 0x1000;
 		break;
-	case CAMSS_8300:
-	case CAMSS_8775P:
-		regs->lane_regs = &lane_regs_sa8775p[0];
-		regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
-		break;
 	default:
+		regs->offset = 0x800;
 		break;
 	}
 
 	return 0;
 }
 
 const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
 	.get_lane_mask = csiphy_get_lane_mask,

-- 
2.53.0

[PATCH WIP v5 5/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init

[David Heidelberg via B4 Relay]

From: Casey Connolly <casey.connolly@linaro.org>

Add a PHY configuration sequence for the sdm845 which uses a Qualcomm
Gen 2 version 1.1 CSI-2 PHY.

The PHY can be configured as two phase or three phase in C-PHY or D-PHY
mode. This configuration supports three-phase C-PHY mode.

Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Acked-by: Cory Keitz <ckeitz@amazon.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Co-developed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 70 +++++++++++++++++++++-
 1 file changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 8bcba6107471f..d837fcf7cd2f0 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -141,16 +141,17 @@ csiphy_lane_regs lane_regs_sa8775p[] = {
 	{0x0460, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x065C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0660, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 };
 
 /* GEN2 1.0 2PH */
+/* 5 entries: clock + 4 lanes */
 static const struct
 csiphy_lane_regs lane_regs_sdm845[] = {
 	{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
@@ -215,16 +216,81 @@ csiphy_lane_regs lane_regs_sdm845[] = {
 	{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 	{0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 	{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 };
 
+/* GEN2 1.0 3PH */
+/* 3 entries: 3 lanes (C-PHY) */
+static const struct
+csiphy_lane_regs lane_regs_sdm845_3ph[] = {
+	{0x015c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x016c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+	{0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0124, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x01dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+	{0x035c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x036c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+	{0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0324, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x03dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+	{0x055c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x056c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+	{0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0524, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x052c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x05cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x05dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
 /* GEN2 1.1 2PH */
 static const struct
 csiphy_lane_regs lane_regs_sc8280xp[] = {
 	{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -1167,18 +1233,18 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
 	struct csiphy_device_regs *regs = csiphy->regs;
 	u8 settle_cnt;
 	u8 val;
 	int i;
 
 	switch (csiphy->camss->res->version) {
 	case CAMSS_845:
 		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
-			regs->lane_regs = NULL;
-			regs->lane_array_size = 0;
+			regs->lane_regs = &lane_regs_sdm845_3ph[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845_3ph);
 		} else {
 			regs->lane_regs = &lane_regs_sdm845[0];
 			regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
 		}
 		break;
 	case CAMSS_2290:
 	case CAMSS_6150:
 		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {

-- 
2.53.0

[PATCH WIP v5 6/9] media: qcom: camss: csiphy-3ph: Update Gen2 v1.1 MIPI CSI-2 C-PHY init

[David Heidelberg via B4 Relay]

From: David Heidelberg <david@ixit.cz>

These values should improve C-PHY behaviour. Should match most recent
Qualcomm code.

Acked-by: Cory Keitz <ckeitz@amazon.com>
Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 .../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c   | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index d837fcf7cd2f0..9a0f009c033bb 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -220,19 +220,19 @@ csiphy_lane_regs lane_regs_sdm845[] = {
 	{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 };
 
 /* GEN2 1.0 3PH */
 /* 3 entries: 3 lanes (C-PHY) */
 static const struct
 csiphy_lane_regs lane_regs_sdm845_3ph[] = {
-	{0x015c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
-	{0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
-	{0x016c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x015c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0168, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x016c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 	{0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 	{0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -240,19 +240,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] = {
 	{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x01dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
 
-	{0x035c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
-	{0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
-	{0x036c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x035c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0368, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x036c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 	{0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 	{0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -260,19 +260,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] = {
 	{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x03dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
 
-	{0x055c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
-	{0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
-	{0x056c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x055c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0568, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x056c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 	{0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 	{0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

-- 
2.53.0

[PATCH WIP v5 7/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 MIPI CSI-2 C-PHY init

[David Heidelberg via B4 Relay]

From: Luca Weiss <luca.weiss@fairphone.com>

Add a PHY configuration sequence for the sm8250 which uses a Qualcomm
Gen 2 version 1.2.1 CSI-2 PHY.

The PHY can be configured as two phase or three phase in C-PHY or D-PHY
mode. This configuration supports three-phase C-PHY mode.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Cory Keitz <ckeitz@amazon.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 111 ++++++++++++++++++++-
 1 file changed, 109 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 9a0f009c033bb..081060026975c 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -665,16 +665,123 @@ csiphy_lane_regs lane_regs_qcm2290[] = {
 	{0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 	{0x060C, 0xff, 0x00, CSIPHY_DNP_PARAMS},
 	{0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0638, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0664, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS},
 };
 
+/* GEN2 1.2.1 3PH */
+/* 3 entries: 3 lanes (C-PHY) */
+static const struct
+csiphy_lane_regs lane_regs_sm8250_3ph[] = {
+	{0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0998, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x098c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS},
+	{0x015c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+	{0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x018c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0124, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x01dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x09ac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x09b0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+	{0x0a90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS},
+	{0x035c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+	{0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x038c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0324, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x03dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0a80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0aac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0ab0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+	{0x0b90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS},
+	{0x055c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+	{0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+	{0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x058c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0524, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x052c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x05cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x05dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0b80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0bac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0bb0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
 /* GEN2 2.1.2 2PH DPHY mode */
 static const struct
 csiphy_lane_regs lane_regs_sm8550[] = {
 	{0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
 	{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -1262,18 +1369,18 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
 		} else {
 			regs->lane_regs = &lane_regs_sm6350[0];
 			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
 		}
 		break;
 	case CAMSS_7280:
 	case CAMSS_8250:
 		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
-			regs->lane_regs = NULL;
-			regs->lane_array_size = 0;
+			regs->lane_regs = &lane_regs_sm8250_3ph[0];
+			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250_3ph);
 		} else {
 			regs->lane_regs = &lane_regs_sm8250[0];
 			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
 		}
 		break;
 	case CAMSS_8280XP:
 		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
 			regs->lane_regs = NULL;

-- 
2.53.0

[PATCH WIP v5 8/9] media: qcom: camss: Account for C-PHY when calculating link frequency

[David Heidelberg via B4 Relay]

From: David Heidelberg <david@ixit.cz>

Ensure that the link frequency divider correctly accounts for C-PHY
operation. The divider differs between D-PHY and C-PHY, as described
in the MIPI CSI-2 specification.

For more details, see:
https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate

Suggested-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Cory Keitz <ckeitz@amazon.com>
Tested-by: Cory Keitz <ckeitz@amazon.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 drivers/media/platform/qcom/camss/camss-csid.c   |  7 +++++--
 drivers/media/platform/qcom/camss/camss-csiphy.c |  6 ++----
 drivers/media/platform/qcom/camss/camss.c        | 18 +++++++++++++++---
 drivers/media/platform/qcom/camss/camss.h        |  2 +-
 4 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index 8d5c872f84ed5..594f280a455ed 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -534,25 +534,28 @@ const struct csid_format_info *csid_get_fmt_entry(const struct csid_format_info
 
 /*
  * csid_set_clock_rates - Calculate and set clock rates on CSID module
  * @csiphy: CSID device
  */
 static int csid_set_clock_rates(struct csid_device *csid)
 {
 	struct device *dev = csid->camss->dev;
+	struct csiphy_device *csiphy = &csid->camss->csiphy[csid->phy.csiphy_id];
+	struct csiphy_lanes_cfg *lane_cfg = &csiphy->cfg.csi2->lane_cfg;
 	const struct csid_format_info *fmt;
+
 	s64 link_freq;
 	int i, j;
 	int ret;
 
 	fmt = csid_get_fmt_entry(csid->res->formats->formats, csid->res->formats->nformats,
 				 csid->fmt[MSM_CSIPHY_PAD_SINK].code);
-	link_freq = camss_get_link_freq(&csid->subdev.entity, fmt->bpp,
-					csid->phy.lane_cnt);
+
+	link_freq = camss_get_link_freq(&csid->subdev.entity, fmt->bpp, lane_cfg);
 	if (link_freq < 0)
 		link_freq = 0;
 
 	for (i = 0; i < csid->nclocks; i++) {
 		struct camss_clock *clock = &csid->clock[i];
 
 		if (!strcmp(clock->name, "csi0") ||
 		    !strcmp(clock->name, "csi1") ||
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
index ec0dc9d31b585..cd16743858d6a 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
@@ -138,19 +138,18 @@ static int csiphy_set_clock_rates(struct csiphy_device *csiphy)
 {
 	struct device *dev = csiphy->camss->dev;
 	s64 link_freq;
 	int i, j;
 	int ret;
 
 	u8 bpp = csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->formats->nformats,
 				csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
-	u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
 
-	link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
+	link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, &csiphy->cfg.csi2->lane_cfg);
 	if (link_freq < 0)
 		link_freq  = 0;
 
 	for (i = 0; i < csiphy->nclocks; i++) {
 		struct camss_clock *clock = &csiphy->clock[i];
 
 		if (csiphy->rate_set[i]) {
 			u64 min_rate = link_freq / 4;
@@ -265,20 +264,19 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on)
 static int csiphy_stream_on(struct csiphy_device *csiphy)
 {
 	struct csiphy_config *cfg = &csiphy->cfg;
 	const struct csiphy_hw_ops *ops = csiphy->res->hw_ops;
 	s64 link_freq;
 	u8 lane_mask = csiphy->res->hw_ops->get_lane_mask(&cfg->csi2->lane_cfg);
 	u8 bpp = csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->formats->nformats,
 				csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
-	u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
 	u8 val;
 
-	link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
+	link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, &csiphy->cfg.csi2->lane_cfg);
 
 	if (link_freq < 0) {
 		dev_err(csiphy->camss->dev,
 			"Cannot get CSI2 transmitter's link frequency\n");
 		return -EINVAL;
 	}
 
 	if (csiphy->base_clk_mux) {
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 072c428e25166..db4e14a84a95f 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -27,16 +27,24 @@
 #include <media/v4l2-mc.h>
 #include <media/v4l2-fwnode.h>
 
 #include "camss.h"
 
 #define CAMSS_CLOCK_MARGIN_NUMERATOR 105
 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
 
+/*
+ * C-PHY encodes data by 16/7 ~ 2.28 bits/symbol
+ * D-PHY doesn't encode data, thus 16/16 = 1 b/s
+ */
+#define CAMSS_COMMON_PHY_DIVIDENT 16
+#define CAMSS_CPHY_DIVISOR 7
+#define CAMSS_DPHY_DIVISOR 16
+
 static const struct parent_dev_ops vfe_parent_dev_ops;
 
 static const struct camss_subdev_resources csiphy_res_8x16[] = {
 	/* CSIPHY0 */
 	{
 		.regulators = {},
 		.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
 		.clock_rate = { { 0 },
@@ -4618,30 +4626,34 @@ struct media_pad *camss_find_sensor_pad(struct media_entity *entity)
 			return pad;
 	}
 }
 
 /**
  * camss_get_link_freq - Get link frequency from sensor
  * @entity: Media entity in the current pipeline
  * @bpp: Number of bits per pixel for the current format
- * @lanes: Number of lanes in the link to the sensor
+ * @lane_cfg: CSI2 lane configuration
  *
  * Return link frequency on success or a negative error code otherwise
  */
 s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
-			unsigned int lanes)
+			struct csiphy_lanes_cfg *lane_cfg)
 {
 	struct media_pad *sensor_pad;
+	u8 num_lanes = lane_cfg->num_data;
+	bool cphy = lane_cfg->phy_cfg == V4L2_MBUS_CSI2_CPHY;
+	unsigned int div = num_lanes * 2 * (cphy ? CAMSS_CPHY_DIVISOR :
+						     CAMSS_DPHY_DIVISOR);
 
 	sensor_pad = camss_find_sensor_pad(entity);
 	if (!sensor_pad)
 		return -ENODEV;
 
-	return v4l2_get_link_freq(sensor_pad, bpp, 2 * lanes);
+	return v4l2_get_link_freq(sensor_pad, CAMSS_COMMON_PHY_DIVIDENT * bpp, div);
 }
 
 /*
  * camss_get_pixel_clock - Get pixel clock rate from sensor
  * @entity: Media entity in the current pipeline
  * @pixel_clock: Received pixel clock value
  *
  * Return 0 on success or a negative error code otherwise
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 93d691c8ac63b..d65a9b62f7e66 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -164,17 +164,17 @@ struct parent_dev_ops {
 };
 
 void camss_add_clock_margin(u64 *rate);
 int camss_enable_clocks(int nclocks, struct camss_clock *clock,
 			struct device *dev);
 void camss_disable_clocks(int nclocks, struct camss_clock *clock);
 struct media_pad *camss_find_sensor_pad(struct media_entity *entity);
 s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
-			unsigned int lanes);
+			struct csiphy_lanes_cfg *lane_cfg);
 int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock);
 int camss_pm_domain_on(struct camss *camss, int id);
 void camss_pm_domain_off(struct camss *camss, int id);
 int camss_vfe_get(struct camss *camss, int id);
 void camss_vfe_put(struct camss *camss, int id);
 void camss_delete(struct camss *camss);
 void camss_buf_done(struct camss *camss, int hw_id, int port_id);
 void camss_reg_update(struct camss *camss, int hw_id,

-- 
2.53.0

[PATCH WIP v5 9/9] media: qcom: camss: Enable C-PHY where available

[David Heidelberg via B4 Relay]

From: David Heidelberg <david@ixit.cz>

After all the changes done we can now safely enable C-PHY for a SoC
where it's available.

Acked-by: Cory Keitz <ckeitz@amazon.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
 drivers/media/platform/qcom/camss/camss.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index db4e14a84a95f..555c53343a1e9 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4761,21 +4761,21 @@ static int camss_parse_endpoint_node(struct device *dev,
 	struct v4l2_fwnode_endpoint vep = { { 0 } };
 	unsigned int i;
 	int ret;
 
 	ret = v4l2_fwnode_endpoint_parse(ep, &vep);
 	if (ret)
 		return ret;
 
-	/*
-	 * Most SoCs support both D-PHY and C-PHY standards, but currently only
-	 * D-PHY is supported in the driver.
-	 */
-	if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) {
+	switch (vep.bus_type) {
+	case V4L2_MBUS_CSI2_CPHY:
+	case V4L2_MBUS_CSI2_DPHY:
+		break;
+	default:
 		dev_err(dev, "Unsupported bus type %d\n", vep.bus_type);
 		return -EINVAL;
 	}
 
 	csd->interface.csiphy_id = vep.base.port;
 
 	mipi_csi2 = &vep.bus.mipi_csi2;
 	lncfg->num_data = mipi_csi2->num_data_lanes;

-- 
2.53.0

Re: [PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes

[Sakari Ailus]

Hi David,

Thanks for the patch.

On Sun, May 31, 2026 at 03:08:10PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
> 
> So far, only D-PHY mode was supported, which uses even bits when enabling
> or masking lanes. For C-PHY configuration, the hardware instead requires
> using the odd bits.
> 
> Since there can be unrecognized configuration allow returning failure.
> 
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Acked-by: Cory Keitz <ckeitz@amazon.com>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
>  .../platform/qcom/camss/camss-csiphy-2ph-1-0.c     |  8 ++--
>  .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 49 +++++++++++++++++-----
>  drivers/media/platform/qcom/camss/camss-csiphy.c   |  5 +--
>  drivers/media/platform/qcom/camss/camss-csiphy.h   |  6 +--
>  4 files changed, 48 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
> index 9d67e7fa6366a..bb4b91f69616b 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
> @@ -89,19 +89,19 @@ static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)
>  	t_hs_settle = (t_hs_prepare_max + t_hs_prepare_zero_min) / 2;
>  
>  	timer_period = div_u64(1000000000000LL, timer_clk_rate);
>  	settle_cnt = t_hs_settle / timer_period - 1;
>  
>  	return settle_cnt;
>  }
>  
> -static void csiphy_lanes_enable(struct csiphy_device *csiphy,
> -				struct csiphy_config *cfg,
> -				s64 link_freq, u8 lane_mask)
> +static int csiphy_lanes_enable(struct csiphy_device *csiphy,
> +			       struct csiphy_config *cfg,
> +			       s64 link_freq, u8 lane_mask)
>  {
>  	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
>  	u8 settle_cnt;
>  	u8 val, l = 0;
>  	int i = 0;
>  
>  	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>  
> @@ -127,16 +127,18 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
>  			       CAMSS_CSI_PHY_LNn_CFG2(l));
>  		writel_relaxed(settle_cnt, csiphy->base +
>  			       CAMSS_CSI_PHY_LNn_CFG3(l));
>  		writel_relaxed(0x3f, csiphy->base +
>  			       CAMSS_CSI_PHY_INTERRUPT_MASKn(l));
>  		writel_relaxed(0x3f, csiphy->base +
>  			       CAMSS_CSI_PHY_INTERRUPT_CLEARn(l));
>  	}
> +
> +	return 0;
>  }
>  
>  static void csiphy_lanes_disable(struct csiphy_device *csiphy,
>  				 struct csiphy_config *cfg)
>  {
>  	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
>  	u8 l = 0;
>  	int i = 0;
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index dac8d2ecf7995..d4624417a7424 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -9,16 +9,17 @@
>   */
>  
>  #include "camss.h"
>  #include "camss-csiphy.h"
>  
>  #include <linux/delay.h>
>  #include <linux/interrupt.h>
>  #include <linux/io.h>
> +#include <linux/media-bus-format.h>
>  
>  #define CSIPHY_3PH_LNn_CFG1(n)			(0x000 + 0x100 * (n))
>  #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG	(BIT(7) | BIT(6))
>  #define CSIPHY_3PH_LNn_CFG2(n)			(0x004 + 0x100 * (n))
>  #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT	BIT(3)
>  #define CSIPHY_3PH_LNn_CFG3(n)			(0x008 + 0x100 * (n))
>  #define CSIPHY_3PH_LNn_CFG4(n)			(0x00c + 0x100 * (n))
>  #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS	0xa4
> @@ -1108,23 +1109,32 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
>  		writel_relaxed(val, csiphy->base + r->reg_addr);
>  		if (r->delay_us)
>  			udelay(r->delay_us);
>  	}
>  }
>  
>  static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
>  {
> -	u8 lane_mask;
> -	int i;
> +	u8 lane_mask = 0;
>  
> -	lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> +	switch (lane_cfg->phy_cfg) {
> +	case V4L2_MBUS_CSI2_CPHY:
> +		for (int i = 0; i < lane_cfg->num_data; i++)
> +			lane_mask |= BIT(lane_cfg->data[i].pos + 1);
> +		break;
> +	case V4L2_MBUS_CSI2_DPHY:
> +		lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
>  
> -	for (i = 0; i < lane_cfg->num_data; i++)
> -		lane_mask |= 1 << lane_cfg->data[i].pos;
> +		for (int i = 0; i < lane_cfg->num_data; i++)
> +			lane_mask |= BIT(lane_cfg->data[i].pos);
> +		break;
> +	default:
> +		break;
> +	}
>  
>  	return lane_mask;
>  }
>  
>  static bool csiphy_is_gen2(u32 version)
>  {
>  	bool ret = false;
>  
> @@ -1143,31 +1153,46 @@ static bool csiphy_is_gen2(u32 version)
>  	case CAMSS_X1E80100:
>  		ret = true;
>  		break;
>  	}
>  
>  	return ret;
>  }
>  
> -static void csiphy_lanes_enable(struct csiphy_device *csiphy,
> -				struct csiphy_config *cfg,
> -				s64 link_freq, u8 lane_mask)
> +static int csiphy_lanes_enable(struct csiphy_device *csiphy,
> +			       struct csiphy_config *cfg,
> +			       s64 link_freq, u8 lane_mask)
>  {
> +	struct device *dev = csiphy->camss->dev;
>  	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
>  	struct csiphy_device_regs *regs = csiphy->regs;
>  	u8 settle_cnt;
>  	u8 val;
>  	int i;
>  
>  	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>  
> -	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> -	for (i = 0; i < c->num_data; i++)
> -		val |= BIT(c->data[i].pos * 2);
> +	val = 0;
> +
> +	switch (c->phy_cfg) {
> +	case V4L2_MBUS_CSI2_CPHY:
> +		for (i = 0; i < c->num_data; i++)
> +			val |= BIT((c->data[i].pos * 2) + 1);
> +		break;
> +	case V4L2_MBUS_CSI2_DPHY:
> +		val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> +
> +		for (i = 0; i < c->num_data; i++)
> +			val |= BIT(c->data[i].pos * 2);
> +		break;
> +	default:
> +		dev_err(dev, "Unsupported bus type %d\n", c->phy_cfg);
> +		return -EINVAL;

If this is the only reason why you're changing the return type to int, I'd
suggest using WARN_ON() in this case. I presume it'd take a driver bug for
this to trigger?

> +	}
>  
>  	writel_relaxed(val, csiphy->base +
>  		       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5));
>  
>  	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
>  	writel_relaxed(val, csiphy->base +
>  		       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6));
>  
> @@ -1184,16 +1209,18 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
>  	else
>  		csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt);
>  
>  	/* IRQ_MASK registers - disable all interrupts */
>  	for (i = 11; i < 22; i++) {
>  		writel_relaxed(0, csiphy->base +
>  			       CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i));
>  	}
> +
> +	return 0;
>  }
>  
>  static void csiphy_lanes_disable(struct csiphy_device *csiphy,
>  				 struct csiphy_config *cfg)
>  {
>  	struct csiphy_device_regs *regs = csiphy->regs;
>  
>  	writel_relaxed(0, csiphy->base +
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
> index 539ac4888b608..ec0dc9d31b585 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
> @@ -260,16 +260,17 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on)
>   * Helper function to enable streaming on CSIPHY module.
>   * Main configuration of CSIPHY module is also done here.
>   *
>   * Return 0 on success or a negative error code otherwise
>   */
>  static int csiphy_stream_on(struct csiphy_device *csiphy)
>  {
>  	struct csiphy_config *cfg = &csiphy->cfg;
> +	const struct csiphy_hw_ops *ops = csiphy->res->hw_ops;
>  	s64 link_freq;
>  	u8 lane_mask = csiphy->res->hw_ops->get_lane_mask(&cfg->csi2->lane_cfg);
>  	u8 bpp = csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->formats->nformats,
>  				csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
>  	u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
>  	u8 val;
>  
>  	link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
> @@ -290,19 +291,17 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
>  			val |= cfg->csid_id;
>  		}
>  		writel_relaxed(val, csiphy->base_clk_mux);
>  
>  		/* Enforce reg write ordering between clk mux & lane enabling */
>  		wmb();
>  	}
>  
> -	csiphy->res->hw_ops->lanes_enable(csiphy, cfg, link_freq, lane_mask);
> -
> -	return 0;
> +	return ops->lanes_enable(csiphy, cfg, link_freq, lane_mask);
>  }
>  
>  /*
>   * csiphy_stream_off - Disable streaming on CSIPHY module
>   * @csiphy: CSIPHY device
>   *
>   * Helper function to disable streaming on CSIPHY module
>   */
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
> index 2ebb307be18ba..42f0134635316 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy.h
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
> @@ -70,19 +70,19 @@ struct csiphy_hw_ops {
>  	 * @lane_cfg - CSI2 lane configuration
>  	 *
>  	 * Return lane mask
>  	 */
>  	u8 (*get_lane_mask)(struct csiphy_lanes_cfg *lane_cfg);
>  	void (*hw_version_read)(struct csiphy_device *csiphy,
>  				struct device *dev);
>  	void (*reset)(struct csiphy_device *csiphy);
> -	void (*lanes_enable)(struct csiphy_device *csiphy,
> -			     struct csiphy_config *cfg,
> -			     s64 link_freq, u8 lane_mask);
> +	int (*lanes_enable)(struct csiphy_device *csiphy,
> +			    struct csiphy_config *cfg,
> +			    s64 link_freq, u8 lane_mask);
>  	void (*lanes_disable)(struct csiphy_device *csiphy,
>  			      struct csiphy_config *cfg);
>  	irqreturn_t (*isr)(int irq, void *dev);
>  	int (*init)(struct csiphy_device *csiphy);
>  };
>  
>  struct csiphy_subdev_resources {
>  	u8 id;
> 

-- 
Kind regards,

Sakari Ailus

Re: [PATCH WIP v5 4/9] media: qcom: camss: Initialize lanes after lane configuration is available

[Sakari Ailus]

Hi David,

On Sun, May 31, 2026 at 03:08:12PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
> 
> The lanes must not be initialized before the driver has access to
> the lane configuration, as it depends on whether D-PHY or C-PHY mode
> is in use. Move the lane initialization to csiphy_lanes_enable which is
> called when the configuration structures are available.
> 
> Co-developed-by: Petr Hodina <phodina@protonmail.com>
> Signed-off-by: Petr Hodina <phodina@protonmail.com>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
>  .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 133 +++++++++++++++------
>  1 file changed, 95 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index d4624417a7424..8bcba6107471f 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -1164,16 +1164,110 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
>  {
>  	struct device *dev = csiphy->camss->dev;
>  	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
>  	struct csiphy_device_regs *regs = csiphy->regs;
>  	u8 settle_cnt;
>  	u8 val;
>  	int i;
>  
> +	switch (csiphy->camss->res->version) {
> +	case CAMSS_845:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;

Aren't these fields already initialised to 0?

Using the compatible string to assign these using device matching would be
nice if possible.

> +		} else {
> +			regs->lane_regs = &lane_regs_sdm845[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
> +		}
> +		break;
> +	case CAMSS_2290:
> +	case CAMSS_6150:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;
> +		} else {
> +			regs->lane_regs = &lane_regs_qcm2290[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
> +		}
> +		break;
> +	case CAMSS_6350:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;
> +		} else {
> +			regs->lane_regs = &lane_regs_sm6350[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
> +		}
> +		break;
> +	case CAMSS_7280:
> +	case CAMSS_8250:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;
> +		} else {
> +			regs->lane_regs = &lane_regs_sm8250[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
> +		}
> +		break;
> +	case CAMSS_8280XP:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;
> +		} else {
> +			regs->lane_regs = &lane_regs_sc8280xp[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
> +		}
> +		break;
> +	case CAMSS_X1E80100:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;
> +		} else {
> +			regs->lane_regs = &lane_regs_x1e80100[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
> +		}
> +		break;
> +	case CAMSS_8550:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;
> +		} else {
> +			regs->lane_regs = &lane_regs_sm8550[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
> +		}
> +		break;
> +	case CAMSS_8650:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;
> +		} else {
> +			regs->lane_regs = &lane_regs_sm8650[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
> +		}
> +		break;
> +	case CAMSS_8300:
> +	case CAMSS_8775P:
> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +			regs->lane_regs = NULL;
> +			regs->lane_array_size = 0;
> +		} else {
> +			regs->lane_regs = &lane_regs_sa8775p[0];
> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> +		}
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	if (!regs->lane_regs && c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
> +		dev_err(dev, "Missing lane_regs definition for C-PHY\n");
> +		return -EINVAL;
> +	}
> +
>  	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>  
>  	val = 0;
>  
>  	switch (c->phy_cfg) {
>  	case V4L2_MBUS_CSI2_CPHY:
>  		for (i = 0; i < c->num_data; i++)
>  			val |= BIT((c->data[i].pos * 2) + 1);
> @@ -1235,63 +1329,26 @@ static int csiphy_init(struct csiphy_device *csiphy)
>  	struct device *dev = csiphy->camss->dev;
>  	struct csiphy_device_regs *regs;
>  
>  	regs = devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL);
>  	if (!regs)
>  		return -ENOMEM;
>  
>  	csiphy->regs = regs;
> -	regs->offset = 0x800;
>  	regs->common_status_offset = 0xb0;
>  
>  	switch (csiphy->camss->res->version) {
> -	case CAMSS_845:
> -		regs->lane_regs = &lane_regs_sdm845[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
> -		break;
> -	case CAMSS_2290:
> -	case CAMSS_6150:
> -		regs->lane_regs = &lane_regs_qcm2290[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
> -		break;
> -	case CAMSS_6350:
> -		regs->lane_regs = &lane_regs_sm6350[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
> -		break;
> -	case CAMSS_7280:
> -	case CAMSS_8250:
> -		regs->lane_regs = &lane_regs_sm8250[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
> -		break;
> -	case CAMSS_8280XP:
> -		regs->lane_regs = &lane_regs_sc8280xp[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
> -		break;
>  	case CAMSS_X1E80100:
> -		regs->lane_regs = &lane_regs_x1e80100[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
> -		regs->offset = 0x1000;
> -		break;
>  	case CAMSS_8550:
> -		regs->lane_regs = &lane_regs_sm8550[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
> -		regs->offset = 0x1000;
> -		break;
>  	case CAMSS_8650:
> -		regs->lane_regs = &lane_regs_sm8650[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
>  		regs->offset = 0x1000;
>  		break;
> -	case CAMSS_8300:
> -	case CAMSS_8775P:
> -		regs->lane_regs = &lane_regs_sa8775p[0];
> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> -		break;
>  	default:
> +		regs->offset = 0x800;
>  		break;
>  	}
>  
>  	return 0;
>  }
>  
>  const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
>  	.get_lane_mask = csiphy_get_lane_mask,
> 
> -- 
> 2.53.0
> 
> 

-- 
Sakari Ailus

Re: [PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes

[David Heidelberg]

On 01/06/2026 10:49, Sakari Ailus wrote:
> Hi David,
> 
> Thanks for the patch.
> 
> On Sun, May 31, 2026 at 03:08:10PM +0200, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> So far, only D-PHY mode was supported, which uses even bits when enabling
>> or masking lanes. For C-PHY configuration, the hardware instead requires
>> using the odd bits.
>>
>> Since there can be unrecognized configuration allow returning failure.
>>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>> Acked-by: Cory Keitz <ckeitz@amazon.com>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>>   .../platform/qcom/camss/camss-csiphy-2ph-1-0.c     |  8 ++--
>>   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 49 +++++++++++++++++-----
>>   drivers/media/platform/qcom/camss/camss-csiphy.c   |  5 +--
>>   drivers/media/platform/qcom/camss/camss-csiphy.h   |  6 +--
>>   4 files changed, 48 insertions(+), 20 deletions(-)
>>

[...]

>> -static void csiphy_lanes_enable(struct csiphy_device *csiphy,
>> -				struct csiphy_config *cfg,
>> -				s64 link_freq, u8 lane_mask)
>> +static int csiphy_lanes_enable(struct csiphy_device *csiphy,
>> +			       struct csiphy_config *cfg,
>> +			       s64 link_freq, u8 lane_mask)
>>   {
>> +	struct device *dev = csiphy->camss->dev;
>>   	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
>>   	struct csiphy_device_regs *regs = csiphy->regs;
>>   	u8 settle_cnt;
>>   	u8 val;
>>   	int i;
>>   
>>   	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>>   
>> -	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
>> -	for (i = 0; i < c->num_data; i++)
>> -		val |= BIT(c->data[i].pos * 2);
>> +	val = 0;
>> +
>> +	switch (c->phy_cfg) {
>> +	case V4L2_MBUS_CSI2_CPHY:
>> +		for (i = 0; i < c->num_data; i++)
>> +			val |= BIT((c->data[i].pos * 2) + 1);
>> +		break;
>> +	case V4L2_MBUS_CSI2_DPHY:
>> +		val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
>> +
>> +		for (i = 0; i < c->num_data; i++)
>> +			val |= BIT(c->data[i].pos * 2);
>> +		break;
>> +	default:
>> +		dev_err(dev, "Unsupported bus type %d\n", c->phy_cfg);
>> +		return -EINVAL;
> 
> If this is the only reason why you're changing the return type to int, I'd
> suggest using WARN_ON() in this case. I presume it'd take a driver bug for
> this to trigger?

Thank you for the review.

If others agree, I would also prefer WARN_ON instead of changing return values.

David

[...]

Re: [PATCH WIP v5 4/9] media: qcom: camss: Initialize lanes after lane configuration is available

[David Heidelberg]

On 01/06/2026 11:00, Sakari Ailus wrote:
> Hi David,
> 
> On Sun, May 31, 2026 at 03:08:12PM +0200, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> The lanes must not be initialized before the driver has access to
>> the lane configuration, as it depends on whether D-PHY or C-PHY mode
>> is in use. Move the lane initialization to csiphy_lanes_enable which is
>> called when the configuration structures are available.
>>
>> Co-developed-by: Petr Hodina <phodina@protonmail.com>
>> Signed-off-by: Petr Hodina <phodina@protonmail.com>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>>   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 133 +++++++++++++++------
>>   1 file changed, 95 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> index d4624417a7424..8bcba6107471f 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> @@ -1164,16 +1164,110 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
>>   {
>>   	struct device *dev = csiphy->camss->dev;
>>   	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
>>   	struct csiphy_device_regs *regs = csiphy->regs;
>>   	u8 settle_cnt;
>>   	u8 val;
>>   	int i;
>>   
>> +	switch (csiphy->camss->res->version) {
>> +	case CAMSS_845:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
> 
> Aren't these fields already initialised to 0?

I assume yes, but I wanted to be more explicit here so it's more obvious that 
C-PHY sequences are missing (until these get filled in by users).

> 
> Using the compatible string to assign these using device matching would be
> nice if possible.

Sure, thou if not explicitly requested, I would prefer to do minimal changes 
above the C-PHY itself introduction (it's pretty much breaking with every CAMSS 
version addition). I can do it as follow up, if wanted.

David

> 
>> +		} else {
>> +			regs->lane_regs = &lane_regs_sdm845[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
>> +		}
>> +		break;
>> +	case CAMSS_2290:
>> +	case CAMSS_6150:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
>> +		} else {
>> +			regs->lane_regs = &lane_regs_qcm2290[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
>> +		}
>> +		break;
>> +	case CAMSS_6350:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
>> +		} else {
>> +			regs->lane_regs = &lane_regs_sm6350[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
>> +		}
>> +		break;
>> +	case CAMSS_7280:
>> +	case CAMSS_8250:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
>> +		} else {
>> +			regs->lane_regs = &lane_regs_sm8250[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
>> +		}
>> +		break;
>> +	case CAMSS_8280XP:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
>> +		} else {
>> +			regs->lane_regs = &lane_regs_sc8280xp[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
>> +		}
>> +		break;
>> +	case CAMSS_X1E80100:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
>> +		} else {
>> +			regs->lane_regs = &lane_regs_x1e80100[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
>> +		}
>> +		break;
>> +	case CAMSS_8550:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
>> +		} else {
>> +			regs->lane_regs = &lane_regs_sm8550[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
>> +		}
>> +		break;
>> +	case CAMSS_8650:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
>> +		} else {
>> +			regs->lane_regs = &lane_regs_sm8650[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
>> +		}
>> +		break;
>> +	case CAMSS_8300:
>> +	case CAMSS_8775P:
>> +		if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +			regs->lane_regs = NULL;
>> +			regs->lane_array_size = 0;
>> +		} else {
>> +			regs->lane_regs = &lane_regs_sa8775p[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
>> +		}
>> +		break;
>> +	default:
>> +		break;
>> +	}
>> +
>> +	if (!regs->lane_regs && c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> +		dev_err(dev, "Missing lane_regs definition for C-PHY\n");
>> +		return -EINVAL;
>> +	}
>> +
>>   	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>>   
>>   	val = 0;
>>   
>>   	switch (c->phy_cfg) {
>>   	case V4L2_MBUS_CSI2_CPHY:
>>   		for (i = 0; i < c->num_data; i++)
>>   			val |= BIT((c->data[i].pos * 2) + 1);
>> @@ -1235,63 +1329,26 @@ static int csiphy_init(struct csiphy_device *csiphy)
>>   	struct device *dev = csiphy->camss->dev;
>>   	struct csiphy_device_regs *regs;
>>   
>>   	regs = devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL);
>>   	if (!regs)
>>   		return -ENOMEM;
>>   
>>   	csiphy->regs = regs;
>> -	regs->offset = 0x800;
>>   	regs->common_status_offset = 0xb0;
>>   
>>   	switch (csiphy->camss->res->version) {
>> -	case CAMSS_845:
>> -		regs->lane_regs = &lane_regs_sdm845[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
>> -		break;
>> -	case CAMSS_2290:
>> -	case CAMSS_6150:
>> -		regs->lane_regs = &lane_regs_qcm2290[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
>> -		break;
>> -	case CAMSS_6350:
>> -		regs->lane_regs = &lane_regs_sm6350[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
>> -		break;
>> -	case CAMSS_7280:
>> -	case CAMSS_8250:
>> -		regs->lane_regs = &lane_regs_sm8250[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
>> -		break;
>> -	case CAMSS_8280XP:
>> -		regs->lane_regs = &lane_regs_sc8280xp[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
>> -		break;
>>   	case CAMSS_X1E80100:
>> -		regs->lane_regs = &lane_regs_x1e80100[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
>> -		regs->offset = 0x1000;
>> -		break;
>>   	case CAMSS_8550:
>> -		regs->lane_regs = &lane_regs_sm8550[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
>> -		regs->offset = 0x1000;
>> -		break;
>>   	case CAMSS_8650:
>> -		regs->lane_regs = &lane_regs_sm8650[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
>>   		regs->offset = 0x1000;
>>   		break;
>> -	case CAMSS_8300:
>> -	case CAMSS_8775P:
>> -		regs->lane_regs = &lane_regs_sa8775p[0];
>> -		regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
>> -		break;
>>   	default:
>> +		regs->offset = 0x800;
>>   		break;
>>   	}
>>   
>>   	return 0;
>>   }
>>   
>>   const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
>>   	.get_lane_mask = csiphy_get_lane_mask,
>>
>> -- 
>> 2.53.0
>>
>>
> 

-- 
David Heidelberg

Re: [PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms

[Bryan O'Donoghue]

On 31/05/2026 14:08, David Heidelberg via B4 Relay wrote:
> Note: WIP tag added, as not everything from the previous review round has
> been addressed.
> 
> # Short summary
> 
> This patch series extends the Qualcomm CAMSS (Camera Subsystem),
> including CSID and CSIPHY components, to support C-PHY mode configuration.
> 
> # Background and motivation
> 
> Modern smartphone cameras increasingly rely on MIPI C-PHY rather than
> D-PHY, thanks to its higher data throughput and signal efficiency.
> As a result, many OEMs adopt C-PHY interfaces for main (rear) cameras on
> Qualcomm-based devices.
> 
> Until now, mainline Linux lacked C-PHY configuration support for Qualcomm
> chipsets, preventing bring-up of primary camera sensors on several
> Snapdragon platforms. This series closes that gap.
> 
>   - Introduces C-PHY configuration support for the CAMSS driver stack,
>     covering both CSID and CSIPHY blocks.
>   - Successfully enables C-PHY operation on the Snapdragon 845 platform.
>   - Tested on OnePlus 6 and 6T phones running mainline Linux,
>     using the Sony IMX519 main camera sensor.
>   - The new configuration allows other chipsets versionsto enable C-PHY by
>     simply adding corresponding sensor driver support and csiphy
>     initialization data, following the example set for sdm845.
> 
> With this patch series, mainline Linux gains working C-PHY support for
> Snapdragon 845, paving the way for improved main camera functionality
> across many Qualcomm-based devices. The groundwork also simplifies
> future enablement efforts for additional SoCs and sensors.
> 
> Until merged, the series will be also available at:
>    https://codeberg.org/sdm845/linux/commits/branch/b4/qcom-cphy
> 
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> Changes in v5:
> - Split first patch enabling C-PHY part into last patch. (Bryan)
> - Fix the camss_get_link_freq crash. (Cory)
> - Dropped patch whitelisting C-PHY, instead use nullptr check. (Bryan)
> - Dropped A-b/R-b from
>   "media: qcom: camss: Initialize lanes after lane configuration is available"
>   and changed Petr to Co-developed by and owned the patch.
> - Link to v4: https://lore.kernel.org/r/20260301-qcom-cphy-v4-0-e53316d2cc65@ixit.cz
> 
> Changes in v4:
> - Documented cphy parametr to camss_get_link_freq.
> - Use BIT() macro for lane_mask. (Bryan)
> - Correct lane_mask calculation. (Kieran + me)
> - Removed comment for the D/C-PHY sequences init. (Bryan)
> - Pass &csid->phy for calculate freq. (Bryan)
> - Added missing cphy description to camss_get_link_freq. (kernel test robot)
> - Gen2 v1.1 MIPI CSI-2 CPHY init hex to lowercase.
> - Added back missed commit with improved electrical for sdm845 3ph.
> - NOT addressed yet:
>    - Proliferating special cases in switch statements on a per-SoC basis is verboten.
>    - is it possible to set clock_lane to say 0xff in DT ?
> - Link to v3: https://lore.kernel.org/r/20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz
> 
> Changes in v3:
> - Make lanes_enable return sucess or error, since I couldn't move the
>    configuration to the _init.
> - Dropped R-b tags on
>    "media: qcom: camss: Initialize lanes after lane configuration is available"
>    as I changed formatting.
> - Link to v2: https://lore.kernel.org/r/20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz
> 
> Changes in v2:
> - This is still WIP patch series, thus I wanted to publish already
>    changed parts to get feedback regarding to the direction of patchset.
> - When switch to using odd bits, zeroed val which was left unitialized in v1.
> - Accidentally missed archs added back in the commit moving lane regs to
>    new location.
> - Remove commit with reverting check for only D-PHY is supported and
>    adjusted the check to also account for C-PHY.
> - Documented link frequency calculation with defines. (Casey)
> - Changed the cphy boolean to phy_cfg enum in the camss/camss-csiphy.
>    (Brian)
> - Added patch for csiphy-3ph enablement for sm7280 from Luca as I'm
>    meanwhile trying to bring up the C-PHY sensor on FairPhone 5.
> - Merged these two commits together
>      csiphy-3ph: Enable sdm845 C-PHY sequence
>      csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init
>    merged R-b.
> - Link to v1: https://lore.kernel.org/r/20251109-qcom-cphy-v1-0-165f7e79b0e1@ixit.cz
> 
> ---
> Casey Connolly (1):
>        media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init
> 
> David Heidelberg (7):
>        media: qcom: camss: csiphy: Introduce PHY configuration
>        media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes
>        media: qcom: camss: Prepare CSID for C-PHY support
>        media: qcom: camss: Initialize lanes after lane configuration is available
>        media: qcom: camss: csiphy-3ph: Update Gen2 v1.1 MIPI CSI-2 C-PHY init
>        media: qcom: camss: Account for C-PHY when calculating link frequency
>        media: qcom: camss: Enable C-PHY where available
> 
> Luca Weiss (1):
>        media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 MIPI CSI-2 C-PHY init
> 
>   .../media/platform/qcom/camss/camss-csid-gen2.c    |   1 +
>   drivers/media/platform/qcom/camss/camss-csid.c     |   8 +-
>   drivers/media/platform/qcom/camss/camss-csid.h     |   1 +
>   .../platform/qcom/camss/camss-csiphy-2ph-1-0.c     |   8 +-
>   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 355 ++++++++++++++++++---
>   drivers/media/platform/qcom/camss/camss-csiphy.c   |  11 +-
>   drivers/media/platform/qcom/camss/camss-csiphy.h   |   8 +-
>   drivers/media/platform/qcom/camss/camss.c          |  36 ++-
>   drivers/media/platform/qcom/camss/camss.h          |   2 +-
>   9 files changed, 355 insertions(+), 75 deletions(-)
> ---
> base-commit: e7d700e14934e68f86338c5610cf2ae76798b663
> change-id: 20251109-qcom-cphy-bb8cbda1c644
> 
> Best regards,
> --
> David Heidelberg <david@ixit.cz>
> 
> 
> 

It feels to me that the standalone PHY is pretty far alone by now.

Its totally up to you BUT if you are up for the effort and BTW thank you 
for taking personal time to work on this but, how would you feel about 
basing this series on top of the standalone DPHY series ?

---
bod

Re: [PATCH WIP v5 1/9] media: qcom: camss: csiphy: Introduce PHY configuration

[Bryan O'Donoghue]

On 31/05/2026 14:08, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
> 
> Read PHY configuration from the device-tree bus-type and save it into
> the csiphy structure for later use.
> 
> For C-PHY, skip clock line configuration, as there is none.
> 
> Acked-by: Cory Keitz <ckeitz@amazon.com>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
>   drivers/media/platform/qcom/camss/camss-csiphy.h | 2 ++
>   drivers/media/platform/qcom/camss/camss.c        | 8 ++++++--
>   2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
> index 9d9657b82f748..2ebb307be18ba 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy.h
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
> @@ -25,21 +25,23 @@
> 
>   struct csiphy_lane {
>   	u8 pos;
>   	u8 pol;
>   };
> 
>   /**
>    * struct csiphy_lanes_cfg - CSIPHY lanes configuration
> + * @phy_cfg:  interface selection (C-PHY or D-PHY)
>    * @num_data: number of data lanes
>    * @data:     data lanes configuration
>    * @clk:      clock lane configuration (only for D-PHY)
>    */
>   struct csiphy_lanes_cfg {
> +	enum v4l2_mbus_type phy_cfg;
>   	int num_data;
>   	struct csiphy_lane *data;
>   	struct csiphy_lane clk;
>   };
> 
>   struct csiphy_csi2_cfg {
>   	struct csiphy_lanes_cfg lane_cfg;
>   };
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 2123f6388e3d7..072c428e25166 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -4761,19 +4761,23 @@ static int camss_parse_endpoint_node(struct device *dev,
>   	if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) {
>   		dev_err(dev, "Unsupported bus type %d\n", vep.bus_type);
>   		return -EINVAL;
>   	}
> 
>   	csd->interface.csiphy_id = vep.base.port;
> 
>   	mipi_csi2 = &vep.bus.mipi_csi2;
> -	lncfg->clk.pos = mipi_csi2->clock_lane;
> -	lncfg->clk.pol = mipi_csi2->lane_polarities[0];
>   	lncfg->num_data = mipi_csi2->num_data_lanes;
> +	lncfg->phy_cfg = vep.bus_type;
> +
> +	if (lncfg->phy_cfg != V4L2_MBUS_CSI2_CPHY) {
> +		lncfg->clk.pos = mipi_csi2->clock_lane;
> +		lncfg->clk.pol = mipi_csi2->lane_polarities[0];
> +	}
> 
>   	lncfg->data = devm_kcalloc(dev,
>   				   lncfg->num_data, sizeof(*lncfg->data),
>   				   GFP_KERNEL);
>   	if (!lncfg->data)
>   		return -ENOMEM;
> 
>   	for (i = 0; i < lncfg->num_data; i++) {
> 
> --
> 2.53.0
> 
> 
> 

Reviewed-by: Bryan O'Donoghue <bod@kernel.org>

---
bod

Re: [PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes

[Bryan O'Donoghue]

On 01/06/2026 13:48, David Heidelberg wrote:
> On 01/06/2026 10:49, Sakari Ailus wrote:
>> Hi David,
>>
>> Thanks for the patch.
>>
>> On Sun, May 31, 2026 at 03:08:10PM +0200, David Heidelberg via B4 Relay wrote:
>>> From: David Heidelberg <david@ixit.cz>
>>>
>>> So far, only D-PHY mode was supported, which uses even bits when enabling
>>> or masking lanes. For C-PHY configuration, the hardware instead requires
>>> using the odd bits.
>>>
>>> Since there can be unrecognized configuration allow returning failure.
>>>
>>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>>> Acked-by: Cory Keitz <ckeitz@amazon.com>
>>> Signed-off-by: David Heidelberg <david@ixit.cz>
>>> ---
>>>    .../platform/qcom/camss/camss-csiphy-2ph-1-0.c     |  8 ++--
>>>    .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 49 +++++++++++++++++-----
>>>    drivers/media/platform/qcom/camss/camss-csiphy.c   |  5 +--
>>>    drivers/media/platform/qcom/camss/camss-csiphy.h   |  6 +--
>>>    4 files changed, 48 insertions(+), 20 deletions(-)
>>>
> 
> [...]
> 
>>> -static void csiphy_lanes_enable(struct csiphy_device *csiphy,
>>> -				struct csiphy_config *cfg,
>>> -				s64 link_freq, u8 lane_mask)
>>> +static int csiphy_lanes_enable(struct csiphy_device *csiphy,
>>> +			       struct csiphy_config *cfg,
>>> +			       s64 link_freq, u8 lane_mask)
>>>    {
>>> +	struct device *dev = csiphy->camss->dev;
>>>    	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
>>>    	struct csiphy_device_regs *regs = csiphy->regs;
>>>    	u8 settle_cnt;
>>>    	u8 val;
>>>    	int i;
>>>
>>>    	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>>>
>>> -	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
>>> -	for (i = 0; i < c->num_data; i++)
>>> -		val |= BIT(c->data[i].pos * 2);
>>> +	val = 0;
>>> +
>>> +	switch (c->phy_cfg) {
>>> +	case V4L2_MBUS_CSI2_CPHY:
>>> +		for (i = 0; i < c->num_data; i++)
>>> +			val |= BIT((c->data[i].pos * 2) + 1);
>>> +		break;
>>> +	case V4L2_MBUS_CSI2_DPHY:
>>> +		val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
>>> +
>>> +		for (i = 0; i < c->num_data; i++)
>>> +			val |= BIT(c->data[i].pos * 2);
>>> +		break;
>>> +	default:
>>> +		dev_err(dev, "Unsupported bus type %d\n", c->phy_cfg);
>>> +		return -EINVAL;
>>
>> If this is the only reason why you're changing the return type to int, I'd
>> suggest using WARN_ON() in this case. I presume it'd take a driver bug for
>> this to trigger?
> 
> Thank you for the review.
> 
> If others agree, I would also prefer WARN_ON instead of changing return values.
> 
> David
> 
> [...]
> 

In the standalone PHY we validate the PHY type in probe :)

WARN_ON() seems fine to me though.


Reviewed-by: Bryan O'Donoghue <bod@kernel.org>

---
bod

Re: [PATCH WIP v5 6/9] media: qcom: camss: csiphy-3ph: Update Gen2 v1.1 MIPI CSI-2 C-PHY init

[Bryan O'Donoghue]

On 31/05/2026 14:08, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
> 
> These values should improve C-PHY behaviour. Should match most recent
> Qualcomm code.
> 
> Acked-by: Cory Keitz <ckeitz@amazon.com>
> Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
>   .../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c   | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index d837fcf7cd2f0..9a0f009c033bb 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -220,19 +220,19 @@ csiphy_lane_regs lane_regs_sdm845[] = {
>   	{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
>   };
> 
>   /* GEN2 1.0 3PH */
>   /* 3 entries: 3 lanes (C-PHY) */
>   static const struct
>   csiphy_lane_regs lane_regs_sdm845_3ph[] = {
> -	{0x015c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
> -	{0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
> -	{0x016c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x015c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x0168, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x016c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>   	{0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>   	{0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
> @@ -240,19 +240,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] = {
>   	{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x01dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
> 
> -	{0x035c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
> -	{0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
> -	{0x036c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x035c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x0368, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x036c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>   	{0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>   	{0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
> @@ -260,19 +260,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] = {
>   	{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x03dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
> 
> -	{0x055c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
> -	{0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
> -	{0x056c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x055c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x0568, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
> +	{0x056c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>   	{0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>   	{0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>   	{0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
> 
> --
> 2.53.0
> 
> 
> 

Squash this down !

---
bod

Re: [PATCH WIP v5 9/9] media: qcom: camss: Enable C-PHY where available

[Bryan O'Donoghue]

On 31/05/2026 14:08, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
> 
> After all the changes done we can now safely enable C-PHY for a SoC
> where it's available.
> 
> Acked-by: Cory Keitz <ckeitz@amazon.com>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
>   drivers/media/platform/qcom/camss/camss.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index db4e14a84a95f..555c53343a1e9 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -4761,21 +4761,21 @@ static int camss_parse_endpoint_node(struct device *dev,
>   	struct v4l2_fwnode_endpoint vep = { { 0 } };
>   	unsigned int i;
>   	int ret;
> 
>   	ret = v4l2_fwnode_endpoint_parse(ep, &vep);
>   	if (ret)
>   		return ret;
> 
> -	/*
> -	 * Most SoCs support both D-PHY and C-PHY standards, but currently only
> -	 * D-PHY is supported in the driver.
> -	 */
> -	if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) {
> +	switch (vep.bus_type) {
> +	case V4L2_MBUS_CSI2_CPHY:
> +	case V4L2_MBUS_CSI2_DPHY:
> +		break;
> +	default:
>   		dev_err(dev, "Unsupported bus type %d\n", vep.bus_type);
>   		return -EINVAL;
>   	}
> 
>   	csd->interface.csiphy_id = vep.base.port;
> 
>   	mipi_csi2 = &vep.bus.mipi_csi2;
>   	lncfg->num_data = mipi_csi2->num_data_lanes;
> 
> --
> 2.53.0
> 
> 
> 


Reviewed-by: Bryan O'Donoghue <bod@kernel.org>

---
bod

Re: [PATCH WIP v5 6/9] media: qcom: camss: csiphy-3ph: Update Gen2 v1.1 MIPI CSI-2 C-PHY init

[David Heidelberg]

On 01/06/2026 18:03, Bryan O'Donoghue wrote:
> On 31/05/2026 14:08, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> These values should improve C-PHY behaviour. Should match most recent
>> Qualcomm code.
>>
>> Acked-by: Cory Keitz <ckeitz@amazon.com>
>> Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>>    .../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c   | 18 +++++++++---------
>>    1 file changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> index d837fcf7cd2f0..9a0f009c033bb 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> @@ -220,19 +220,19 @@ csiphy_lane_regs lane_regs_sdm845[] = {
>>    	{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    };
>>
>>    /* GEN2 1.0 3PH */
>>    /* 3 entries: 3 lanes (C-PHY) */
>>    static const struct
>>    csiphy_lane_regs lane_regs_sdm845_3ph[] = {
>> -	{0x015c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
>> -	{0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
>> -	{0x016c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x015c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x0168, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x016c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>>    	{0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>>    	{0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> @@ -240,19 +240,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] = {
>>    	{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x01dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
>>
>> -	{0x035c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
>> -	{0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
>> -	{0x036c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x035c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x0368, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x036c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>>    	{0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>>    	{0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> @@ -260,19 +260,19 @@ csiphy_lane_regs lane_regs_sdm845_3ph[] = {
>>    	{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x03dc, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
>>
>> -	{0x055c, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
>> -	{0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
>> -	{0x056c, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x055c, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x0568, 0xac, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{0x056c, 0xa5, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>>    	{0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>>    	{0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>>    	{0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>>
>> --
>> 2.53.0
>>
>>
>>
> 
> Squash this down !

Document the regs !

But now seriously - it's nice to have at least commit documenting what these 
change doing.

In previous discussion [1] we agreed on keeping this commit.

David

[1] 
https://lore.kernel.org/linux-media/be4abbc8-414a-429d-baff-48c829378a31@linaro.org/

> 
> ---
> bod
> 

-- 
David Heidelberg