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From: Dave Jiang <dave.jiang@intel.com>
To: Anisa Su <anisa.su887@gmail.com>,
	linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: nvdimm@lists.linux.dev, Dan Williams <djbw@kernel.org>,
	Jonathan Cameron <jic23@kernel.org>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <iweiny@kernel.org>,
	Alison Schofield <alison.schofield@intel.com>,
	John Groves <John@Groves.net>, Gregory Price <gourry@gourry.net>,
	Ira Weiny <ira.weiny@intel.com>
Subject: Re: [PATCH v10 04/31] cxl/core: Enforce partition order/simplify partition calls
Date: Wed, 27 May 2026 16:37:11 -0700	[thread overview]
Message-ID: <c1f55b99-31d2-4c5f-9f22-05f363e31e5b@intel.com> (raw)
In-Reply-To: <22ae445b8a99d26299520e2429c5bf4e64b0d9e6.1779528761.git.anisa.su@samsung.com>



On 5/23/26 2:42 AM, Anisa Su wrote:
> From: Ira Weiny <ira.weiny@intel.com>
> 
> Device partitions have an implied order which is made more complex by
> the addition of a dynamic partition.
> 
> Remove the ram special case information calls in favor of generic calls
> with a check ahead of time to ensure the preservation of the implied
> partition order.
> 
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> 
> ---
> Changes::
> [anisa: rebase]
> [davidlohr: core/hdm.c: return -EINVAL instead of 0 in cxl_dpa_setup
> if partitions are out of order]
> ---
>  drivers/cxl/core/hdm.c    | 11 ++++++++++-
>  drivers/cxl/core/memdev.c | 32 +++++++++-----------------------
>  drivers/cxl/cxlmem.h      |  9 +++------
>  drivers/cxl/mem.c         |  2 +-
>  4 files changed, 23 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 28974adaab75..7a5812971f8f 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -464,6 +464,7 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode)
>  int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
>  {
>  	struct device *dev = cxlds->dev;
> +	int i;
>  
>  	guard(rwsem_write)(&cxl_rwsem.dpa);
>  
> @@ -476,9 +477,17 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info)
>  		return 0;
>  	}
>  
> +	/* Verify partitions are in expected order. */
> +	for (i = 1; i < info->nr_partitions; i++) {
> +		if (cxlds->part[i].mode < cxlds->part[i-1].mode) {

I think we need to check info->part[i].mode and not cxlds here. cxlds mode is assigned later in this function.

DJ


> +			dev_err(dev, "Partition order mismatch\n");
> +			return -EINVAL;
> +		}
> +	}
> +
>  	cxlds->dpa_res = DEFINE_RES_MEM(0, info->size);
>  
> -	for (int i = 0; i < info->nr_partitions; i++) {
> +	for (i = 0; i < info->nr_partitions; i++) {
>  		const struct cxl_dpa_part_info *part = &info->part[i];
>  		int rc;
>  
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 80e65690eb77..71602820f896 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -75,20 +75,12 @@ static ssize_t label_storage_size_show(struct device *dev,
>  }
>  static DEVICE_ATTR_RO(label_storage_size);
>  
> -static resource_size_t cxl_ram_size(struct cxl_dev_state *cxlds)
> -{
> -	/* Static RAM is only expected at partition 0. */
> -	if (cxlds->part[0].mode != CXL_PARTMODE_RAM)
> -		return 0;
> -	return resource_size(&cxlds->part[0].res);
> -}
> -
>  static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr,
>  			     char *buf)
>  {
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>  	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> -	unsigned long long len = cxl_ram_size(cxlds);
> +	unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_RAM);
>  
>  	return sysfs_emit(buf, "%#llx\n", len);
>  }
> @@ -101,7 +93,7 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
>  {
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>  	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> -	unsigned long long len = cxl_pmem_size(cxlds);
> +	unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_PMEM);
>  
>  	return sysfs_emit(buf, "%#llx\n", len);
>  }
> @@ -424,10 +416,11 @@ static struct attribute *cxl_memdev_attributes[] = {
>  	NULL,
>  };
>  
> -static struct cxl_dpa_perf *to_pmem_perf(struct cxl_dev_state *cxlds)
> +static struct cxl_dpa_perf *part_perf(struct cxl_dev_state *cxlds,
> +				      enum cxl_partition_mode mode)
>  {
>  	for (int i = 0; i < cxlds->nr_partitions; i++)
> -		if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
> +		if (cxlds->part[i].mode == mode)
>  			return &cxlds->part[i].perf;
>  	return NULL;
>  }
> @@ -438,7 +431,7 @@ static ssize_t pmem_qos_class_show(struct device *dev,
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>  	struct cxl_dev_state *cxlds = cxlmd->cxlds;
>  
> -	return sysfs_emit(buf, "%d\n", to_pmem_perf(cxlds)->qos_class);
> +	return sysfs_emit(buf, "%d\n", part_perf(cxlds, CXL_PARTMODE_PMEM)->qos_class);
>  }
>  
>  static struct device_attribute dev_attr_pmem_qos_class =
> @@ -450,20 +443,13 @@ static struct attribute *cxl_memdev_pmem_attributes[] = {
>  	NULL,
>  };
>  
> -static struct cxl_dpa_perf *to_ram_perf(struct cxl_dev_state *cxlds)
> -{
> -	if (cxlds->part[0].mode != CXL_PARTMODE_RAM)
> -		return NULL;
> -	return &cxlds->part[0].perf;
> -}
> -
>  static ssize_t ram_qos_class_show(struct device *dev,
>  				  struct device_attribute *attr, char *buf)
>  {
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>  	struct cxl_dev_state *cxlds = cxlmd->cxlds;
>  
> -	return sysfs_emit(buf, "%d\n", to_ram_perf(cxlds)->qos_class);
> +	return sysfs_emit(buf, "%d\n", part_perf(cxlds, CXL_PARTMODE_RAM)->qos_class);
>  }
>  
>  static struct device_attribute dev_attr_ram_qos_class =
> @@ -499,7 +485,7 @@ static umode_t cxl_ram_visible(struct kobject *kobj, struct attribute *a, int n)
>  {
>  	struct device *dev = kobj_to_dev(kobj);
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> -	struct cxl_dpa_perf *perf = to_ram_perf(cxlmd->cxlds);
> +	struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_RAM);
>  
>  	if (a == &dev_attr_ram_qos_class.attr &&
>  	    (!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
> @@ -518,7 +504,7 @@ static umode_t cxl_pmem_visible(struct kobject *kobj, struct attribute *a, int n
>  {
>  	struct device *dev = kobj_to_dev(kobj);
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> -	struct cxl_dpa_perf *perf = to_pmem_perf(cxlmd->cxlds);
> +	struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_PMEM);
>  
>  	if (a == &dev_attr_pmem_qos_class.attr &&
>  	    (!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index cee936fb3d03..10175ca3b7ee 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -383,14 +383,11 @@ struct cxl_security_state {
>  
>  #define CXL_MAX_DC_PARTITIONS 8
>  
> -static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
> +static inline resource_size_t cxl_part_size(struct cxl_dev_state *cxlds,
> +					    enum cxl_partition_mode mode)
>  {
> -	/*
> -	 * Static PMEM may be at partition index 0 when there is no static RAM
> -	 * capacity.
> -	 */
>  	for (int i = 0; i < cxlds->nr_partitions; i++)
> -		if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
> +		if (cxlds->part[i].mode == mode)
>  			return resource_size(&cxlds->part[i].res);
>  	return 0;
>  }
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index fcffe24dcb42..f19e08279ec7 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -114,7 +114,7 @@ static int cxl_mem_probe(struct device *dev)
>  		return -ENXIO;
>  	}
>  
> -	if (cxl_pmem_size(cxlds) && IS_ENABLED(CONFIG_CXL_PMEM)) {
> +	if (cxl_part_size(cxlds, CXL_PARTMODE_PMEM) && IS_ENABLED(CONFIG_CXL_PMEM)) {
>  		rc = devm_cxl_add_nvdimm(dev, parent_port, cxlmd);
>  		if (rc) {
>  			if (rc == -ENODEV)


  reply	other threads:[~2026-05-27 23:37 UTC|newest]

Thread overview: 95+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-23  9:42 [PATCH v10 00/31] DCD: Add support for Dynamic Capacity Devices (DCD) Anisa Su
2026-05-23  9:42 ` [PATCH v10 01/31] cxl/mbox: Flag " Anisa Su
2026-05-27 21:34   ` Dave Jiang
2026-05-30  6:22     ` Anisa Su
2026-05-23  9:42 ` [PATCH v10 02/31] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-05-27 22:28   ` Dave Jiang
2026-05-30  6:40     ` Anisa Su
2026-06-01 15:23       ` Dave Jiang
2026-06-02  9:46         ` Anisa Su
2026-05-23  9:42 ` [PATCH v10 03/31] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-05-27 23:16   ` Dave Jiang
2026-05-30  6:45     ` Anisa Su
2026-05-23  9:42 ` [PATCH v10 04/31] cxl/core: Enforce partition order/simplify partition calls Anisa Su
2026-05-27 23:37   ` Dave Jiang [this message]
2026-05-30  6:57     ` Anisa Su
2026-05-23  9:42 ` [PATCH v10 05/31] cxl/mem: Expose dynamic ram A partition in sysfs Anisa Su
2026-05-27 23:54   ` Dave Jiang
2026-05-27 23:56   ` Dave Jiang
2026-05-30  7:04     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 06/31] cxl/port: Add 'dynamic_ram_a' to endpoint decoder mode Anisa Su
2026-05-28  0:01   ` Dave Jiang
2026-05-30  7:07     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 07/31] cxl/region: Add DC DAX region support Anisa Su
2026-05-28  0:16   ` Dave Jiang
2026-06-02  9:22     ` Anisa Su
2026-06-02 15:42       ` Dave Jiang
2026-06-18 20:21   ` Alison Schofield
2026-05-23  9:43 ` [PATCH v10 08/31] cxl/events: Split event msgnum configuration from irq setup Anisa Su
2026-05-23  9:43 ` [PATCH v10 09/31] cxl/pci: Factor out interrupt policy check Anisa Su
2026-05-23  9:43 ` [PATCH v10 10/31] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-05-28 16:21   ` Dave Jiang
2026-06-08  8:16     ` Anisa Su
2026-06-10 16:57       ` Dave Jiang
2026-06-11 18:19         ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 11/31] cxl/core: Return endpoint decoder information from region search Anisa Su
2026-05-23  9:43 ` [PATCH v10 12/31] cxl/mem: Set up framework for handling DC Events Anisa Su
2026-05-28 16:40   ` Dave Jiang
2026-06-09 17:34     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 13/31] cxl/mem: Add 20 second timeout for stalled DC_ADD_CAPACITY chains Anisa Su
2026-05-28 16:57   ` Dave Jiang
2026-06-09 17:36     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 14/31] cxl/extent: Handle DC Add Capacity events Anisa Su
2026-05-28 19:06   ` Dave Jiang
2026-06-10  3:48     ` Anisa Su
2026-06-24  9:16   ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 15/31] cxl/mem: Drop misaligned DCD extent groups Anisa Su
2026-05-28 21:03   ` Dave Jiang
2026-06-11  6:22     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 16/31] cxl/extent: Validate DC extent partition Anisa Su
2026-05-28 21:34   ` Dave Jiang
2026-06-11  7:35     ` Anisa Su
2026-06-24  9:04   ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 17/31] cxl/mem: Enforce tag-group semantics Anisa Su
2026-05-23  9:43 ` [PATCH v10 18/31] cxl/extent: Handle DC Release Capacity events Anisa Su
2026-05-28 22:13   ` Dave Jiang
2026-06-12  5:56     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 19/31] cxl/extent: Enforce cross-region tag uniqueness Anisa Su
2026-05-28 22:44   ` Dave Jiang
2026-05-23  9:43 ` [PATCH v10 20/31] cxl/region/extent: Expose dc_extent information in sysfs Anisa Su
2026-05-28 22:54   ` Dave Jiang
2026-06-12  5:58     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 21/31] cxl + dax: Surface dax_resources on DCD Add Capacity events Anisa Su
2026-05-28 23:41   ` Dave Jiang
2026-06-16  8:44     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 22/31] cxl + dax: Release dax_resources on DCD Release " Anisa Su
2026-05-28 23:53   ` Dave Jiang
2026-06-16  8:52     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 23/31] dax/bus: Factor out dev dax resize logic Anisa Su
2026-06-24  8:36   ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 24/31] dax/bus: Add uuid sysfs attribute to dax devices Anisa Su
2026-05-29 17:07   ` Dave Jiang
2026-05-23  9:43 ` [PATCH v10 25/31] dax/bus: Reject resize on DC dax devices and enforce 0-size creation Anisa Su
2026-05-29 17:16   ` Dave Jiang
2026-06-16  8:54     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 26/31] dax/bus: Tag-aware uuid claim and show on DC dax devices Anisa Su
2026-05-29 17:53   ` Dave Jiang
2026-06-16  9:01     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 27/31] cxl/region: Read existing extents on region creation Anisa Su
2026-05-29 21:30   ` Dave Jiang
2026-06-16  9:39     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 28/31] cxl/mem: Trace Dynamic capacity Event Record Anisa Su
2026-05-29 22:41   ` Dave Jiang
2026-06-16  9:59     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 29/31] tools/testing/cxl: Make event logs dynamic Anisa Su
2026-05-29 22:58   ` Dave Jiang
2026-06-16 10:29     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 30/31] tools/testing/cxl: Add DC Regions to mock mem data Anisa Su
2026-05-29 23:42   ` Dave Jiang
2026-06-25 11:22     ` Anisa Su
2026-05-23  9:43 ` [PATCH v10 31/31] Documentation/cxl: Document DCD extent handling and DC-backed DAX regions Anisa Su
2026-05-27 18:51 ` [PATCH v10 00/31] DCD: Add support for Dynamic Capacity Devices (DCD) Dave Jiang
2026-05-30  0:16   ` Anisa Su
2026-06-05  5:35 ` Alison Schofield
2026-06-08  7:54   ` Anisa Su
2026-06-24  7:49 ` Anisa Su

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