From: Dave Jiang <dave.jiang@intel.com>
To: Anisa Su <anisa.su887@gmail.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: nvdimm@lists.linux.dev, Dan Williams <djbw@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <iweiny@kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
John Groves <John@Groves.net>, Gregory Price <gourry@gourry.net>,
Ira Weiny <ira.weiny@intel.com>
Subject: Re: [PATCH v10 06/31] cxl/port: Add 'dynamic_ram_a' to endpoint decoder mode
Date: Wed, 27 May 2026 17:01:44 -0700 [thread overview]
Message-ID: <e504359a-ff13-4ad1-a74c-337ede7f11c6@intel.com> (raw)
In-Reply-To: <58e5e5007cd11e0b8e65016f126144f187badb39.1779528761.git.anisa.su@samsung.com>
On 5/23/26 2:43 AM, Anisa Su wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> Endpoints can now support a single dynamic ram partition following the
> persistent memory partition.
>
> Expand the mode to allow a decoder to point to the first dynamic ram
> partition.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Need Anisa sign off
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Just update kver and dates below.
>
> ---
> Changes:
> [anisa: rebase]
> ---
> Documentation/ABI/testing/sysfs-bus-cxl | 18 +++++++++---------
> drivers/cxl/core/port.c | 4 ++++
> 2 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index 3d95c325f6e0..c604c7ca6432 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -358,22 +358,22 @@ Description:
>
>
> What: /sys/bus/cxl/devices/decoderX.Y/mode
> -Date: May, 2022
> -KernelVersion: v6.0
> +Date: May, 2022, May 2025
A later date
> +KernelVersion: v6.0, v6.16 (dynamic_ram_a)
7.3 maybe?
DJ
> Contact: linux-cxl@vger.kernel.org
> Description:
> (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
> translates from a host physical address range, to a device
> local address range. Device-local address ranges are further
> - split into a 'ram' (volatile memory) range and 'pmem'
> - (persistent memory) range. The 'mode' attribute emits one of
> - 'ram', 'pmem', or 'none'. The 'none' indicates the decoder is
> - not actively decoding, or no DPA allocation policy has been
> - set.
> + split into a 'ram' (volatile memory) range, 'pmem' (persistent
> + memory), and 'dynamic_ram_a' (first Dynamic RAM) range. The
> + 'mode' attribute emits one of 'ram', 'pmem', 'dynamic_ram_a' or
> + 'none'. The 'none' indicates the decoder is not actively
> + decoding, or no DPA allocation policy has been set.
>
> 'mode' can be written, when the decoder is in the 'disabled'
> - state, with either 'ram' or 'pmem' to set the boundaries for the
> - next allocation.
> + state, with either 'ram', 'pmem', or 'dynamic_ram_a' to set the
> + boundaries for the next allocation.
>
>
> What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 0c5957d1d329..a7f71f36531f 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -128,6 +128,7 @@ static DEVICE_ATTR_RO(name)
>
> CXL_DECODER_FLAG_ATTR(cap_pmem, CXL_DECODER_F_PMEM);
> CXL_DECODER_FLAG_ATTR(cap_ram, CXL_DECODER_F_RAM);
> +CXL_DECODER_FLAG_ATTR(cap_dynamic_ram_a, CXL_DECODER_F_RAM);
> CXL_DECODER_FLAG_ATTR(cap_type2, CXL_DECODER_F_TYPE2);
> CXL_DECODER_FLAG_ATTR(cap_type3, CXL_DECODER_F_TYPE3);
> CXL_DECODER_FLAG_ATTR(locked, CXL_DECODER_F_LOCK);
> @@ -222,6 +223,8 @@ static ssize_t mode_store(struct device *dev, struct device_attribute *attr,
> mode = CXL_PARTMODE_PMEM;
> else if (sysfs_streq(buf, "ram"))
> mode = CXL_PARTMODE_RAM;
> + else if (sysfs_streq(buf, "dynamic_ram_a"))
> + mode = CXL_PARTMODE_DYNAMIC_RAM_A;
> else
> return -EINVAL;
>
> @@ -327,6 +330,7 @@ static struct attribute_group cxl_decoder_base_attribute_group = {
> static struct attribute *cxl_decoder_root_attrs[] = {
> &dev_attr_cap_pmem.attr,
> &dev_attr_cap_ram.attr,
> + &dev_attr_cap_dynamic_ram_a.attr,
> &dev_attr_cap_type2.attr,
> &dev_attr_cap_type3.attr,
> &dev_attr_target_list.attr,
next prev parent reply other threads:[~2026-05-28 0:01 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-23 9:42 [PATCH v10 00/31] DCD: Add support for Dynamic Capacity Devices (DCD) Anisa Su
2026-05-23 9:42 ` [PATCH v10 01/31] cxl/mbox: Flag " Anisa Su
2026-05-27 21:34 ` Dave Jiang
2026-05-30 6:22 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 02/31] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-05-27 22:28 ` Dave Jiang
2026-05-30 6:40 ` Anisa Su
2026-06-01 15:23 ` Dave Jiang
2026-06-02 9:46 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 03/31] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-05-27 23:16 ` Dave Jiang
2026-05-30 6:45 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 04/31] cxl/core: Enforce partition order/simplify partition calls Anisa Su
2026-05-27 23:37 ` Dave Jiang
2026-05-30 6:57 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 05/31] cxl/mem: Expose dynamic ram A partition in sysfs Anisa Su
2026-05-27 23:54 ` Dave Jiang
2026-05-27 23:56 ` Dave Jiang
2026-05-30 7:04 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 06/31] cxl/port: Add 'dynamic_ram_a' to endpoint decoder mode Anisa Su
2026-05-28 0:01 ` Dave Jiang [this message]
2026-05-30 7:07 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 07/31] cxl/region: Add DC DAX region support Anisa Su
2026-05-28 0:16 ` Dave Jiang
2026-06-02 9:22 ` Anisa Su
2026-06-02 15:42 ` Dave Jiang
2026-06-18 20:21 ` Alison Schofield
2026-05-23 9:43 ` [PATCH v10 08/31] cxl/events: Split event msgnum configuration from irq setup Anisa Su
2026-05-23 9:43 ` [PATCH v10 09/31] cxl/pci: Factor out interrupt policy check Anisa Su
2026-05-23 9:43 ` [PATCH v10 10/31] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-05-28 16:21 ` Dave Jiang
2026-06-08 8:16 ` Anisa Su
2026-06-10 16:57 ` Dave Jiang
2026-06-11 18:19 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 11/31] cxl/core: Return endpoint decoder information from region search Anisa Su
2026-05-23 9:43 ` [PATCH v10 12/31] cxl/mem: Set up framework for handling DC Events Anisa Su
2026-05-28 16:40 ` Dave Jiang
2026-06-09 17:34 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 13/31] cxl/mem: Add 20 second timeout for stalled DC_ADD_CAPACITY chains Anisa Su
2026-05-28 16:57 ` Dave Jiang
2026-06-09 17:36 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 14/31] cxl/extent: Handle DC Add Capacity events Anisa Su
2026-05-28 19:06 ` Dave Jiang
2026-06-10 3:48 ` Anisa Su
2026-06-24 9:16 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 15/31] cxl/mem: Drop misaligned DCD extent groups Anisa Su
2026-05-28 21:03 ` Dave Jiang
2026-06-11 6:22 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 16/31] cxl/extent: Validate DC extent partition Anisa Su
2026-05-28 21:34 ` Dave Jiang
2026-06-11 7:35 ` Anisa Su
2026-06-24 9:04 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 17/31] cxl/mem: Enforce tag-group semantics Anisa Su
2026-05-23 9:43 ` [PATCH v10 18/31] cxl/extent: Handle DC Release Capacity events Anisa Su
2026-05-28 22:13 ` Dave Jiang
2026-06-12 5:56 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 19/31] cxl/extent: Enforce cross-region tag uniqueness Anisa Su
2026-05-28 22:44 ` Dave Jiang
2026-05-23 9:43 ` [PATCH v10 20/31] cxl/region/extent: Expose dc_extent information in sysfs Anisa Su
2026-05-28 22:54 ` Dave Jiang
2026-06-12 5:58 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 21/31] cxl + dax: Surface dax_resources on DCD Add Capacity events Anisa Su
2026-05-28 23:41 ` Dave Jiang
2026-06-16 8:44 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 22/31] cxl + dax: Release dax_resources on DCD Release " Anisa Su
2026-05-28 23:53 ` Dave Jiang
2026-06-16 8:52 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 23/31] dax/bus: Factor out dev dax resize logic Anisa Su
2026-06-24 8:36 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 24/31] dax/bus: Add uuid sysfs attribute to dax devices Anisa Su
2026-05-29 17:07 ` Dave Jiang
2026-05-23 9:43 ` [PATCH v10 25/31] dax/bus: Reject resize on DC dax devices and enforce 0-size creation Anisa Su
2026-05-29 17:16 ` Dave Jiang
2026-06-16 8:54 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 26/31] dax/bus: Tag-aware uuid claim and show on DC dax devices Anisa Su
2026-05-29 17:53 ` Dave Jiang
2026-06-16 9:01 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 27/31] cxl/region: Read existing extents on region creation Anisa Su
2026-05-29 21:30 ` Dave Jiang
2026-06-16 9:39 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 28/31] cxl/mem: Trace Dynamic capacity Event Record Anisa Su
2026-05-29 22:41 ` Dave Jiang
2026-06-16 9:59 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 29/31] tools/testing/cxl: Make event logs dynamic Anisa Su
2026-05-29 22:58 ` Dave Jiang
2026-06-16 10:29 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 30/31] tools/testing/cxl: Add DC Regions to mock mem data Anisa Su
2026-05-29 23:42 ` Dave Jiang
2026-06-25 11:22 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 31/31] Documentation/cxl: Document DCD extent handling and DC-backed DAX regions Anisa Su
2026-05-27 18:51 ` [PATCH v10 00/31] DCD: Add support for Dynamic Capacity Devices (DCD) Dave Jiang
2026-05-30 0:16 ` Anisa Su
2026-06-05 5:35 ` Alison Schofield
2026-06-08 7:54 ` Anisa Su
2026-06-24 7:49 ` Anisa Su
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