From: Dave Jiang <dave.jiang@intel.com>
To: Anisa Su <anisa.su887@gmail.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: nvdimm@lists.linux.dev, Dan Williams <djbw@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <iweiny@kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
John Groves <John@Groves.net>, Gregory Price <gourry@gourry.net>,
Ira Weiny <ira.weiny@intel.com>
Subject: Re: [PATCH v10 05/31] cxl/mem: Expose dynamic ram A partition in sysfs
Date: Wed, 27 May 2026 16:56:34 -0700 [thread overview]
Message-ID: <df99e0c6-e571-4dba-a8c4-2a8ecbb47c34@intel.com> (raw)
In-Reply-To: <45bc277b11c1aabf495132925c0d75c78e3b5a8a.1779528761.git.anisa.su@samsung.com>
On 5/23/26 2:42 AM, Anisa Su wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> To properly configure CXL regions user space will need to know the
> details of the dynamic ram partition.
>
> Expose the first dynamic ram partition through sysfs.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
>
> ---
> Changes:
> [anisa: Update kernel version to 7.0]
> [davidlohr: Remove "persistent" from description of
> /sys/bus/cxl/devices/memX/dynamic_ram_a/qos_class]
> ---
> Documentation/ABI/testing/sysfs-bus-cxl | 24 +++++++++++
> drivers/cxl/core/memdev.c | 57 +++++++++++++++++++++++++
> 2 files changed, 81 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index 16a9b3d2e2c0..3d95c325f6e0 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -89,6 +89,30 @@ Description:
> and there are platform specific performance related
> side-effects that may result. First class-id is displayed.
>
> +What: /sys/bus/cxl/devices/memX/dynamic_ram_a/size
> +Date: May, 2025
> +KernelVersion: v7.0
Probably should update this to 7.3 maybe?
DJ
> +Contact: linux-cxl@vger.kernel.org
> +Description:
> + (RO) The first Dynamic RAM partition capacity as bytes.
> +
> +
> +What: /sys/bus/cxl/devices/memX/dynamic_ram_a/qos_class
> +Date: May, 2025
> +KernelVersion: v7.0
> +Contact: linux-cxl@vger.kernel.org
> +Description:
> + (RO) For CXL host platforms that support "QoS Telemmetry"
> + this attribute conveys a comma delimited list of platform
> + specific cookies that identifies a QoS performance class
> + for the partition of the CXL mem device. These
> + class-ids can be compared against a similar "qos_class"
> + published for a root decoder. While it is not required
> + that the endpoints map their local memory-class to a
> + matching platform class, mismatches are not recommended
> + and there are platform specific performance related
> + side-effects that may result. First class-id is displayed.
> +
>
> What: /sys/bus/cxl/devices/memX/serial
> Date: January, 2022
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 71602820f896..064cfd628577 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -101,6 +101,19 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
> static struct device_attribute dev_attr_pmem_size =
> __ATTR(size, 0444, pmem_size_show, NULL);
>
> +static ssize_t dynamic_ram_a_size_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> + unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_DYNAMIC_RAM_A);
> +
> + return sysfs_emit(buf, "%#llx\n", len);
> +}
> +
> +static struct device_attribute dev_attr_dynamic_ram_a_size =
> + __ATTR(size, 0444, dynamic_ram_a_size_show, NULL);
> +
> static ssize_t serial_show(struct device *dev, struct device_attribute *attr,
> char *buf)
> {
> @@ -443,6 +456,25 @@ static struct attribute *cxl_memdev_pmem_attributes[] = {
> NULL,
> };
>
> +static ssize_t dynamic_ram_a_qos_class_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> +
> + return sysfs_emit(buf, "%d\n",
> + part_perf(cxlds, CXL_PARTMODE_DYNAMIC_RAM_A)->qos_class);
> +}
> +
> +static struct device_attribute dev_attr_dynamic_ram_a_qos_class =
> + __ATTR(qos_class, 0444, dynamic_ram_a_qos_class_show, NULL);
> +
> +static struct attribute *cxl_memdev_dynamic_ram_a_attributes[] = {
> + &dev_attr_dynamic_ram_a_size.attr,
> + &dev_attr_dynamic_ram_a_qos_class.attr,
> + NULL,
> +};
> +
> static ssize_t ram_qos_class_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> {
> @@ -519,6 +551,29 @@ static struct attribute_group cxl_memdev_pmem_attribute_group = {
> .is_visible = cxl_pmem_visible,
> };
>
> +static umode_t cxl_dynamic_ram_a_visible(struct kobject *kobj, struct attribute *a, int n)
> +{
> + struct device *dev = kobj_to_dev(kobj);
> + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> + struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_DYNAMIC_RAM_A);
> +
> + if (a == &dev_attr_dynamic_ram_a_qos_class.attr &&
> + (!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
> + return 0;
> +
> + if (a == &dev_attr_dynamic_ram_a_size.attr &&
> + (!cxl_part_size(cxlmd->cxlds, CXL_PARTMODE_DYNAMIC_RAM_A)))
> + return 0;
> +
> + return a->mode;
> +}
> +
> +static struct attribute_group cxl_memdev_dynamic_ram_a_attribute_group = {
> + .name = "dynamic_ram_a",
> + .attrs = cxl_memdev_dynamic_ram_a_attributes,
> + .is_visible = cxl_dynamic_ram_a_visible,
> +};
> +
> static umode_t cxl_memdev_security_visible(struct kobject *kobj,
> struct attribute *a, int n)
> {
> @@ -547,6 +602,7 @@ static const struct attribute_group *cxl_memdev_attribute_groups[] = {
> &cxl_memdev_attribute_group,
> &cxl_memdev_ram_attribute_group,
> &cxl_memdev_pmem_attribute_group,
> + &cxl_memdev_dynamic_ram_a_attribute_group,
> &cxl_memdev_security_attribute_group,
> NULL,
> };
> @@ -555,6 +611,7 @@ void cxl_memdev_update_perf(struct cxl_memdev *cxlmd)
> {
> sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_ram_attribute_group);
> sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_pmem_attribute_group);
> + sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_dynamic_ram_a_attribute_group);
> }
> EXPORT_SYMBOL_NS_GPL(cxl_memdev_update_perf, "CXL");
>
next prev parent reply other threads:[~2026-05-27 23:56 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-23 9:42 [PATCH v10 00/31] DCD: Add support for Dynamic Capacity Devices (DCD) Anisa Su
2026-05-23 9:42 ` [PATCH v10 01/31] cxl/mbox: Flag " Anisa Su
2026-05-27 21:34 ` Dave Jiang
2026-05-30 6:22 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 02/31] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-05-27 22:28 ` Dave Jiang
2026-05-30 6:40 ` Anisa Su
2026-06-01 15:23 ` Dave Jiang
2026-06-02 9:46 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 03/31] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-05-27 23:16 ` Dave Jiang
2026-05-30 6:45 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 04/31] cxl/core: Enforce partition order/simplify partition calls Anisa Su
2026-05-27 23:37 ` Dave Jiang
2026-05-30 6:57 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 05/31] cxl/mem: Expose dynamic ram A partition in sysfs Anisa Su
2026-05-27 23:54 ` Dave Jiang
2026-05-27 23:56 ` Dave Jiang [this message]
2026-05-30 7:04 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 06/31] cxl/port: Add 'dynamic_ram_a' to endpoint decoder mode Anisa Su
2026-05-28 0:01 ` Dave Jiang
2026-05-30 7:07 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 07/31] cxl/region: Add DC DAX region support Anisa Su
2026-05-28 0:16 ` Dave Jiang
2026-06-02 9:22 ` Anisa Su
2026-06-02 15:42 ` Dave Jiang
2026-06-18 20:21 ` Alison Schofield
2026-05-23 9:43 ` [PATCH v10 08/31] cxl/events: Split event msgnum configuration from irq setup Anisa Su
2026-05-23 9:43 ` [PATCH v10 09/31] cxl/pci: Factor out interrupt policy check Anisa Su
2026-05-23 9:43 ` [PATCH v10 10/31] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-05-28 16:21 ` Dave Jiang
2026-06-08 8:16 ` Anisa Su
2026-06-10 16:57 ` Dave Jiang
2026-06-11 18:19 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 11/31] cxl/core: Return endpoint decoder information from region search Anisa Su
2026-05-23 9:43 ` [PATCH v10 12/31] cxl/mem: Set up framework for handling DC Events Anisa Su
2026-05-28 16:40 ` Dave Jiang
2026-06-09 17:34 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 13/31] cxl/mem: Add 20 second timeout for stalled DC_ADD_CAPACITY chains Anisa Su
2026-05-28 16:57 ` Dave Jiang
2026-06-09 17:36 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 14/31] cxl/extent: Handle DC Add Capacity events Anisa Su
2026-05-28 19:06 ` Dave Jiang
2026-06-10 3:48 ` Anisa Su
2026-06-24 9:16 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 15/31] cxl/mem: Drop misaligned DCD extent groups Anisa Su
2026-05-28 21:03 ` Dave Jiang
2026-06-11 6:22 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 16/31] cxl/extent: Validate DC extent partition Anisa Su
2026-05-28 21:34 ` Dave Jiang
2026-06-11 7:35 ` Anisa Su
2026-06-24 9:04 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 17/31] cxl/mem: Enforce tag-group semantics Anisa Su
2026-05-23 9:43 ` [PATCH v10 18/31] cxl/extent: Handle DC Release Capacity events Anisa Su
2026-05-28 22:13 ` Dave Jiang
2026-06-12 5:56 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 19/31] cxl/extent: Enforce cross-region tag uniqueness Anisa Su
2026-05-28 22:44 ` Dave Jiang
2026-05-23 9:43 ` [PATCH v10 20/31] cxl/region/extent: Expose dc_extent information in sysfs Anisa Su
2026-05-28 22:54 ` Dave Jiang
2026-06-12 5:58 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 21/31] cxl + dax: Surface dax_resources on DCD Add Capacity events Anisa Su
2026-05-28 23:41 ` Dave Jiang
2026-06-16 8:44 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 22/31] cxl + dax: Release dax_resources on DCD Release " Anisa Su
2026-05-28 23:53 ` Dave Jiang
2026-06-16 8:52 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 23/31] dax/bus: Factor out dev dax resize logic Anisa Su
2026-06-24 8:36 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 24/31] dax/bus: Add uuid sysfs attribute to dax devices Anisa Su
2026-05-29 17:07 ` Dave Jiang
2026-05-23 9:43 ` [PATCH v10 25/31] dax/bus: Reject resize on DC dax devices and enforce 0-size creation Anisa Su
2026-05-29 17:16 ` Dave Jiang
2026-06-16 8:54 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 26/31] dax/bus: Tag-aware uuid claim and show on DC dax devices Anisa Su
2026-05-29 17:53 ` Dave Jiang
2026-06-16 9:01 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 27/31] cxl/region: Read existing extents on region creation Anisa Su
2026-05-29 21:30 ` Dave Jiang
2026-06-16 9:39 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 28/31] cxl/mem: Trace Dynamic capacity Event Record Anisa Su
2026-05-29 22:41 ` Dave Jiang
2026-06-16 9:59 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 29/31] tools/testing/cxl: Make event logs dynamic Anisa Su
2026-05-29 22:58 ` Dave Jiang
2026-06-16 10:29 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 30/31] tools/testing/cxl: Add DC Regions to mock mem data Anisa Su
2026-05-29 23:42 ` Dave Jiang
2026-06-25 11:22 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 31/31] Documentation/cxl: Document DCD extent handling and DC-backed DAX regions Anisa Su
2026-05-27 18:51 ` [PATCH v10 00/31] DCD: Add support for Dynamic Capacity Devices (DCD) Dave Jiang
2026-05-30 0:16 ` Anisa Su
2026-06-05 5:35 ` Alison Schofield
2026-06-08 7:54 ` Anisa Su
2026-06-24 7:49 ` Anisa Su
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