From: Dave Jiang <dave.jiang@intel.com>
To: Anisa Su <anisa.su887@gmail.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: nvdimm@lists.linux.dev, Dan Williams <djbw@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <iweiny@kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
John Groves <John@Groves.net>, Gregory Price <gourry@gourry.net>,
Anisa Su <anisa.su@samsung.com>, Ira Weiny <ira.weiny@intel.com>
Subject: Re: [PATCH v10 16/31] cxl/extent: Validate DC extent partition
Date: Thu, 28 May 2026 14:34:49 -0700 [thread overview]
Message-ID: <dbcfcbe8-5a4a-4b5d-b1f1-188e33eb2a4b@intel.com> (raw)
In-Reply-To: <def526ee51b647e9256c7e777c6b7bd5cd647f89.1779528761.git.anisa.su@samsung.com>
On 5/23/26 2:43 AM, Anisa Su wrote:
> Extend cxl_validate_extent() — the per-extent check of the add pipeline
> to check partition membership.
>
> Resolves an extent's DPA to its containing DC partition. Then based on
> if the partition is shareable:
>
> - Shareable: tag must be non-null and shared_extn_seq must be non-zero
> — multiple hosts reading the same allocation rely on the device-
> stamped 1..n sequence to assemble extents in agreed order.
> - Non-sharable: shared_extn_seq must be zero — sequencing is
> meaningless when only one host consumes the allocation; tag is
> optional (null UUID permitted).
>
> Any cross-mix is a device firmware bug; reject the extent.
>
> Based on patches by John Groves.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: John Groves <John@Groves.net>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
>
> ---
> Changes:
> [anisa: split out as a separate validation step]
> ---
> drivers/cxl/core/core.h | 4 ++
> drivers/cxl/core/extent.c | 78 +++++++++++++++++++++++++++++++++++++--
> 2 files changed, 79 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 1bae80dbf991..30b6b05b155b 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -179,6 +179,10 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c);
> int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
> struct access_coordinate *c);
> void memdev_release_extent(struct cxl_memdev_state *mds, struct range *range);
> +const struct cxl_dpa_partition *
> +cxl_extent_dc_partition(struct cxl_memdev_state *mds,
> + struct cxl_extent *extent,
> + struct range *ext_range);
>
> static inline struct device *port_to_host(struct cxl_port *port)
> {
> diff --git a/drivers/cxl/core/extent.c b/drivers/cxl/core/extent.c
> index 94128d06f4ed..b01507022cff 100644
> --- a/drivers/cxl/core/extent.c
> +++ b/drivers/cxl/core/extent.c
> @@ -63,11 +63,55 @@ alloc_tag_group(struct cxl_dax_region *cxlr_dax, uuid_t *uuid)
> return no_free_ptr(group);
> }
>
> +/*
> + * Find the DC (Dynamic Capacity) partition that fully contains @ext_range,
> + * or NULL if the extent falls outside every DC partition on this memdev.
> + * The returned pointer is owned by mds->cxlds.part[] and lives for the
> + * lifetime of the memdev.
> + */
> +const struct cxl_dpa_partition *
> +cxl_extent_dc_partition(struct cxl_memdev_state *mds,
> + struct cxl_extent *extent,
> + struct range *ext_range)
This can be static, given it's only called in extent.c
> +{
> + struct cxl_dev_state *cxlds = &mds->cxlds;
> + struct device *dev = mds->cxlds.dev;
> +
> + for (int i = 0; i < cxlds->nr_partitions; i++) {
> + struct cxl_dpa_partition *part = &cxlds->part[i];
> + struct range partition_range = {
> + .start = part->res.start,
> + .end = part->res.end,
> + };
> +
> + if (part->mode != CXL_PARTMODE_DYNAMIC_RAM_A)
> + continue;
> +
> + if (range_contains(&partition_range, ext_range)) {
> + dev_dbg(dev, "DC extent DPA %pra (DCR:%pra)(%pU)\n",
> + ext_range, &partition_range, extent->uuid);
> + return part;
> + }
> + }
> +
> + dev_err_ratelimited(dev,
> + "DC extent DPA %pra (%pU) is not in a valid DC partition\n",
> + ext_range, extent->uuid);
> + return NULL;
> +}
> +
> /*
> * Stage 1 of the add pipeline: pure, no allocation. Resolve the extent
> - * to its region/endpoint decoder and ext_range, and verify the range
> - * fits in the resolved endpoint decoder's DPA resource. Further
> - * per-extent invariants layer into this function in subsequent commits.
> + * to its region/endpoint decoder and ext_range, and enforce every
> + * per-extent invariant the device must satisfy:
> + *
> + * - DPA falls inside a Dynamic Capacity partition (cxl_extent_dc_partition).
> + * - CDAT-sharability rules:
> + * sharable: tag must be non-null AND shared_extn_seq != 0
> + * non-sharable: shared_extn_seq must be 0 (tag is optional)
> + * Any cross-mixing is a device firmware bug.
> + * - DPA resolves to an endpoint decoder attached to a region.
> + * - The extent's range is fully contained in that ED's DPA resource.
> *
> * Caller must hold cxl_rwsem.region for read (cxl_dpa_to_region()).
> * On success, @out_cxled / @out_cxlr_dax / @out_ext_range carry the
> @@ -81,6 +125,10 @@ static int cxl_validate_extent(struct cxl_memdev_state *mds,
> {
> u64 start_dpa = le64_to_cpu(extent->start_dpa);
> struct cxl_memdev *cxlmd = mds->cxlds.cxlmd;
> + struct device *dev = mds->cxlds.dev;
> + uuid_t *uuid = (uuid_t *)extent->uuid;
Consider using import_uuid() instead of direct cast.
> + u16 seq = le16_to_cpu(extent->shared_extn_seq);
> + const struct cxl_dpa_partition *part;
> struct cxl_endpoint_decoder *cxled;
> struct cxl_region *cxlr;
> struct range ext_range = (struct range) {
> @@ -89,6 +137,30 @@ static int cxl_validate_extent(struct cxl_memdev_state *mds,
> };
> struct range ed_range;
>
> + part = cxl_extent_dc_partition(mds, extent, &ext_range);
> + if (!part)
> + return -ENXIO;
> +
> + if (part->perf.shareable) {
> + if (uuid_is_null(uuid)) {
> + dev_err_ratelimited(dev,
> + "DC extent DPA %pra: sharable-partition extent has null tag (firmware bug)\n",
> + &ext_range);
> + return -ENXIO;
> + }
> + if (seq == 0) {
I don't think this complies with the spec language. In r4.0 Table 8-230: "For extents describing shareable regions this field shall be within the range of 0 to n-1 where n is the number of extents, with each value appearing only once." So seq == 0 is an acceptable value.
Also, looking at cxl_add_pending() @ line ~1396, does shared seq number '0' holds special meanings? Maybe that needs to change? Also suggest adding comments to point out what's happening there if '0' is special.
DJ
> + dev_err_ratelimited(dev,
> + "DC extent DPA %pra (%pU): sharable-partition extent missing shared_extn_seq (firmware bug)\n",
> + &ext_range, uuid);
> + return -ENXIO;
> + }
> + } else if (seq != 0) {
> + dev_err_ratelimited(dev,
> + "DC extent DPA %pra (%pU): non-sharable partition but shared_extn_seq=%u (firmware bug)\n",
> + &ext_range, uuid, seq);
> + return -ENXIO;
> + }
> +
> cxlr = cxl_dpa_to_region(cxlmd, start_dpa, &cxled);
> if (!cxlr)
> return -ENXIO;
next prev parent reply other threads:[~2026-05-28 21:35 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-23 9:42 [PATCH v10 00/31] DCD: Add support for Dynamic Capacity Devices (DCD) Anisa Su
2026-05-23 9:42 ` [PATCH v10 01/31] cxl/mbox: Flag " Anisa Su
2026-05-27 21:34 ` Dave Jiang
2026-05-30 6:22 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 02/31] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-05-27 22:28 ` Dave Jiang
2026-05-30 6:40 ` Anisa Su
2026-06-01 15:23 ` Dave Jiang
2026-06-02 9:46 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 03/31] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-05-27 23:16 ` Dave Jiang
2026-05-30 6:45 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 04/31] cxl/core: Enforce partition order/simplify partition calls Anisa Su
2026-05-27 23:37 ` Dave Jiang
2026-05-30 6:57 ` Anisa Su
2026-05-23 9:42 ` [PATCH v10 05/31] cxl/mem: Expose dynamic ram A partition in sysfs Anisa Su
2026-05-27 23:54 ` Dave Jiang
2026-05-27 23:56 ` Dave Jiang
2026-05-30 7:04 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 06/31] cxl/port: Add 'dynamic_ram_a' to endpoint decoder mode Anisa Su
2026-05-28 0:01 ` Dave Jiang
2026-05-30 7:07 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 07/31] cxl/region: Add DC DAX region support Anisa Su
2026-05-28 0:16 ` Dave Jiang
2026-06-02 9:22 ` Anisa Su
2026-06-02 15:42 ` Dave Jiang
2026-06-18 20:21 ` Alison Schofield
2026-05-23 9:43 ` [PATCH v10 08/31] cxl/events: Split event msgnum configuration from irq setup Anisa Su
2026-05-23 9:43 ` [PATCH v10 09/31] cxl/pci: Factor out interrupt policy check Anisa Su
2026-05-23 9:43 ` [PATCH v10 10/31] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-05-28 16:21 ` Dave Jiang
2026-06-08 8:16 ` Anisa Su
2026-06-10 16:57 ` Dave Jiang
2026-06-11 18:19 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 11/31] cxl/core: Return endpoint decoder information from region search Anisa Su
2026-05-23 9:43 ` [PATCH v10 12/31] cxl/mem: Set up framework for handling DC Events Anisa Su
2026-05-28 16:40 ` Dave Jiang
2026-06-09 17:34 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 13/31] cxl/mem: Add 20 second timeout for stalled DC_ADD_CAPACITY chains Anisa Su
2026-05-28 16:57 ` Dave Jiang
2026-06-09 17:36 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 14/31] cxl/extent: Handle DC Add Capacity events Anisa Su
2026-05-28 19:06 ` Dave Jiang
2026-06-10 3:48 ` Anisa Su
2026-06-24 9:16 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 15/31] cxl/mem: Drop misaligned DCD extent groups Anisa Su
2026-05-28 21:03 ` Dave Jiang
2026-06-11 6:22 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 16/31] cxl/extent: Validate DC extent partition Anisa Su
2026-05-28 21:34 ` Dave Jiang [this message]
2026-06-11 7:35 ` Anisa Su
2026-06-24 9:04 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 17/31] cxl/mem: Enforce tag-group semantics Anisa Su
2026-05-23 9:43 ` [PATCH v10 18/31] cxl/extent: Handle DC Release Capacity events Anisa Su
2026-05-28 22:13 ` Dave Jiang
2026-06-12 5:56 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 19/31] cxl/extent: Enforce cross-region tag uniqueness Anisa Su
2026-05-28 22:44 ` Dave Jiang
2026-05-23 9:43 ` [PATCH v10 20/31] cxl/region/extent: Expose dc_extent information in sysfs Anisa Su
2026-05-28 22:54 ` Dave Jiang
2026-06-12 5:58 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 21/31] cxl + dax: Surface dax_resources on DCD Add Capacity events Anisa Su
2026-05-28 23:41 ` Dave Jiang
2026-06-16 8:44 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 22/31] cxl + dax: Release dax_resources on DCD Release " Anisa Su
2026-05-28 23:53 ` Dave Jiang
2026-06-16 8:52 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 23/31] dax/bus: Factor out dev dax resize logic Anisa Su
2026-06-24 8:36 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 24/31] dax/bus: Add uuid sysfs attribute to dax devices Anisa Su
2026-05-29 17:07 ` Dave Jiang
2026-05-23 9:43 ` [PATCH v10 25/31] dax/bus: Reject resize on DC dax devices and enforce 0-size creation Anisa Su
2026-05-29 17:16 ` Dave Jiang
2026-06-16 8:54 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 26/31] dax/bus: Tag-aware uuid claim and show on DC dax devices Anisa Su
2026-05-29 17:53 ` Dave Jiang
2026-06-16 9:01 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 27/31] cxl/region: Read existing extents on region creation Anisa Su
2026-05-29 21:30 ` Dave Jiang
2026-06-16 9:39 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 28/31] cxl/mem: Trace Dynamic capacity Event Record Anisa Su
2026-05-29 22:41 ` Dave Jiang
2026-06-16 9:59 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 29/31] tools/testing/cxl: Make event logs dynamic Anisa Su
2026-05-29 22:58 ` Dave Jiang
2026-06-16 10:29 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 30/31] tools/testing/cxl: Add DC Regions to mock mem data Anisa Su
2026-05-29 23:42 ` Dave Jiang
2026-06-25 11:22 ` Anisa Su
2026-05-23 9:43 ` [PATCH v10 31/31] Documentation/cxl: Document DCD extent handling and DC-backed DAX regions Anisa Su
2026-05-27 18:51 ` [PATCH v10 00/31] DCD: Add support for Dynamic Capacity Devices (DCD) Dave Jiang
2026-05-30 0:16 ` Anisa Su
2026-06-05 5:35 ` Alison Schofield
2026-06-08 7:54 ` Anisa Su
2026-06-24 7:49 ` Anisa Su
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